rust/zynq7000-rs
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prepare PAC release #81

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muellerr merged 1 commits from prep-pac-release into main 2026-05-08 17:09:10 +02:00
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+8 -5
5 changed files with 8 additions and 5 deletions
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firmware/zedboard-bsp/Cargo.toml
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@@ -10,7 +10,7 @@ keywords = ["no-std", "zedboard", "bare-metal", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
zynq7000 = { path = "../zynq7000", version = "0.2" }
zynq7000 = { path = "../zynq7000", version = "0.3" }
zynq7000-hal = { path = "../zynq7000-hal", version = "0.1" }
bitbybit = "2"
log = "0.4"
firmware/zynq7000-hal/Cargo.toml
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@@ -12,7 +12,7 @@ categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
aarch32-cpu = { version = "0.3" }
zynq7000 = { path = "../zynq7000", version = "0.2" }
zynq7000 = { path = "../zynq7000", version = "0.3" }
zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }
static_assertions = "1.1"
bitbybit = "2"
firmware/zynq7000/CHANGELOG.md
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@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
# [unreleased]
# [v0.3.0] 2026-05-08
- Better names for various registers. Replaced abbreviations like SR, MR, CR, IER, IMR etc.
# [v0.2.0] 2026-04-01
@@ -28,7 +30,8 @@ Documentation fix
Initial release
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.2.0...HEAD
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.3.0...HEAD
[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.2.0...zynq7000-v0.3.0
[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.0...zynq7000-v0.2.0
[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.0...zynq7000-v0.1.1
[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/tag/zynq7000-v0.1.0
firmware/zynq7000/Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "zynq7000"
version = "0.2.0"
version = "0.3.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2024"
description = "Peripheral Access Crate (PAC) for the Zynq7000 family of SoCs"
host/Cargo.lock
Generated
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@@ -647,7 +647,7 @@ checksum = "d6bbff5f0aada427a1e5a6da5f1f98158182f26556f345ac9e04d36d0ebed650"
[[package]]
name = "zynq7000"
version = "0.2.0"
version = "0.3.0"
dependencies = [
"arbitrary-int 2.0.0",
"bitbybit 2.0.0",