Robin Mueller
dd15acbda3
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63 lines
2.6 KiB
Markdown
63 lines
2.6 KiB
Markdown
Zedboard FPGA design for Rust
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=======
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This is an example/reference design which was used to verify various components provided
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by this library. To minimize the amount of HW designs required, one project is provided.
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The design was kept as generic as possible. In principle, it should be possible to adapt the
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hardware design to other boards with modifications.
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# Pre-Requisites
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- [Vivado installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html)
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or [Vitis installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html)
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which includes Vivado. This example design was created with/for Vivado 2024.1, but also might work
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for newer versions.
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- [Zedboard board files](https://github.com/Digilent/vivado-boards) added to the Vivado installation.
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# Loading the project and the block design with the GUI
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You can load the project using the batch mode of `vivado` inside the folder where you want to
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create the `zedboard-rust` project:
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```sh
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vivado -mode batch -source <path to zedboard-rust.tcl> -tclargs --overwrite
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```
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for example, to create the directory directly insdie this directory:
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```sh
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vivado -mode batch -source zedboard-rust.tcl -tclargs --overwrite
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```
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This should create a `zedboard-rust` Vivado project folder containing a `zedboard-rust.xpr`
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project file. You can load this project file with Vivado:
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```sh
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vivado zedboard-rust.xpr
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```
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You can perform all the steps specified in the Vivado GUI as well using `Execute TCL script` and
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`Load Project`.
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# Generating the SDT folder from a hardware description
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You can generate a hardware description by building the block design by using `Generate Bitstream`
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inside the Vivado GUI and then exporting the hardware description via
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`File -> Export -> Export Hardware`. This allows to generate a `*.xsa` file which describes the
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hardware.
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After that, you can generate the SDT output folder which contains various useful files like
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the `ps7_init.tcl` script. The provided ` sdtgen.tcl` and `stdgen.py` script simplify this process.
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For example, the following command generates the SDT output folder inside a folder
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named `sdt_out` for a hardware description files `zedboard-rust/zedboard-rust.xsa`,
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assuming that the Vitis tool suite is installed at `/tools/Xilinx/Vitis/2024.1`:
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```sh
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export AMD_TOOLS="/tools/Xilinx/Vitis/2024.1"
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./sdtgen.py -x ./zedboard-rust/zedboard-rust.xsa
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```
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Run `stdgen.py -h` for more information and configuration options. The `stdgen.py` is a helper
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script which will invoke `sdtgen.tcl` to generate the SDT.
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