Robin Mueller
5d7f38f41d
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245 lines
7.2 KiB
Rust
245 lines
7.2 KiB
Rust
use arbitrary_int::{u2, u4, u5};
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#[derive(Clone, Debug)]
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pub struct PhyIdentifier {
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pub oui: u32,
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pub model: u8,
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pub rev: u8,
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}
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// Organizational Unique Identifier for Marvell 88E1518 PHY
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const MARVELL_88E1518_OUI: u32 = 0x005043;
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const MARVELL_88E1518_MODELL_NUMBER: u8 = 0b011101;
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#[bitbybit::bitenum(u5, exhaustive = false)]
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pub enum MarvellRegistersPage0 {
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CopperControl = 0,
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CopperStatus = 1,
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IdReg1 = 2,
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IdReg2 = 3,
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CopperSpecificStatus = 17,
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PageSel = 22,
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}
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#[bitbybit::bitfield(u16)]
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pub struct CopperControlRegister {
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#[bit(15, rw)]
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copper_reset: bool,
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#[bit(14, rw)]
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loopback: bool,
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#[bit(12, rw)]
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auto_negotiation_enable: bool,
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#[bit(11, rw)]
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power_down: bool,
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#[bit(10, rw)]
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isolate: bool,
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#[bit(9, rw)]
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restart_auto_negotiation: bool,
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/// 1: Full-duplex, 0: Half-duplex
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#[bit(8, rw)]
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copper_duplex_mode: bool,
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#[bits([13, 6], rw)]
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speed_selection: u2,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum LatchingLinkStatus {
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Up = 1,
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DownSinceLastRead = 0,
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}
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#[bitbybit::bitfield(u16)]
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pub struct CopperStatusRegister {
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/// Always 0, the 100BASE-T4 protocol is not available on Marvell 88E15XX.
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#[bit(15, r)]
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p_100_base_t4: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(14, r)]
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p_100_base_x_full_duplex: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(13, r)]
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p_100_base_x_half_duplex: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(12, r)]
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p_10_base_t_full_duplex: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(11, r)]
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p_10_base_t_half_duplex: bool,
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/// Always 0 for Marvell 88E15XX
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#[bit(10, r)]
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p_100_base_t2_full_duplex: bool,
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/// Always 0 for Marvell 88E15XX
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#[bit(9, r)]
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p_100_base_t2_half_duplex: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(8, r)]
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extended_status: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(6, r)]
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mf_preamble_suppression: bool,
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#[bit(5, r)]
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auto_negotiation_complete: bool,
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// Latching high register bit.
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#[bit(4, r)]
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copper_remote_fault: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(3, r)]
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auto_negotation_ability: bool,
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// Latching low register bit. For the current link status, this register should be read back
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// to back, or the link real time register (17_0.10) should be read
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#[bit(2, r)]
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copper_link_status: LatchingLinkStatus,
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// Latching high register bit.
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#[bit(1, r)]
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jabber_detect: bool,
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/// Always 1 for Marvell 88E15XX
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#[bit(0, r)]
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extended_capabilities: bool,
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}
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#[bitbybit::bitenum(u2, exhaustive = true)]
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pub enum PhySpeedBits {
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Reserved = 0b11,
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Mbps1000 = 0b10,
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Mbps100 = 0b01,
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Mbps10 = 0b00,
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}
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impl PhySpeedBits {
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#[inline]
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pub fn as_zynq7000_eth_speed(&self) -> Option<zynq7000_hal::eth::Speed> {
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match self {
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PhySpeedBits::Reserved => None,
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PhySpeedBits::Mbps1000 => Some(zynq7000_hal::eth::Speed::Mbps1000),
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PhySpeedBits::Mbps100 => Some(zynq7000_hal::eth::Speed::Mbps100),
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PhySpeedBits::Mbps10 => Some(zynq7000_hal::eth::Speed::Mbps10),
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}
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}
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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pub enum PhyDuplexBit {
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Full = 1,
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Half = 0,
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}
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impl PhyDuplexBit {
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#[inline]
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pub fn as_zynq7000_eth_duplex(&self) -> zynq7000_hal::eth::Duplex {
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match self {
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PhyDuplexBit::Full => zynq7000_hal::eth::Duplex::Full,
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PhyDuplexBit::Half => zynq7000_hal::eth::Duplex::Half,
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}
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}
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}
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#[bitbybit::bitfield(u16)]
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pub struct CopperSpecificStatusRegister {
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#[bits(14..=15, r)]
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speed: PhySpeedBits,
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#[bit(13, r)]
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duplex: PhyDuplexBit,
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/// Latching high register bit.
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#[bit(12, r)]
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page_received: bool,
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/// This is 1 when auto-negotiation is not enabled.
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#[bit(11, r)]
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speed_and_duplex_resolved: bool,
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/// This is the real-time link status.
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#[bit(10, r)]
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copper_link: bool,
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#[bit(9, r)]
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transmit_pause_enabled: bool,
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#[bit(8, r)]
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received_pause_enabled: bool,
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#[bit(6, r)]
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mdi_crossover_status: bool,
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#[bit(4, r)]
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copper_energy_detect_status: bool,
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#[bit(3, r)]
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global_link_status: bool,
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#[bit(1, r)]
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polarity: bool,
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#[bit(0, r)]
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jabber: bool,
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}
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pub struct Marvell88E1518Phy {
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mdio: zynq7000_hal::eth::mdio::Mdio,
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addr: u5,
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}
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impl Marvell88E1518Phy {
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pub fn new_autoprobe_addr(mdio: &mut zynq7000_hal::eth::mdio::Mdio) -> Option<(Self, u4)> {
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for addr in 0..32 {
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let phy_id_1 =
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mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg1.raw_value());
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let phy_id_2 =
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mdio.read_blocking(u5::new(addr), MarvellRegistersPage0::IdReg2.raw_value());
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// PHY ID 1 contains bits 3 to 18 of the OUI in the goofy IEEE ordering scheme,
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// which corresponds to bit \[21:6\] of the OUI.
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// PHY ID 2 contains bits 19 to 24 which correspond to bits \[5:0\] of the OUI.
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let oui = ((phy_id_1 as u32) << 6) | ((phy_id_2 >> 10) & 0b111111) as u32;
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let model_number = ((phy_id_2 >> 4) & 0b111111) as u8;
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let revision_number = u4::new((phy_id_2 & 0b1111) as u8);
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if oui == MARVELL_88E1518_OUI && model_number == MARVELL_88E1518_MODELL_NUMBER {
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return Some((
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Self {
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mdio: unsafe { mdio.clone() },
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addr: u5::new(addr),
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},
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revision_number,
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));
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}
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}
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None
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}
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pub fn new(mdio: zynq7000_hal::eth::mdio::Mdio, addr: u5) -> Self {
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Self { mdio, addr }
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}
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pub fn reset(&mut self) {
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let mut ctrl = CopperControlRegister::new_with_raw_value(
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self.mdio
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.read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
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);
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ctrl.set_copper_reset(true);
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self.mdio.write_blocking(
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self.addr,
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MarvellRegistersPage0::CopperControl.raw_value(),
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ctrl.raw_value(),
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);
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}
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pub fn restart_auto_negotiation(&mut self) {
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let mut ctrl = CopperControlRegister::new_with_raw_value(
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self.mdio
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.read_blocking(self.addr, MarvellRegistersPage0::CopperControl.raw_value()),
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);
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ctrl.set_auto_negotiation_enable(true);
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ctrl.set_restart_auto_negotiation(true);
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self.mdio.write_blocking(
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self.addr,
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MarvellRegistersPage0::CopperControl.raw_value(),
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ctrl.raw_value(),
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);
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}
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pub fn read_copper_status(&mut self) -> CopperStatusRegister {
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let raw_value = self
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.mdio
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.read_blocking(self.addr, MarvellRegistersPage0::CopperStatus.raw_value());
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CopperStatusRegister::new_with_raw_value(raw_value)
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}
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pub fn read_copper_specific_status_register_1(&mut self) -> CopperSpecificStatusRegister {
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let raw_value = self.mdio.read_blocking(
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self.addr,
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MarvellRegistersPage0::CopperSpecificStatus.raw_value(),
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);
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CopperSpecificStatusRegister::new_with_raw_value(raw_value)
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}
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}
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