Squashed commit of the following:
commit 120e50299b3b43d42f47054bb5f11ba412fbcb68
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed May 10 14:24:39 2023 +0200
update IP core handler
commit a13687a7dcac179c6d7f9037976d40d612208ab4
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed May 10 14:21:05 2023 +0200
update AXI PTME config code
commit c137df64ab43e5b20fcf26c8821982fa71e43cff
Merge: a919b3d1 4179e8e1
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:38:52 2023 +0200
Merge remote-tracking branch 'origin/main' into update_ptme_code
commit 4179e8e124b3f9f425ac64b7df8b7e7395982dbf
Merge: 26f5eff6 51f9d5e1
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:35:54 2023 +0200
Merge pull request 'This bugfix might be super important' (#621) from possible_bugfix_dual_lane_assy into main
Reviewed-on: #621
Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de>
Reviewed-by: Steffen Gaisser <gaisser@irs.uni-stuttgart.de>
commit 51f9d5e1fe8e71445ec15b833020c4e30b254e72
Merge: a17f57cb 26f5eff6
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:35:10 2023 +0200
Merge branch 'main' into possible_bugfix_dual_lane_assy
commit a17f57cbb587f960366baae7059309d18619cdc4
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:34:45 2023 +0200
changelog
commit 26f5eff6d5957e4898f6d5a84200e77b1bd6250c
Merge: 4074e084 8a0f13ba
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:32:03 2023 +0200
Merge pull request 'More System Modes' (#612) from more-system-modes into main
Reviewed-on: #612
commit 8a0f13bafbb995b724321a3936a674078d01882f
Merge: 14baa356 4074e084
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:31:51 2023 +0200
Merge branch 'main' into more-system-modes
commit 14baa3563c3dc6499bac49bb83c08ba98bfad171
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:30:09 2023 +0200
hello
commit 7045b6034afdb819f4978f91f697d7f23806ab89
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:18:47 2023 +0200
changelog
commit 37b9615525637294118266910979236127f8a8ce
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:18:16 2023 +0200
changelog
commit 4074e0848012042565047726b8c526c6b5809a2c
Merge: 862a4f26 38686ac3
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:12:46 2023 +0200
Merge pull request 'Adaption for EM: Add P60 dock without ACU' (#620) from adaption_em_p60_dock_without_acu into main
Reviewed-on: #620
Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de>
commit 23796345d966787f6f43c1d89b9555413bfe583a
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 15:04:30 2023 +0200
changelog and stop payload tracking
commit b10275ca43f13ee68be013c7ece3b63acf762130
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 14:28:05 2023 +0200
changelog
commit 383849c5cb62b1543037ab07c904b2725c91be13
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 14:25:14 2023 +0200
that is more robust
commit c66cef9129586e8708a8f2679ff86b3c9977c5f5
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 14:23:21 2023 +0200
changelog
commit 02ea8a7298ff14c8acab55b2f693e8593c277624
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 14:22:21 2023 +0200
changelog
commit 38686ac3f621e50ea76be023520167841d2e2c19
Merge: 189a3126 74d5d709
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 14:04:03 2023 +0200
Merge branch 'possible_bugfix_dual_lane_assy' into adaption_em_p60_dock_without_acu
commit 74d5d70973b46c70d1483077e71e2820d3ca4ad6
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 13:58:08 2023 +0200
this bugfix might be super important
commit 48355e82635b071b9347b62f2bd1da636bf4eae5
Merge: 5691fe8e 862a4f26
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 10:25:50 2023 +0200
Merge branch 'main' into more-system-modes
commit 189a312628e561f54491ec238a2d2d5e2f211b57
Merge: a1279428 862a4f26
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 10:23:46 2023 +0200
Merge remote-tracking branch 'origin/main' into adaption_em_p60_dock_without_acu
commit a12794281bfc2ebb27a02bbc151696023e69a9f0
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 10:20:31 2023 +0200
changelog
commit fcaabb4e421b5f792ede490b6dd135ce661c9db5
Merge: 6c326489 4aafca64
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 10:20:02 2023 +0200
Merge remote-tracking branch 'origin/main' into adaption_em_p60_dock_without_acu
commit 6c326489cbc59f2d70993542f05676472ca0102f
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 10:18:46 2023 +0200
adapt EM SW: GS PCDU added, but use dummy for ACU
commit 862a4f268510e04fc3cfb878b5eed9f0f9d62f05
Merge: 4aafca64 2daca272
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Fri Apr 28 09:37:55 2023 +0200
Merge pull request 'Host SW bugfixes' (#618) from try_fix_host_obsw into main
Reviewed-on: #618
Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de>
commit 5691fe8e72a2e3b008d6130f31be32d9d7aee9b7
Merge: 097be17a 4aafca64
Author: meggert <eggertm@irs.uni-stuttgart.de>
Date: Thu Apr 27 15:40:31 2023 +0200
Merge branch 'main' into more-system-modes
commit 2daca272f8f0397125349c0f6c193e22d0a26383
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Thu Apr 27 11:29:18 2023 +0200
changelog
commit 03762f962020b55188d445ee3dd429b6e1a32135
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:38:06 2023 +0200
lower live TM handler frequency
commit a296f16e5ce9d803ce5db54d9602e396dad7ebce
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:36:38 2023 +0200
host SW works properly again
commit 83f07a6e16cbbf5fc4a9ccb2e7d92c3fdffb172b
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:26:32 2023 +0200
configurable event manager queue depth
commit 00dab64628a53d2109fceb5f9a4ffc765a72fab6
Merge: 641b8e84 4aafca64
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:03:35 2023 +0200
Merge remote-tracking branch 'origin/main' into try_fix_host_obsw
commit 4aafca64a67589826f1578865c92fa76141e8531
Merge: f271242d 6901eae8
Author: Robin Müller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:03:01 2023 +0200
Merge pull request 'EM adaptions' (#619) from em_adaptions into main
Reviewed-on: #619
commit 6901eae81689981937e7eb49b98886f8c78b727b
Merge: 7d630ebc f271242d
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:02:24 2023 +0200
Merge remote-tracking branch 'origin/main' into em_adaptions
commit 7d630ebcf3894a9a9896d1c3f05548d5ef230333
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 17:00:04 2023 +0200
EM adaptions
commit 641b8e847d2b63ad11f28c4a37434a6161443690
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 16:41:40 2023 +0200
add back tm funnel handler for hosted build
commit 13142686823bedee1a79ae5f851f124968822a54
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 16:23:50 2023 +0200
host build requires dedicated live TM task..
commit 4040304ef09a172f9d2bef42547d6b1effb8ca76
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 13:15:42 2023 +0200
this is annoying
commit a919b3d1645d5c4a6e20903d973ce96424508cae
Merge: e22f2a53 9672d6d6
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:11:30 2023 +0200
Merge remote-tracking branch 'origin/develop' into update_ptme_code
commit 9672d6d6cca3ad7369bb4b06fd91a7f17a0f9db9
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:11:09 2023 +0200
changelog
commit e22f2a53ea7388cc5c75c2024953aab293c8d277
Merge: b076e80b 0eb6b7cc
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:05:58 2023 +0200
Merge remote-tracking branch 'origin/develop' into update_ptme_code
commit b076e80b44e7ef2b2417def66ec1f1a684cfb228
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:04:10 2023 +0200
changelog
commit 269aa6f7b0006125e9a516f8ecb6cdc32c91cbe5
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:03:42 2023 +0200
changelog
commit caae2b4ba925747aa0ed1e2112582c6deff39d77
Author: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Wed Apr 26 11:02:24 2023 +0200
update PTME code
commit 097be17a2900e64021fcbb457c89d6d4756ab697
Author: meggert <eggertm@irs.uni-stuttgart.de>
Date: Wed Apr 19 15:07:21 2023 +0200
added remaining acs modes as system modes
This commit is contained in:
parent
7e6c25901b
commit
00e98a2fd6
GPG Key ID:
A649FB78196E3849
@ -23,6 +23,7 @@ TODO: New firmware package version.
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## Changed
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- Removed PTME busy/ready signals. Those were not used anyway because register reads are used now.
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- Update PTME config register code: Each VC now has its own configuration register.
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## Fixed
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@ -59,7 +60,6 @@ TODO: New firmware package version.
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# [v2.0.5] 2023-05-11
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- The dual lane assembly transition failed handler started new transitions towards the current mode
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instead of the target mode. This means that if the dual lane assembly never reached the initial
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submode (e.g. mode normal and submode dual side), it will transition back to the current mode,
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@ -32,7 +32,7 @@ ReturnValue_t AxiPtmeConfig::writeCaduRateReg(uint8_t rateVal) {
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to lock mutex" << std::endl;
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return returnvalue::FAILED;
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}
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*(baseAddress + CADU_BITRATE_REG) = static_cast<uint32_t>(rateVal);
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*(baseAddress + ADDR_CADU_BITRATE_REG) = static_cast<uint32_t>(rateVal);
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result = mutex->unlockMutex();
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if (result != returnvalue::OK) {
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to unlock mutex" << std::endl;
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@ -42,27 +42,27 @@ ReturnValue_t AxiPtmeConfig::writeCaduRateReg(uint8_t rateVal) {
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}
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void AxiPtmeConfig::enableTxclockManipulator() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::EN_TX_CLK_MANIPULATOR);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::EN_TX_CLK_MANIPULATOR);
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}
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void AxiPtmeConfig::disableTxclockManipulator() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::EN_TX_CLK_MANIPULATOR);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::EN_TX_CLK_MANIPULATOR);
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}
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void AxiPtmeConfig::enableTxclockInversion() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::INVERT_CLOCK);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::INVERT_CLOCK);
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}
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void AxiPtmeConfig::disableTxclockInversion() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::INVERT_CLOCK);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::INVERT_CLOCK);
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}
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void AxiPtmeConfig::enableBatPriorityBit() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::EN_BAT_PRIORITY);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::EN_BAT_PRIORITY);
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}
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void AxiPtmeConfig::disableBatPriorityBit() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::EN_BAT_PRIORITY);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::EN_BAT_PRIORITY);
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}
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void AxiPtmeConfig::writeReg(uint32_t regOffset, uint32_t writeVal) {
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@ -75,21 +75,62 @@ uint32_t AxiPtmeConfig::readReg(uint32_t regOffset) {
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return *(baseAddress + regOffset / ADRESS_DIVIDER);
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}
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void AxiPtmeConfig::writePollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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uint32_t regVal = readCommonCfgReg();
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void AxiPtmeConfig::writePollThreshold(uint8_t vcIdx,
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AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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uint32_t regVal = readVcCfgReg(vcIdx);
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// Clear bits first
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regVal &= ~(0b111 << 3);
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regVal |= (static_cast<uint8_t>(pollThreshold) << 3);
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writeCommonCfgReg(regVal);
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regVal &= ~(0b111 << 13);
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regVal |= (static_cast<uint8_t>(pollThreshold) << 13);
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writeVcCfgReg(vcIdx, regVal);
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}
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AxiPtmeConfig::IdlePollThreshold AxiPtmeConfig::readPollThreshold() {
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uint32_t regVal = readCommonCfgReg();
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return static_cast<AxiPtmeConfig::IdlePollThreshold>((regVal >> 3) & 0b111);
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AxiPtmeConfig::IdlePollThreshold AxiPtmeConfig::readPollThreshold(uint8_t vcIdx) {
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uint32_t regVal = readVcCfgReg(vcIdx);
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return static_cast<AxiPtmeConfig::IdlePollThreshold>((regVal >> 13) & 0b111);
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}
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void AxiPtmeConfig::writeCommonCfgReg(uint32_t value) { writeReg(COMMON_CONFIG_REG, value); }
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uint32_t AxiPtmeConfig::readCommonCfgReg() { return readReg(COMMON_CONFIG_REG); }
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void AxiPtmeConfig::writeCommonCfgReg(uint32_t value) { writeReg(ADDR_COMMON_CONFIG_REG, value); }
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uint32_t AxiPtmeConfig::readCommonCfgReg() { return readReg(ADDR_COMMON_CONFIG_REG); }
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uint32_t AxiPtmeConfig::readVcCfgReg(uint8_t vcIdx) {
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switch (vcIdx) {
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case (0): {
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return readReg(ADDR_VC0_REG);
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}
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case (1): {
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return readReg(ADDR_VC1_REG);
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}
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case (2): {
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return readReg(ADDR_VC2_REG);
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}
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case (3): {
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return readReg(ADDR_VC3_REG);
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}
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}
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return 0;
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}
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void AxiPtmeConfig::writeVcCfgReg(uint8_t vcIdx, uint32_t reg) {
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switch (vcIdx) {
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case (0): {
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writeReg(ADDR_VC0_REG, reg);
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break;
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}
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case (1): {
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writeReg(ADDR_VC1_REG, reg);
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break;
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}
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case (2): {
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writeReg(ADDR_VC2_REG, reg);
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break;
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}
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case (3): {
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writeReg(ADDR_VC3_REG, reg);
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break;
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}
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}
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}
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void AxiPtmeConfig::writeBit(uint32_t regOffset, bool bitVal, BitPos bitPos) {
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uint32_t readVal = readReg(regOffset);
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@ -67,14 +67,20 @@ class AxiPtmeConfig : public SystemObject {
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void enableBatPriorityBit();
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void disableBatPriorityBit();
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void writePollThreshold(IdlePollThreshold pollThreshold);
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IdlePollThreshold readPollThreshold();
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void writePollThreshold(uint8_t vcIdx, IdlePollThreshold pollThreshold);
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IdlePollThreshold readPollThreshold(uint8_t vcIdx);
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private:
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// Address of register storing the bitrate configuration parameter
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static const uint32_t CADU_BITRATE_REG = 0x0;
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static const uint32_t ADDR_CADU_BITRATE_REG = 0;
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// Address of register storing common configuration parameters
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static const uint32_t COMMON_CONFIG_REG = 0x4;
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static const uint32_t ADDR_COMMON_CONFIG_REG = 4;
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static const uint32_t ADDR_FRAME_LENGTH_REG = 8;
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static const uint32_t ADDR_VC0_REG = 12;
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static const uint32_t ADDR_VC1_REG = 16;
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static const uint32_t ADDR_VC2_REG = 20;
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static const uint32_t ADDR_VC3_REG = 24;
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static const uint32_t ADRESS_DIVIDER = 4;
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enum class BitPos : uint32_t { EN_TX_CLK_MANIPULATOR = 0, INVERT_CLOCK = 1, EN_BAT_PRIORITY = 2 };
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@ -106,6 +112,9 @@ class AxiPtmeConfig : public SystemObject {
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uint32_t readCommonCfgReg();
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void writeCommonCfgReg(uint32_t value);
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uint32_t readVcCfgReg(uint8_t vcIdx);
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void writeVcCfgReg(uint8_t vcIdx, uint32_t reg);
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/**
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* @brief Sets one bit in a register
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*
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@ -50,6 +50,8 @@ void PtmeConfig::enableBatPriorityBit(bool enable) {
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}
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}
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void PtmeConfig::setPollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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axiPtmeConfig->writePollThreshold(pollThreshold);
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void PtmeConfig::setAllPollThresholds(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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for (uint8_t idx = 0; idx < 4; idx++) {
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axiPtmeConfig->writePollThreshold(idx, pollThreshold);
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}
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}
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@ -64,7 +64,7 @@ class PtmeConfig : public SystemObject {
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*/
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void enableBatPriorityBit(bool enable);
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void setPollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold);
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void setAllPollThresholds(AxiPtmeConfig::IdlePollThreshold pollThreshold);
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private:
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static const uint8_t INTERFACE_ID = CLASS_ID::RATE_SETTER;
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@ -76,7 +76,7 @@ ReturnValue_t CcsdsIpCoreHandler::initialize() {
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// This also pulls the PTME out of reset state.
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updateBatPriorityFromParam();
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ptmeConfig.setPollThreshold(
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ptmeConfig.setAllPollThresholds(
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static_cast<AxiPtmeConfig::IdlePollThreshold>(params.pollThresholdParam));
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resetPtme();
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ptmeLocked = false;
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@ -322,7 +322,7 @@ void CcsdsIpCoreHandler::performPtmeUpdateWhenApplicable() {
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doResetPtme = true;
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}
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if (updateContext.updatePollThreshold) {
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ptmeConfig.setPollThreshold(
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ptmeConfig.setAllPollThresholds(
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static_cast<AxiPtmeConfig::IdlePollThreshold>(params.pollThresholdParam));
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updateContext.updatePollThreshold = false;
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doResetPtme = true;
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