Squashed commit of the following:
commit120e50299bAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed May 10 14:24:39 2023 +0200 update IP core handler commita13687a7dcAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed May 10 14:21:05 2023 +0200 update AXI PTME config code commitc137df64abMerge:a919b3d14179e8e1Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:38:52 2023 +0200 Merge remote-tracking branch 'origin/main' into update_ptme_code commit4179e8e124Merge:26f5eff651f9d5e1Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:35:54 2023 +0200 Merge pull request 'This bugfix might be super important' (#621) from possible_bugfix_dual_lane_assy into main Reviewed-on: #621 Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de> Reviewed-by: Steffen Gaisser <gaisser@irs.uni-stuttgart.de> commit51f9d5e1feMerge:a17f57cb26f5eff6Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:35:10 2023 +0200 Merge branch 'main' into possible_bugfix_dual_lane_assy commita17f57cbb5Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:34:45 2023 +0200 changelog commit26f5eff6d5Merge:4074e0848a0f13baAuthor: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:32:03 2023 +0200 Merge pull request 'More System Modes' (#612) from more-system-modes into main Reviewed-on: #612 commit8a0f13bafbMerge:14baa3564074e084Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:31:51 2023 +0200 Merge branch 'main' into more-system-modes commit14baa3563cAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:30:09 2023 +0200 hello commit7045b6034aAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:18:47 2023 +0200 changelog commit37b9615525Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:18:16 2023 +0200 changelog commit4074e08480Merge:862a4f2638686ac3Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:12:46 2023 +0200 Merge pull request 'Adaption for EM: Add P60 dock without ACU' (#620) from adaption_em_p60_dock_without_acu into main Reviewed-on: #620 Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de> commit23796345d9Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 15:04:30 2023 +0200 changelog and stop payload tracking commitb10275ca43Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 14:28:05 2023 +0200 changelog commit383849c5cbAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 14:25:14 2023 +0200 that is more robust commitc66cef9129Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 14:23:21 2023 +0200 changelog commit02ea8a7298Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 14:22:21 2023 +0200 changelog commit38686ac3f6Merge:189a312674d5d709Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 14:04:03 2023 +0200 Merge branch 'possible_bugfix_dual_lane_assy' into adaption_em_p60_dock_without_acu commit74d5d70973Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 13:58:08 2023 +0200 this bugfix might be super important commit48355e8263Merge:5691fe8e862a4f26Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 10:25:50 2023 +0200 Merge branch 'main' into more-system-modes commit189a312628Merge:a1279428862a4f26Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 10:23:46 2023 +0200 Merge remote-tracking branch 'origin/main' into adaption_em_p60_dock_without_acu commita12794281bAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 10:20:31 2023 +0200 changelog commitfcaabb4e42Merge:6c3264894aafca64Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 10:20:02 2023 +0200 Merge remote-tracking branch 'origin/main' into adaption_em_p60_dock_without_acu commit6c326489cbAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 10:18:46 2023 +0200 adapt EM SW: GS PCDU added, but use dummy for ACU commit862a4f2685Merge:4aafca642daca272Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Fri Apr 28 09:37:55 2023 +0200 Merge pull request 'Host SW bugfixes' (#618) from try_fix_host_obsw into main Reviewed-on: #618 Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de> commit5691fe8e72Merge:097be17a4aafca64Author: meggert <eggertm@irs.uni-stuttgart.de> Date: Thu Apr 27 15:40:31 2023 +0200 Merge branch 'main' into more-system-modes commit2daca272f8Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Thu Apr 27 11:29:18 2023 +0200 changelog commit03762f9620Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:38:06 2023 +0200 lower live TM handler frequency commita296f16e5cAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:36:38 2023 +0200 host SW works properly again commit83f07a6e16Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:26:32 2023 +0200 configurable event manager queue depth commit00dab64628Merge:641b8e844aafca64Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:03:35 2023 +0200 Merge remote-tracking branch 'origin/main' into try_fix_host_obsw commit4aafca64a6Merge:f271242d6901eae8Author: Robin Müller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:03:01 2023 +0200 Merge pull request 'EM adaptions' (#619) from em_adaptions into main Reviewed-on: #619 commit6901eae816Merge:7d630ebcf271242dAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:02:24 2023 +0200 Merge remote-tracking branch 'origin/main' into em_adaptions commit7d630ebcf3Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 17:00:04 2023 +0200 EM adaptions commit641b8e847dAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 16:41:40 2023 +0200 add back tm funnel handler for hosted build commit1314268682Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 16:23:50 2023 +0200 host build requires dedicated live TM task.. commit4040304ef0Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 13:15:42 2023 +0200 this is annoying commita919b3d164Merge:e22f2a539672d6d6Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:11:30 2023 +0200 Merge remote-tracking branch 'origin/develop' into update_ptme_code commit9672d6d6ccAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:11:09 2023 +0200 changelog commite22f2a53eaMerge:b076e80b0eb6b7ccAuthor: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:05:58 2023 +0200 Merge remote-tracking branch 'origin/develop' into update_ptme_code commitb076e80b44Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:04:10 2023 +0200 changelog commit269aa6f7b0Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:03:42 2023 +0200 changelog commitcaae2b4ba9Author: Robin Mueller <muellerr@irs.uni-stuttgart.de> Date: Wed Apr 26 11:02:24 2023 +0200 update PTME code commit097be17a29Author: meggert <eggertm@irs.uni-stuttgart.de> Date: Wed Apr 19 15:07:21 2023 +0200 added remaining acs modes as system modes
This commit is contained in:
parent
7e6c25901b
commit
00e98a2fd6
GPG Key ID:
A649FB78196E3849
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@ -23,6 +23,7 @@ TODO: New firmware package version.
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## Changed
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- Removed PTME busy/ready signals. Those were not used anyway because register reads are used now.
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- Update PTME config register code: Each VC now has its own configuration register.
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## Fixed
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@ -59,7 +60,6 @@ TODO: New firmware package version.
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# [v2.0.5] 2023-05-11
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- The dual lane assembly transition failed handler started new transitions towards the current mode
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instead of the target mode. This means that if the dual lane assembly never reached the initial
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submode (e.g. mode normal and submode dual side), it will transition back to the current mode,
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@ -32,7 +32,7 @@ ReturnValue_t AxiPtmeConfig::writeCaduRateReg(uint8_t rateVal) {
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to lock mutex" << std::endl;
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return returnvalue::FAILED;
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}
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*(baseAddress + CADU_BITRATE_REG) = static_cast<uint32_t>(rateVal);
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*(baseAddress + ADDR_CADU_BITRATE_REG) = static_cast<uint32_t>(rateVal);
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result = mutex->unlockMutex();
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if (result != returnvalue::OK) {
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to unlock mutex" << std::endl;
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@ -42,27 +42,27 @@ ReturnValue_t AxiPtmeConfig::writeCaduRateReg(uint8_t rateVal) {
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}
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void AxiPtmeConfig::enableTxclockManipulator() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::EN_TX_CLK_MANIPULATOR);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::EN_TX_CLK_MANIPULATOR);
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}
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void AxiPtmeConfig::disableTxclockManipulator() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::EN_TX_CLK_MANIPULATOR);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::EN_TX_CLK_MANIPULATOR);
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}
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void AxiPtmeConfig::enableTxclockInversion() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::INVERT_CLOCK);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::INVERT_CLOCK);
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}
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void AxiPtmeConfig::disableTxclockInversion() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::INVERT_CLOCK);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::INVERT_CLOCK);
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}
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void AxiPtmeConfig::enableBatPriorityBit() {
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writeBit(COMMON_CONFIG_REG, true, BitPos::EN_BAT_PRIORITY);
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writeBit(ADDR_COMMON_CONFIG_REG, true, BitPos::EN_BAT_PRIORITY);
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}
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void AxiPtmeConfig::disableBatPriorityBit() {
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writeBit(COMMON_CONFIG_REG, false, BitPos::EN_BAT_PRIORITY);
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writeBit(ADDR_COMMON_CONFIG_REG, false, BitPos::EN_BAT_PRIORITY);
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}
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void AxiPtmeConfig::writeReg(uint32_t regOffset, uint32_t writeVal) {
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@ -75,21 +75,62 @@ uint32_t AxiPtmeConfig::readReg(uint32_t regOffset) {
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return *(baseAddress + regOffset / ADRESS_DIVIDER);
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}
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void AxiPtmeConfig::writePollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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uint32_t regVal = readCommonCfgReg();
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void AxiPtmeConfig::writePollThreshold(uint8_t vcIdx,
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AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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uint32_t regVal = readVcCfgReg(vcIdx);
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// Clear bits first
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regVal &= ~(0b111 << 3);
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regVal |= (static_cast<uint8_t>(pollThreshold) << 3);
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writeCommonCfgReg(regVal);
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regVal &= ~(0b111 << 13);
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regVal |= (static_cast<uint8_t>(pollThreshold) << 13);
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writeVcCfgReg(vcIdx, regVal);
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}
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AxiPtmeConfig::IdlePollThreshold AxiPtmeConfig::readPollThreshold() {
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uint32_t regVal = readCommonCfgReg();
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return static_cast<AxiPtmeConfig::IdlePollThreshold>((regVal >> 3) & 0b111);
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AxiPtmeConfig::IdlePollThreshold AxiPtmeConfig::readPollThreshold(uint8_t vcIdx) {
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uint32_t regVal = readVcCfgReg(vcIdx);
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return static_cast<AxiPtmeConfig::IdlePollThreshold>((regVal >> 13) & 0b111);
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}
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void AxiPtmeConfig::writeCommonCfgReg(uint32_t value) { writeReg(COMMON_CONFIG_REG, value); }
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uint32_t AxiPtmeConfig::readCommonCfgReg() { return readReg(COMMON_CONFIG_REG); }
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void AxiPtmeConfig::writeCommonCfgReg(uint32_t value) { writeReg(ADDR_COMMON_CONFIG_REG, value); }
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uint32_t AxiPtmeConfig::readCommonCfgReg() { return readReg(ADDR_COMMON_CONFIG_REG); }
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uint32_t AxiPtmeConfig::readVcCfgReg(uint8_t vcIdx) {
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switch (vcIdx) {
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case (0): {
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return readReg(ADDR_VC0_REG);
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}
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case (1): {
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return readReg(ADDR_VC1_REG);
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}
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case (2): {
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return readReg(ADDR_VC2_REG);
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}
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case (3): {
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return readReg(ADDR_VC3_REG);
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}
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}
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return 0;
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}
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void AxiPtmeConfig::writeVcCfgReg(uint8_t vcIdx, uint32_t reg) {
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switch (vcIdx) {
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case (0): {
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writeReg(ADDR_VC0_REG, reg);
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break;
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}
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case (1): {
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writeReg(ADDR_VC1_REG, reg);
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break;
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}
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case (2): {
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writeReg(ADDR_VC2_REG, reg);
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break;
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}
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case (3): {
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writeReg(ADDR_VC3_REG, reg);
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break;
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}
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}
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}
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void AxiPtmeConfig::writeBit(uint32_t regOffset, bool bitVal, BitPos bitPos) {
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uint32_t readVal = readReg(regOffset);
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@ -67,14 +67,20 @@ class AxiPtmeConfig : public SystemObject {
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void enableBatPriorityBit();
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void disableBatPriorityBit();
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void writePollThreshold(IdlePollThreshold pollThreshold);
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IdlePollThreshold readPollThreshold();
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void writePollThreshold(uint8_t vcIdx, IdlePollThreshold pollThreshold);
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IdlePollThreshold readPollThreshold(uint8_t vcIdx);
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private:
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// Address of register storing the bitrate configuration parameter
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static const uint32_t CADU_BITRATE_REG = 0x0;
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static const uint32_t ADDR_CADU_BITRATE_REG = 0;
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// Address of register storing common configuration parameters
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static const uint32_t COMMON_CONFIG_REG = 0x4;
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static const uint32_t ADDR_COMMON_CONFIG_REG = 4;
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static const uint32_t ADDR_FRAME_LENGTH_REG = 8;
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static const uint32_t ADDR_VC0_REG = 12;
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static const uint32_t ADDR_VC1_REG = 16;
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static const uint32_t ADDR_VC2_REG = 20;
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static const uint32_t ADDR_VC3_REG = 24;
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static const uint32_t ADRESS_DIVIDER = 4;
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enum class BitPos : uint32_t { EN_TX_CLK_MANIPULATOR = 0, INVERT_CLOCK = 1, EN_BAT_PRIORITY = 2 };
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uint32_t readCommonCfgReg();
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void writeCommonCfgReg(uint32_t value);
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uint32_t readVcCfgReg(uint8_t vcIdx);
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void writeVcCfgReg(uint8_t vcIdx, uint32_t reg);
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/**
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* @brief Sets one bit in a register
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*
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}
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}
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void PtmeConfig::setPollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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axiPtmeConfig->writePollThreshold(pollThreshold);
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void PtmeConfig::setAllPollThresholds(AxiPtmeConfig::IdlePollThreshold pollThreshold) {
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for (uint8_t idx = 0; idx < 4; idx++) {
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axiPtmeConfig->writePollThreshold(idx, pollThreshold);
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}
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}
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*/
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void enableBatPriorityBit(bool enable);
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void setPollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold);
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void setAllPollThresholds(AxiPtmeConfig::IdlePollThreshold pollThreshold);
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private:
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static const uint8_t INTERFACE_ID = CLASS_ID::RATE_SETTER;
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// This also pulls the PTME out of reset state.
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updateBatPriorityFromParam();
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ptmeConfig.setPollThreshold(
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ptmeConfig.setAllPollThresholds(
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static_cast<AxiPtmeConfig::IdlePollThreshold>(params.pollThresholdParam));
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resetPtme();
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ptmeLocked = false;
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doResetPtme = true;
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}
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if (updateContext.updatePollThreshold) {
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ptmeConfig.setPollThreshold(
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ptmeConfig.setAllPollThresholds(
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static_cast<AxiPtmeConfig::IdlePollThreshold>(params.pollThresholdParam));
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updateContext.updatePollThreshold = false;
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doResetPtme = true;
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