fsfw/fsfw-hal
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fsfw-hal
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indentation

This commit is contained in:
Robin Müller 2021-06-10 19:11:02 +02:00
parent 8f61c23e62
commit 1611099cb2
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GPG Key ID: BE6480244DFE612C
1 changed files with 27 additions and 27 deletions
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54
stm32h7/spi/mspInit.cpp
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@ -55,22 +55,22 @@ void spi::halMspInitDma(SPI_HandleTypeDef* hspi, MspCfgBase* cfgBase) {
// Assume it was not configured properly
mspErrorHandler("spi::halMspInitDma", "DMA TX handle invalid");
}
hdma_tx->Instance = SPIx_TX_DMA_STREAM;
hdma_tx->Instance = SPIx_TX_DMA_STREAM;
hdma_tx->Init.Request = SPIx_TX_DMA_REQUEST;
hdma_tx->Init.Request = SPIx_TX_DMA_REQUEST;
// offer function to configure this..
hdma_tx->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
hdma_tx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_tx->Init.MemBurst = DMA_MBURST_INC4;
hdma_tx->Init.PeriphBurst = DMA_PBURST_INC4;
hdma_tx->Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_tx->Init.PeriphInc = DMA_PINC_DISABLE;
hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_tx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_tx->Init.Mode = DMA_NORMAL;
hdma_tx->Init.Priority = DMA_PRIORITY_LOW;
// offer function to configure this..
hdma_tx->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
hdma_tx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_tx->Init.MemBurst = DMA_MBURST_INC4;
hdma_tx->Init.PeriphBurst = DMA_PBURST_INC4;
hdma_tx->Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_tx->Init.PeriphInc = DMA_PINC_DISABLE;
hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_tx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_tx->Init.Mode = DMA_NORMAL;
hdma_tx->Init.Priority = DMA_PRIORITY_LOW;
HAL_DMA_Init(hdma_tx);
@ -78,20 +78,20 @@ void spi::halMspInitDma(SPI_HandleTypeDef* hspi, MspCfgBase* cfgBase) {
__HAL_LINKDMA(hspi, hdmatx, *hdma_tx);
/* Configure the DMA handler for Transmission process */
hdma_rx->Instance = SPIx_RX_DMA_STREAM;
hdma_rx->Instance = SPIx_RX_DMA_STREAM;
hdma_rx->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
hdma_rx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_rx->Init.MemBurst = DMA_MBURST_INC4;
hdma_rx->Init.PeriphBurst = DMA_PBURST_INC4;
hdma_rx->Init.Request = SPIx_RX_DMA_REQUEST;
hdma_rx->Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_rx->Init.PeriphInc = DMA_PINC_DISABLE;
hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_rx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_rx->Init.Mode = DMA_NORMAL;
hdma_rx->Init.Priority = DMA_PRIORITY_HIGH;
hdma_rx->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
hdma_rx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
hdma_rx->Init.MemBurst = DMA_MBURST_INC4;
hdma_rx->Init.PeriphBurst = DMA_PBURST_INC4;
hdma_rx->Init.Request = SPIx_RX_DMA_REQUEST;
hdma_rx->Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_rx->Init.PeriphInc = DMA_PINC_DISABLE;
hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_rx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_rx->Init.Mode = DMA_NORMAL;
hdma_rx->Init.Priority = DMA_PRIORITY_HIGH;
HAL_DMA_Init(hdma_rx);