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xilinx ps7_cortexa9 code Version xilinx_v2024.1

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Ulrich Mohr 2024-10-14 13:36:25 +02:00
parent dd9c39af30
commit fb4b12c8f9
219 changed files with 11733 additions and 7355 deletions
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11
bsp_z7/ps7_cortexa9_0/README.md Normal file
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@ -0,0 +1,11 @@
This is based on the bsp of the zynq_fsbl in https://github.com/Xilinx/embeddedsw/tree/xilinx_v2024.1/lib/sw_apps/zynq_fsbl
It is generated/collected by xilinx's build system when building the fsbl.
Currently, version xilinx_v2024.1 is used.
We use our own CMakeLists.txt located in the subfolders of `libsrc` to select which files to include in our bsp.
Xilinx exports CMakeLists.txt files for some of their folders as well, which we remove to avoid confusion.
Additionally, drivers from https://github.com/Xilinx/embeddedsw/tree/xilinx_v2024.1/XilinxProcessorIPLib/drivers are added as needed.

60
bsp_z7/ps7_cortexa9_0/include/diskio.h
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@ -9,8 +9,8 @@
extern "C" {
#endif
#define USE_WRITE 1 /* 1: Enable disk_write function */
#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
#define USE_WRITE 1 /**< 1: Enable disk_write function */
#define USE_IOCTL 1 /**< 1: Enable disk_ioctl function */
#include "ff.h"
#include "xil_types.h"
@ -20,11 +20,11 @@ typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
RES_OK = 0, /**< 0: Successful */
RES_ERROR, /**< 1: R/W Error */
RES_WRPRT, /**< 2: Write Protected */
RES_NOTRDY, /**< 3: Not Ready */
RES_PARERR /**< 4: Invalid Parameter */
} DRESULT;
@ -41,40 +41,40 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01U /* Drive not initialized */
#define STA_NODISK 0x02U /* No medium in the drive */
#define STA_PROTECT 0x04U /* Write protected */
#define STA_NOINIT 0x01U /**< Drive not initialized */
#define STA_NODISK 0x02U /**< No medium in the drive */
#define STA_PROTECT 0x04U /**< Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0U /* Complete pending write process (needed at FF_FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1U /* Get media size (needed at FF_USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2U /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
#define GET_BLOCK_SIZE 3U /* Get erase block size (needed at FF_USE_MKFS == 1) */
#define CTRL_TRIM 4U /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
#define CTRL_SYNC 0U /**< Complete pending write process (needed at FF_FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1U /**< Get media size (needed at FF_USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2U /**< Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
#define GET_BLOCK_SIZE 3U /**< Get erase block size (needed at FF_USE_MKFS == 1) */
#define CTRL_TRIM 4U /**< Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5U /* Get/Set power status */
#define CTRL_LOCK 6U /* Lock/Unlock media removal */
#define CTRL_EJECT 7U /* Eject media */
#define CTRL_FORMAT 8U /* Create physical format on the media */
#define CTRL_POWER 5U /**< Get/Set power status */
#define CTRL_LOCK 6U /**< Lock/Unlock media removal */
#define CTRL_EJECT 7U /**< Eject media */
#define CTRL_FORMAT 8U /**< Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10U /* Get card type */
#define MMC_GET_CSD 11U /* Get CSD */
#define MMC_GET_CID 12U /* Get CID */
#define MMC_GET_OCR 13U /* Get OCR */
#define MMC_GET_SDSTAT 14U /* Get SD status */
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
#define MMC_GET_TYPE 10U /**< Get card type */
#define MMC_GET_CSD 11U /**< Get CSD */
#define MMC_GET_CID 12U /**< Get CID */
#define MMC_GET_OCR 13U /**< Get OCR */
#define MMC_GET_SDSTAT 14U /**< Get SD status */
#define ISDIO_READ 55 /**< Read data form SD iSDIO register */
#define ISDIO_WRITE 56 /**< Write data to SD iSDIO register */
#define ISDIO_MRITE 57 /**< Masked write data to SD iSDIO register */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20U /* Get F/W revision */
#define ATA_GET_MODEL 21U /* Get model name */
#define ATA_GET_SN 22U /* Get serial number */
#define ATA_GET_REV 20U /**< Get F/W revision */
#define ATA_GET_MODEL 21U /**< Get model name */
#define ATA_GET_SN 22U /**< Get serial number */
#ifdef __cplusplus
}

4
bsp_z7/ps7_cortexa9_0/include/ff.h
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@ -26,8 +26,8 @@
extern "C" {
#endif
#include "xil_types.h"
#include "ffconf.h" /* FatFs configuration options */
#include "xilffs.h"
#if FF_DEFINED != FFCONF_DEF
#error Wrong configuration file (ffconf.h).
@ -355,7 +355,7 @@ int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
/* Some API fucntions are implemented as macro */
/* Some API functions are implemented as macro */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
#define f_error(fp) ((fp)->err)

15
bsp_z7/ps7_cortexa9_0/include/ffconf.h
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@ -8,7 +8,11 @@
extern "C" {
#endif
#ifdef SDT
#include "xilffs_config.h"
#else
#include "xparameters.h"
#endif
/*---------------------------------------------------------------------------/
/ Function Configurations
@ -34,7 +38,7 @@ extern "C" {
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#ifdef FILE_SYSTEM_USE_STRFUNC
#if FILE_SYSTEM_USE_STRFUNC == 0
#define FF_USE_STRFUNC 0 /* 0:Disable */
#elif FILE_SYSTEM_USE_STRFUNC == 1
@ -42,6 +46,9 @@ extern "C" {
#elif FILE_SYSTEM_USE_STRFUNC == 2
#define FF_USE_STRFUNC 2 /* 2:Enable */
#endif
#else
#define FF_USE_STRFUNC 0 /* 0:Disable */
#endif
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
/
/ 0: Disable string functions.
@ -87,7 +94,6 @@ extern "C" {
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
#define FF_USE_STRFUNC 0
#define FF_PRINT_LLI 1
#define FF_PRINT_FLOAT 1
#define FF_STRF_ENCODE 3
@ -187,7 +193,7 @@ extern "C" {
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#ifdef FILE_SYSTEM_SET_FS_RPATH
#if FILE_SYSTEM_SET_FS_RPATH == 0
#define FF_FS_RPATH 0U
#elif FILE_SYSTEM_SET_FS_RPATH == 1
@ -195,6 +201,9 @@ extern "C" {
#elif FILE_SYSTEM_SET_FS_RPATH == 2
#define FF_FS_RPATH 2U
#endif
#else
#define FF_FS_RPATH 0U
#endif
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.

268
bsp_z7/ps7_cortexa9_0/include/pm_api_version.h Normal file
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@ -0,0 +1,268 @@
/******************************************************************************
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_api_version.h
*
* @addtogroup xpm_versal_apis XilPM APIs
*****************************************************************************/
#ifndef PM_API_VERSION_H_
#define PM_API_VERSION_H_
/*****************************************************************************/
/**
* @section EEMI_API_DETAIL XilPM EEMI API Version Detail
*
* This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
*
* | NAME | ID | Platform | Version| Description |
* |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
* | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API |
* | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device |
* | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality |
* | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event |
* | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem |
* | PM_SELF_SUSPEND | 0x7 | Both | 3 | V1 - The API is used to suspend a child subsystem |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | V3 - Added support of CPU off state |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal and Versal NET but ZynqMP supports only V1|
* | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem |
* | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem |
* | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source |
* | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system |
* | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use |
* | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device |
* | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device |
* | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state |
* | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices |
* | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip |
* | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin |
* | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin |
* | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function |
* | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function |
* | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value |
* | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value |
* | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 |
* | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 |
* | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock |
* | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock |
* | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state |
* | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock |
* | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider |
* | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock |
* | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent |
* | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock |
* | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock |
* | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock |
* | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock |
* | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
*
* This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|---------------------------------------|
* | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode |
* | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode |
* | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config |
* | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config |
* | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass |
* | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset |
* | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay |
* | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode |
* | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode |
* | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data |
* | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data |
* | IOCTL_WRITE_GGS | 12 | Both | Write GGS |
* | IOCTL_READ_GGS | 13 | Both | Read GGS |
* | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS |
* | IOCTL_READ_PGGS | 15 | Both | Read PGGS |
* | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset |
* | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status |
* | IOCTL_AFI | 18 | ZynqMP | AFI |
* | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select |
* | IOCTL_USB_SET_STATE | 22 | Versal | USB set state |
* | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason |
* | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear |
* | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF |
* | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config |
* | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config |
* | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register |
* | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register |
* | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value |
* | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value |
* | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value |
* | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations |
* | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value |
* | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode |
* | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode |
* | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down |
* | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
*
* This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |--------------------------------------------|-------|---------------|---------------------------------------|
* | XPM_QID_INVALID | 0 | Both | Invalid Query ID |
* | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name |
* | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology |
* | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter |
* | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources |
* | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes |
* | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups |
* | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name |
* | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups |
* | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups |
* | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks |
* | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor |
* | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent |
* | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
*
* This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|-----------------------------------------------|
* | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power |
* | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature |
* | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency |
*
*****************************************************************************/
/**
* PM API IDs
*/
typedef enum {
PM_API_MIN, /**< 0x0 */
PM_GET_API_VERSION, /**< 0x1 */
PM_SET_CONFIGURATION, /**< 0x2 */
PM_GET_NODE_STATUS, /**< 0x3 */
PM_GET_OP_CHARACTERISTIC, /**< 0x4 */
PM_REGISTER_NOTIFIER, /**< 0x5 */
PM_REQUEST_SUSPEND, /**< 0x6 */
PM_SELF_SUSPEND, /**< 0x7 */
PM_FORCE_POWERDOWN, /**< 0x8 */
PM_ABORT_SUSPEND, /**< 0x9 */
PM_REQUEST_WAKEUP, /**< 0xA */
PM_SET_WAKEUP_SOURCE, /**< 0xB */
PM_SYSTEM_SHUTDOWN, /**< 0xC */
PM_REQUEST_NODE, /**< 0xD */
PM_RELEASE_NODE, /**< 0xE */
PM_SET_REQUIREMENT, /**< 0xF */
PM_SET_MAX_LATENCY, /**< 0x10 */
PM_RESET_ASSERT, /**< 0x11 */
PM_RESET_GET_STATUS, /**< 0x12 */
PM_MMIO_WRITE, /**< 0x13 */
PM_MMIO_READ, /**< 0x14 */
PM_INIT_FINALIZE, /**< 0x15 */
PM_FPGA_LOAD, /**< 0x16 */
PM_FPGA_GET_STATUS, /**< 0x17 */
PM_GET_CHIPID, /**< 0x18 */
PM_SECURE_RSA_AES, /**< 0x19 */
PM_SECURE_SHA, /**< 0x1A */
PM_SECURE_RSA, /**< 0x1B */
PM_PINCTRL_REQUEST, /**< 0x1C */
PM_PINCTRL_RELEASE, /**< 0x1D */
PM_PINCTRL_GET_FUNCTION, /**< 0x1E */
PM_PINCTRL_SET_FUNCTION, /**< 0x1F */
PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */
PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */
PM_IOCTL, /**< 0x22 */
PM_QUERY_DATA, /**< 0x23 */
PM_CLOCK_ENABLE, /**< 0x24 */
PM_CLOCK_DISABLE, /**< 0x25 */
PM_CLOCK_GETSTATE, /**< 0x26 */
PM_CLOCK_SETDIVIDER, /**< 0x27 */
PM_CLOCK_GETDIVIDER, /**< 0x28 */
PM_CLOCK_SETRATE, /**< 0x29 */
/* PM_CLOCK_GETRATE API is deprecated */
PM_RESERVE_ID, /**< 0x2A */
PM_CLOCK_SETPARENT, /**< 0x2B */
PM_CLOCK_GETPARENT, /**< 0x2C */
PM_SECURE_IMAGE, /**< 0x2D */
PM_FPGA_READ, /**< 0x2E */
PM_SECURE_AES, /**< 0x2F */
PM_PLL_SET_PARAMETER, /**< 0x30 */
PM_PLL_GET_PARAMETER, /**< 0x31 */
PM_PLL_SET_MODE, /**< 0x32 */
PM_PLL_GET_MODE, /**< 0x33 */
PM_REGISTER_ACCESS, /**< 0x34 */
PM_EFUSE_ACCESS, /**< 0x35 */
PM_ADD_SUBSYSTEM, /**< 0x36 */
PM_DESTROY_SUBSYSTEM, /**< 0x37 */
PM_DESCRIBE_NODES, /**< 0x38 */
PM_ADD_NODE, /**< 0x39 */
PM_ADD_NODE_PARENT, /**< 0x3A */
PM_ADD_NODE_NAME, /**< 0x3B */
PM_ADD_REQUIREMENT, /**< 0x3C */
PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */
PM_INIT_NODE, /**< 0x3E */
PM_FEATURE_CHECK, /**< 0x3F */
PM_ISO_CONTROL, /**< 0x40 */
PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */
PM_SET_NODE_ACCESS, /**< 0x42 */
PM_BISR, /**< 0x43 */
PM_APPLY_TRIM, /**< 0x44 */
PM_NOC_CLOCK_ENABLE, /**< 0x45 */
PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */
PM_FORCE_HOUSECLEAN, /**< 0x47 */
PM_FPGA_GET_VERSION, /**< 0x48 */
PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */
PM_API_MAX /**< 0x4A */
} XPm_ApiId;
#endif /* PM_API_VERSION_H_ */

13
bsp_z7/ps7_cortexa9_0/include/print.c
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@ -12,19 +12,22 @@
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
*/
*****************************************************************************/
/***************************** Include Files *********************************/
/*
* print -- do a raw print of a string
*/
#include "xil_printf.h"
/*****************************************************************************/
/**
* print -- do a raw print of a string
*
******************************************************************************/
void print(const char8 *ptr)
{
#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE)
XPVXenConsole_Write(ptr);
#else
#ifdef STDOUT_BASEADDRESS
#if defined(STDOUT_BASEADDRESS) || defined(SDT)
while (*ptr != (char8)0) {
outbyte (*ptr);
ptr++;

11
bsp_z7/ps7_cortexa9_0/include/sleep.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -30,7 +31,8 @@
* 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to
* u32 and usleep_MB parameter type from unsigned long to
* ULONG to fix misra_c_2012_rule_4_6 violation.
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* 9.1 mus 10/24/23 Add support for RISC-V.
* </pre>
*
******************************************************************************/
@ -87,6 +89,7 @@ extern "C" {
(timeout>0) ? 0 : -1; \
} )
/************************** Function Prototypes ******************************/
void usleep(ULONG useconds);
void sleep(u32 seconds);
void usleep_R5(ULONG useconds);
@ -97,6 +100,10 @@ int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
void sleep_riscv(u32 seconds);
void usleep_riscv(ULONG useconds);
/*****************************************************************************/
#ifdef __cplusplus
}

13
bsp_z7/ps7_cortexa9_0/include/xadcps.h
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@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xadcps.h
* @addtogroup xadcps_v2_6
* @addtogroup Overview
* @{
* @details
*
@ -157,6 +158,8 @@
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
* aad 12/17/20 Added missing function declarations and removed
* functions with no definitions.
* 2.7 cog 07/24/23 Added support for SDT flow
*
*
* </pre>
*
@ -300,7 +303,11 @@ extern "C" {
* device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Device base address */
} XAdcPs_Config;
@ -472,7 +479,11 @@ typedef struct {
/**
* Functions in xadcps_sinit.c
*/
#ifndef SDT
XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
#else
XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress);
#endif
/**
* Functions in xadcps.c

3
bsp_z7/ps7_cortexa9_0/include/xadcps_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xadcps_hw.h
* @addtogroup xadcps_v2_6
* @addtogroup Overview
* @{
*
* This header file contains identifiers and basic driver functions (or

18
bsp_z7/ps7_cortexa9_0/include/xcortexa9.h Normal file
View File

@ -0,0 +1,18 @@
/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
/**************************** Type Definitions ******************************/
typedef struct {
u32 CpuFreq;
} XCortexa9_Config;
#endif /* XIL_XCORTEXA9_H_ */

18
bsp_z7/ps7_cortexa9_0/include/xcortexa9_config.h Normal file
View File

@ -0,0 +1,18 @@
/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xcortexa9.h"
/************************** Variable Definitions ****************************/
extern XCortexa9_Config XCortexa9_ConfigTable;
/***************** Macros (Inline Functions) Definitions ********************/
#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq
#endif /* XIL_XCORTEXA9_CONFIG_H_ */

3
bsp_z7/ps7_cortexa9_0/include/xcpu_cortexa9.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xcpu_cortexa9.h
* @addtogroup cpu_cortexa9_v2_11
* @addtogroup cpu_cortexa9 Overview
* @{
* @details
*

6
bsp_z7/ps7_cortexa9_0/include/xdebug.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -61,13 +61,13 @@ int printf(const char *format, ...);
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_stmnt(x) /**< Debug statement */
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#define xdbg_printf(...) /**< Debug printf */
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */

48
bsp_z7/ps7_cortexa9_0/include/xdevcfg.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
* @details
*
@ -133,6 +134,7 @@
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of devcfg in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -178,8 +180,18 @@ typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDcfg_Config;
/**
@ -210,7 +222,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_Unlock(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
@ -230,8 +242,8 @@ typedef struct {
#define XDcfg_GetPsVersion(InstancePtr) \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_OFFSET)) & \
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
@ -250,7 +262,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_ReadMultiBootConfig(InstancePtr) \
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MULTIBOOT_ADDR_OFFSET)
XDCFG_MULTIBOOT_ADDR_OFFSET)
/****************************************************************************/
@ -269,8 +281,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectIcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
/****************************************************************************/
/**
@ -288,8 +300,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectPcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
@ -298,7 +310,11 @@ typedef struct {
/*
* Lookup configuration in xdevcfg_sinit.c.
*/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xdevcfg_selftest.c
@ -309,7 +325,7 @@ int XDcfg_SelfTest(XDcfg *InstancePtr);
* Interface functions in xdevcfg.c
*/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
void XDcfg_EnablePCAP(XDcfg *InstancePtr);
@ -344,12 +360,12 @@ u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength);
u32 SrcWordLength, u32 DestWordLength);
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
/*
* Interrupt related function prototypes implemented in xdevcfg_intr.c
@ -367,7 +383,7 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
void XDcfg_InterruptHandler(XDcfg *InstancePtr);
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef);
void *CallBackRef);
#ifdef __cplusplus
}

28
bsp_z7/ps7_cortexa9_0/include/xdevcfg_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_hw.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the hardware interface to the Device Config Interface.
@ -26,6 +27,7 @@
* version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -210,14 +212,14 @@ extern "C" {
* of Init Signal
*/
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
@ -266,9 +268,9 @@ extern "C" {
* Status
*/
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
/**< BBRAM key
* disable
*/
/**< BBRAM key
* disable
*/
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
* Enable Status
*/

56
bsp_z7/ps7_cortexa9_0/include/xdmaps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
* @details
*
@ -60,6 +61,7 @@
* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
* to static inline to avoid the linkage conflict for IAR compiler.
* 2.9 aj 11/07/23 Added support for system device tree
* </pre>
*
*****************************************************************************/
@ -88,8 +90,19 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of device (IPIF) */
#ifdef SDT
u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDmaPs_Config;
@ -169,15 +182,15 @@ typedef struct {
* It's the done handler a user can set for a channel
*/
typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
/**
* It's the fault handler a user can set for a channel
*/
typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
#define XDMAPS_MAX_CHAN_BUFS 2
#define XDMAPS_CHAN_BUF_LEN 128
@ -236,18 +249,18 @@ typedef struct {
* Functions implemented in xdmaps.c
*/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr);
XDmaPs_Config *Config,
u32 EffectiveAddr);
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
@ -256,13 +269,13 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
int XDmaPs_Instr_DMARMB(char *DmaProg);
@ -276,10 +289,10 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg);
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns);
u32 Imm, unsigned int Ns);
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations);
unsigned LoopIterations);
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
@ -312,7 +325,12 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr);
/*
* Static loopup function implemented in xdmaps_sinit.c
*/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress);
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress);
#endif
/*

9
bsp_z7/ps7_cortexa9_0/include/xdmaps_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_hw.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
@ -233,7 +234,7 @@ extern "C" {
#define XDMAPS_INTCLR_ALL_MASK 0xFF
#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
Xil_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
@ -251,7 +252,7 @@ extern "C" {
* u32 RegisterValue)
******************************************************************************/
#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes *****************************/

101
bsp_z7/ps7_cortexa9_0/include/xemacps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
* @details
*
@ -417,15 +418,15 @@ extern "C" {
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
@ -456,11 +457,11 @@ extern "C" {
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
@ -500,7 +501,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
u32 ErrorWord);
/*@}*/
@ -508,12 +509,25 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifdef SDT
char *Name; /**< Unique name of the device */
#else
u16 DeviceId; /**< Unique ID of device */
#endif
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#if defined (XCLOCKING)
#ifdef SDT
u16 IntrId;
UINTPTR IntrParent;
#endif
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clock */
#endif
#ifdef SDT
char *PhyType; /**< PhyType indicates which type of PHY interface is
* used (MII, GMII, RGMII, etc.
*/
#endif
u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
@ -606,8 +620,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -627,8 +641,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -648,8 +662,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -669,8 +683,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -687,10 +701,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
@ -711,9 +725,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
@ -734,9 +748,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
@ -761,10 +775,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
/****************************************************************************/
/**
@ -781,8 +795,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_GetRXWatermark(InstancePtr) \
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
/*
* Initialization functions in xemacps.c
*/
@ -797,7 +811,12 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
/*
* Lookup configuration in xemacps_sinit.c
*/
#ifndef SDT
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
#else
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Interrupt-related functions in xemacps_intr.c
@ -823,7 +842,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,

10
bsp_z7/ps7_cortexa9_0/include/xemacps_bd.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bd.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header provides operations to manage buffer descriptors in support
@ -45,6 +46,7 @@
* 3.2 hk 11/18/15 Change BD typedef and number of words.
* 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
* 3.9 aj 22/03/24 Add mask for XEmaPs_BdGetBufAddr
*
* </pre>
*
@ -239,11 +241,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
#endif
/*****************************************************************************/

5
bsp_z7/ps7_cortexa9_0/include/xemacps_bdring.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs

2
bsp_z7/ps7_cortexa9_0/include/xemacps_hw.h
View File

@ -8,7 +8,7 @@
/**
*
* @file xemacps_hw.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or

33
bsp_z7/ps7_cortexa9_0/include/xgpiops.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -124,6 +124,11 @@
* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
* 3.9 sne 03/15/21 Fixed MISRA-C violations.
* 3.11 sg 02/23/23 Update bank and pin mapping information.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto
* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable,
* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin
* to add multi-core interrupt support.
*
* </pre>
*
@ -167,6 +172,7 @@ extern "C" {
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
@ -209,8 +215,18 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XGpioPs_Config;
/**
@ -227,6 +243,7 @@ typedef struct {
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */
} XGpioPs;
/************************** Variable Definitions *****************************/
@ -262,12 +279,12 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
@ -283,14 +300,18 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif

2
bsp_z7/ps7_cortexa9_0/include/xgpiops_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

4
bsp_z7/ps7_cortexa9_0/include/xil_cache.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -26,6 +27,7 @@
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
* APIs.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* 9.0 ml 03/03/23 Updated function prototypes.
* </pre>
*
******************************************************************************/

50
bsp_z7/ps7_cortexa9_0/include/xil_cryptoalginfo.h Normal file
View File

@ -0,0 +1,50 @@
/******************************************************************************/
/**
* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_cryptoalginfo.h
* @{
* @details
*
* Crypto algotithm information structure declaration.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 9.0 mmd 07/04/23 First release.
* </pre>
*
*****************************************************************************/
#ifndef XIL_CRYPTOALGINFO_H
#define XIL_CRYPTOALGINFO_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/**************************** Type Definitions *******************************/
typedef enum _Xil_CryptoAlgNistStatus {
NOT_APPLICABLE = 0x00,
NIST_COMPLIANT = 0x11,
NIST_NON_COMPLIANT = 0xFE,
} Xil_CryptoAlgNistStatus;
typedef struct _Xil_CryptoAlgInfo {
u32 Version;
Xil_CryptoAlgNistStatus NistStatus;
} Xil_CryptoAlgInfo;
#ifdef __cplusplus
}
#endif
#endif /* XIL_CRYPTOALGINFO_H */

10
bsp_z7/ps7_cortexa9_0/include/xil_exception.h
View File

@ -75,8 +75,10 @@
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#include "xdebug.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -228,7 +230,7 @@ extern "C" {
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
#else
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
@ -267,7 +269,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
@ -295,7 +297,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* @note None.
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
#else
@ -315,7 +317,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always disable FIQ

133
bsp_z7/ps7_cortexa9_0/include/xil_io.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -32,12 +33,12 @@
* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
* when -Werror=conversion compiler flag is enabled
* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
*
* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings.
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifndef XIL_IO_H /**< prevent circular inclusions */
#define XIL_IO_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -63,25 +64,25 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */
# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */
# define INST_SYNC isb() /**< Instruction Synchronization Barrier */
# define DATA_SYNC dsb() /**< Data Synchronization Barrier */
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
# define SYNCHRONIZE_IO /**< Data Memory Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#define INLINE inline /**< static inline keyword */
#else
#define INLINE __inline
#define INLINE __inline /**<static inline keyword */
#endif
/*****************************************************************************/
@ -91,7 +92,7 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
@ -109,7 +110,7 @@ static INLINE u8 Xil_In8(UINTPTR Addr)
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
@ -126,7 +127,7 @@ static INLINE u16 Xil_In16(UINTPTR Addr)
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
@ -143,7 +144,7 @@ static INLINE u32 Xil_In32(UINTPTR Addr)
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
@ -159,8 +160,8 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* @param Addr contains the address to perform the output operation
* @param Value contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
@ -275,7 +276,7 @@ static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
*
* @brief Perform a 16-bit endian conversion.
*
* @param Data: 16 bit value to be converted
* @param Data 16 bit value to be converted
*
* @return 16 bit Data with converted endianness
*
@ -290,7 +291,7 @@ static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
*
* @brief Perform a 32-bit endian conversion.
*
* @param Data: 32 bit value to be converted
* @param Data : 32 bit value to be converted
*
* @return 32 bit data with converted endianness
*
@ -317,42 +318,47 @@ static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
# define Xil_In16BE Xil_In16 /**< Register Read of 16 Bits in Big Endian */
# define Xil_In32BE Xil_In32 /**< Register Read of 32 Bits in Big Endian */
# define Xil_Out16BE Xil_Out16 /**< Register Write of 16 Bits in Big Endian */
# define Xil_Out32BE Xil_Out32 /**< Register Write of 32 Bits in Big Endian */
# define Xil_Htons(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Htonl(Data) (Data) /**< Endian swap of 32 bits */
# define Xil_Ntohs(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Ntohl(Data) (Data) /**< Endian swap of 32 bits */
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
static INLINE u16 Xil_In16BE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Big Endian */
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
static INLINE u16 Xil_In16LE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
@ -362,11 +368,16 @@ static INLINE u16 Xil_In16BE(UINTPTR Addr)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
static INLINE u32 Xil_In32BE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Big Endian */
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
static INLINE u32 Xil_In32LE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 32 Bits in Big Endian.
**********************************************************************************/
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
@ -376,11 +387,16 @@ static INLINE u32 Xil_In32BE(UINTPTR Addr)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Big Endian */
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to write Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
@ -390,11 +406,16 @@ static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Big Endian */
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{

8
bsp_z7/ps7_cortexa9_0/include/xil_mem.h
View File

@ -1,6 +1,6 @@
/******************************************************************************/
/**
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -23,12 +23,12 @@
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
* 7.0 mus 01/07/19 Add cpp extern macro
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
*****************************************************************************/
#ifndef XIL_MEM_H /* prevent circular inclusions */
#define XIL_MEM_H /* by using protection macros */
#ifndef XIL_MEM_H /**< prevent circular inclusions */
#define XIL_MEM_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {

8
bsp_z7/ps7_cortexa9_0/include/xil_misc_psreset_api.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -15,12 +16,13 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */
#define XIL_MISC_RESET_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {

601
bsp_z7/ps7_cortexa9_0/include/xil_printf.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 1995 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*---------------------------------------------------*/
@ -12,24 +13,38 @@
#include "xil_printf.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "bspconfig.h"
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
static void padding( const s32 l_flag,const struct params_s *par);
/************************** Function Prototypes ******************************/
static void padding( const s32 l_flag, const struct params_s *par);
static void outs(const charptr lp, struct params_s *par);
static s32 getnum( charptr* linep);
static s32 getnum( charptr *linep);
/**************************** Type Definitions *******************************/
typedef struct params_s {
s32 len;
s32 num1;
s32 num2;
char8 pad_character;
s32 do_padding;
s32 left_flag;
s32 unsigned_flag;
s32 len; /**< length */
s32 num1; /**< number 1 */
s32 num2; /**< number 2 */
char8 pad_character; /**< pad character */
s32 do_padding; /**< do padding */
s32 left_flag; /**< left flag */
s32 unsigned_flag; /**< unsigned flag */
} params_t;
/***************** Macros (Inline Functions) Definitions *********************/
#if (defined(__MICROBLAZE__)) && (!defined(__arch64__))
#define MICROBLAZE32
#endif
#if (!defined(MICROBLAZE32)) && (!defined(ZYNQMP_R5_FSBL_BSP)) && (!defined(DISABLE_64BIT_PRINT))
#define SUPPORT_64BIT_PRINT
#endif
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
@ -40,107 +55,109 @@ typedef struct params_s {
/*---------------------------------------------------*/
/*---------------------------------------------------*/
/* */
/* This routine puts pad characters into the output */
/* buffer. */
/* */
/*****************************************************************************/
/**
* This routine puts pad characters into the output buffer.
*
******************************************************************************/
static void padding( const s32 l_flag, const struct params_s *par)
{
s32 i;
s32 i;
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i=(par->len);
for (; i<(par->num1); i++) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( par->pad_character);
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i = (par->len);
for (; i < (par->num1); i++) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( par->pad_character);
#endif
}
}
}
}
/*---------------------------------------------------*/
/* */
/* This routine moves a string to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
/******************************************************************************/
/**
* This routine moves a string to the output buffer
* as directed by the padding and positioning flags.
*
*******************************************************************************/
static void outs(const charptr lp, struct params_s *par)
{
charptr LocalPtr;
charptr LocalPtr;
LocalPtr = lp;
/* pad on left if needed */
if(LocalPtr != NULL) {
/* pad on left if needed */
if (LocalPtr != NULL) {
par->len = (s32)strlen( LocalPtr);
padding( !(par->left_flag), par);
/* Move string to the buffer */
while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
(par->num2)--;
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte(*LocalPtr);
#endif
LocalPtr += 1;
}
}
/* Pad on right if needed */
/* CR 439175 - elided next stmt. Seemed bogus. */
padding( par->left_flag, par);
}
/* Pad on right if needed */
/* CR 439175 - elided next stmt. Seemed bogus. */
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
/* This routine moves a number to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
/*****************************************************************************/
/**
*
* This routine moves a number to the output buffer
* as directed by the padding and positioning flags.
*
******************************************************************************/
static void outnum( const s32 n, const s32 base, struct params_s *par)
{
s32 negative;
s32 negative;
s32 i;
char8 outbuf[32];
const char8 digits[] = "0123456789ABCDEF";
u32 num;
for(i = 0; i<32; i++) {
outbuf[i] = '0';
}
char8 outbuf[32];
const char8 digits[] = "0123456789ABCDEF";
u32 num;
for (i = 0; i < 32; i++) {
outbuf[i] = '0';
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num =(-(n));
}
else{
num = n;
negative = 0;
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num = (-(n));
} else {
num = n;
negative = 0;
}
/* Build number (backwards) in outbuf */
i = 0;
do {
/* Build number (backwards) in outbuf */
i = 0;
do {
outbuf[i] = digits[(num % (u32)base)];
i++;
num /= base;
} while (num > 0U);
} while (num > 0U);
if (negative != 0) {
if (negative != 0) {
outbuf[i] = '-';
i++;
}
outbuf[i] = '\0';
i--;
outbuf[i] = '\0';
i--;
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( outbuf[i] );
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( outbuf[i] );
#endif
i--;
}
padding( par->left_flag, par);
}
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
@ -148,96 +165,98 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
/* buffer as directed by the padding and positioning */
/* flags. */
/* */
#if defined (__aarch64__) || defined (__arch64__)
#if defined (SUPPORT_64BIT_PRINT)
static void outnum1( const s64 n, const s32 base, params_t *par)
{
s32 negative;
s32 negative;
s32 i;
char8 outbuf[64];
const char8 digits[] = "0123456789ABCDEF";
u64 num;
for(i = 0; i<64; i++) {
outbuf[i] = '0';
}
char8 outbuf[64];
const char8 digits[] = "0123456789ABCDEF";
u64 num;
for (i = 0; i < 64; i++) {
outbuf[i] = '0';
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num =(-(n));
}
else{
num = (n);
negative = 0;
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num = (-(n));
} else {
num = (n);
negative = 0;
}
/* Build number (backwards) in outbuf */
i = 0;
do {
/* Build number (backwards) in outbuf */
i = 0;
do {
outbuf[i] = digits[(num % base)];
i++;
num /= base;
} while (num > 0);
} while (num > 0);
if (negative != 0) {
if (negative != 0) {
outbuf[i] = '-';
i++;
}
outbuf[i] = '\0';
i--;
outbuf[i] = '\0';
i--;
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
outbyte( outbuf[i] );
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
outbyte( outbuf[i] );
i--;
}
padding( par->left_flag, par);
}
padding( par->left_flag, par);
}
#endif
/*---------------------------------------------------*/
/* */
/* This routine gets a number from the format */
/* string. */
/* */
static s32 getnum(charptr* linep)
/*****************************************************************************/
/**
*
* This routine gets a number from the format string.
*
******************************************************************************/
static s32 getnum(charptr *linep)
{
s32 n = 0;
s32 ResultIsDigit = 0;
charptr cptr = *linep;
while (cptr != NULL) {
ResultIsDigit = isdigit(((u8)*cptr));
ResultIsDigit = isdigit(((u8) * cptr));
if (ResultIsDigit == 0) {
break;
}
n = ((n*10) + (((s32)*cptr) - (s32)'0'));
n = ((n * 10) + (((s32) * cptr) - (s32)'0'));
cptr += 1;
}
*linep = ((charptr)(cptr));
return(n);
return (n);
}
/*---------------------------------------------------*/
/* */
/* This routine operates just like a printf/sprintf */
/* routine. It outputs a set of data under the */
/* control of a formatting string. Not all of the */
/* standard C format control are supported. The ones */
/* provided are primarily those needed for embedded */
/* systems work. Primarily the floating point */
/* routines are omitted. Other formats could be */
/* added easily by following the examples shown for */
/* the supported formats. */
/* */
/* void esp_printf( const func_ptr f_ptr,
const charptr ctrl1, ...) */
/*****************************************************************************/
/**
* This routine operates just like a printf/sprintf
* routine. It outputs a set of data under the
* control of a formatting string. Not all of the
* standard C format control are supported. The ones
* provided are primarily those needed for embedded
* systems work. Primarily the floating point
* routines are omitted. Other formats could be
* added easily by following the examples shown for
* the supported formats.
* void esp_printf( const func_ptr f_ptr,
* const charptr ctrl1, ...)
*
*******************************************************************************/
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
void xil_printf( const char8 *ctrl1, ...){
void xil_printf( const char8 *ctrl1, ...)
{
XPVXenConsole_Printf(ctrl1);
}
#else
@ -253,195 +272,205 @@ void xil_printf( const char8 *ctrl1, ...)
}
#endif
/* This routine is equivalent to vprintf routine */
/*****************************************************************************/
/**
* This routine is equivalent to vprintf routine
******************************************************************************/
void xil_vprintf(const char8 *ctrl1, va_list argp)
{
s32 Check;
#if defined (__aarch64__) || defined (__arch64__)
s32 long_flag;
#if defined (SUPPORT_64BIT_PRINT)
s32 long_flag;
#endif
s32 dot_flag;
s32 dot_flag;
u32 width, index;
params_t par;
params_t par;
u8 ch;
char8 *ctrl = (char8 *)ctrl1;
const char *string;
u8 ch;
char8 *ctrl = (char8 *)ctrl1;
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte(*ctrl);
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte(*ctrl);
#endif
ctrl += 1;
continue;
}
continue;
}
/* initialize all the flags for this format. */
dot_flag = 0;
#if defined (__aarch64__) || defined (__arch64__)
/* initialize all the flags for this format. */
dot_flag = 0;
#if defined (SUPPORT_64BIT_PRINT)
long_flag = 0;
#endif
par.unsigned_flag = 0;
par.unsigned_flag = 0;
par.left_flag = 0;
par.do_padding = 0;
par.pad_character = ' ';
par.num2=32767;
par.num1=0;
par.len=0;
par.pad_character = ' ';
par.num2 = 32767;
par.num1 = 0;
par.len = 0;
try_next:
if(ctrl != NULL) {
try_next:
if (ctrl != NULL) {
ctrl += 1;
}
if(ctrl != NULL) {
ch = (u8)*ctrl;
if (ctrl != NULL) {
ch = (u8) * ctrl;
} else {
break;
}
if (isdigit(ch) != 0) {
if (dot_flag != 0) {
par.num2 = getnum(&ctrl);
}
else {
if (ch == (u8)'0') {
par.pad_character = '0';
if (isdigit(ch) != 0) {
if (dot_flag != 0) {
par.num2 = getnum(&ctrl);
} else {
if (ch == (u8)'0') {
par.pad_character = '0';
}
if(ctrl != NULL) {
par.num1 = getnum(&ctrl);
if (ctrl != NULL) {
par.num1 = getnum(&ctrl);
}
par.do_padding = 1;
}
if(ctrl != NULL) {
ctrl -= 1;
par.do_padding = 1;
}
goto try_next;
}
if (ctrl != NULL) {
ctrl -= 1;
}
goto try_next;
}
switch (tolower(ch)) {
case '%':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( '%');
switch (tolower(ch)) {
case '%':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( '%');
#endif
Check = 1;
break;
case '-':
par.left_flag = 1;
Check = 0;
break;
case '.':
dot_flag = 1;
Check = 0;
break;
case 'l':
#if defined (__aarch64__) || defined (__arch64__)
long_flag = 1;
#endif
Check = 0;
break;
case 'u':
par.unsigned_flag = 1;
/* fall through */
case 'i':
case 'd':
#if defined (__aarch64__) || defined (__arch64__)
if (long_flag != 0){
outnum1((s64)va_arg(argp, s64), 10L, &par);
}
else {
outnum( va_arg(argp, s32), 10L, &par);
}
#else
outnum( va_arg(argp, s32), 10L, &par);
#endif
Check = 1;
break;
case 'p':
#if defined (__aarch64__) || defined (__arch64__)
par.unsigned_flag = 1;
outnum1((s64)va_arg(argp, s64), 16L, &par);
Check = 1;
break;
#endif
case 'X':
case 'x':
par.unsigned_flag = 1;
#if defined (__aarch64__) || defined (__arch64__)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 16L, &par);
break;
case '-':
par.left_flag = 1;
Check = 0;
break;
case '.':
if ((*(ctrl + 1) == '*') && (*(ctrl + 2) == 's')) {
width = va_arg(argp, u32);
string = va_arg(argp, const char *);
for (index = 0; index < width && string[index] != '\0' ; index++) {
outbyte(string[index]);
}
ctrl += 2;
} else {
dot_flag = 1;
Check = 0;
}
else {
outnum((s32)va_arg(argp, s32), 16L, &par);
}
#else
outnum((s32)va_arg(argp, s32), 16L, &par);
#endif
Check = 1;
break;
break;
case 's':
outs( va_arg( argp, char *), &par);
Check = 1;
break;
case 'l':
#if defined (SUPPORT_64BIT_PRINT)
long_flag = 1;
#endif
Check = 0;
break;
case 'c':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( (char8)va_arg( argp, s32));
case 'u':
par.unsigned_flag = 1;
/* fall through */
case 'i':
case 'd':
#if defined (SUPPORT_64BIT_PRINT)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 10L, &par);
} else {
outnum( va_arg(argp, s32), 10L, &par);
}
#else
outnum( va_arg(argp, s32), 10L, &par);
#endif
Check = 1;
break;
Check = 1;
break;
case 'p':
#if defined (__aarch64__) || defined (__arch64__)
par.unsigned_flag = 1;
outnum1((s64)va_arg(argp, s64), 16L, &par);
Check = 1;
break;
#endif
case 'X':
case 'x':
par.unsigned_flag = 1;
#if defined (SUPPORT_64BIT_PRINT)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 16L, &par);
} else {
outnum((s32)va_arg(argp, s32), 16L, &par);
}
#else
outnum((s32)va_arg(argp, s32), 16L, &par);
#endif
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x07));
#endif
break;
case 'h':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x08));
#endif
break;
case 'r':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x0D));
#endif
break;
case 'n':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
#endif
break;
default:
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( *ctrl);
#endif
break;
}
ctrl += 1;
Check = 0;
break;
case 's':
outs( va_arg( argp, char *), &par);
Check = 1;
break;
default:
Check = 1;
break;
}
if(Check == 1) {
if(ctrl != NULL) {
case 'c':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( (char8)va_arg( argp, s32));
#endif
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x07));
#endif
break;
case 'h':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x08));
#endif
break;
case 'r':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x0D));
#endif
break;
case 'n':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
#endif
break;
default:
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( *ctrl);
#endif
break;
}
ctrl += 1;
Check = 0;
break;
default:
Check = 1;
break;
}
if (Check == 1) {
if (ctrl != NULL) {
ctrl += 1;
}
continue;
}
goto try_next;
}
continue;
}
goto try_next;
}
}
/*---------------------------------------------------*/

16
bsp_z7/ps7_cortexa9_0/include/xil_printf.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef XIL_PRINTF_H
@ -13,8 +14,10 @@ extern "C" {
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
@ -38,13 +41,14 @@ struct params_s;
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
/************************** Function Prototypes ******************************/
/**< prints the statement */
void xil_printf( const char8 *ctrl1, ...);
/**< This routine is equivalent to vprintf routine */
void xil_vprintf(const char8 *ctrl1, va_list argp);
void print( const char8 *ptr);
extern void outbyte (uint8_t c);
extern char inbyte(void);
extern void outbyte (char c); /**< To send byte */
extern char inbyte(void); /**< To receive byte */
#ifdef __cplusplus
}

6
bsp_z7/ps7_cortexa9_0/include/xil_sleepcommon.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -21,6 +22,7 @@
* violation.
* 8.0 sk 03/02/22 Update usleep argument type to fix misra_c_2012_
* directive_4_6 violation.
* 9.1 mus 10/24/23 Add support for RISC-V.
* </pre>
******************************************************************************/
@ -52,6 +54,8 @@
sleep_A53(seconds);
#elif defined (__MICROBLAZE__)
sleep_MB(seconds);
#elif defined (__riscv)
sleep_riscv(seconds);
#else
sleep_A9(seconds);
#endif
@ -78,6 +82,8 @@
usleep_A53(useconds);
#elif defined (__MICROBLAZE__)
usleep_MB(useconds);
#elif defined (__riscv)
usleep_riscv(useconds);
#else
usleep_A9(useconds);
#endif

11
bsp_z7/ps7_cortexa9_0/include/xil_sleeptimer.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -24,7 +25,7 @@
* misra_c_2012_rule_12_1 violation.
* 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration
* to fix misra_c_2012_rule_8_2 violation.
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*****************************************************************************/
@ -103,8 +104,12 @@ extern "C" {
*/
/************************** Function Prototypes ******************************/
/**< This is a helper function used by sleep/usleep APIs to
* have delay in sec/usec */
void Xil_SleepTTCCommon(u32 delay, u64 frequency);
void XTime_StartTTCTimer(void);
void XTime_StartTTCTimer(void); /**< This API starts the Triple
* Timer Counter */
#endif

13
bsp_z7/ps7_cortexa9_0/include/xil_spinlock.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -23,12 +24,13 @@
* if condition to fix misrac violations.
* 7.7 sk 01/10/22 Update XIL_SPINLOCK_ENABLED from signed to unsigned to
* fix misra_c_2012_rule_10_4 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_SPINLOCK_H /* prevent circular inclusions */
#define XIL_SPINLOCK_H /* by using protection macros */
#ifndef XIL_SPINLOCK_H /**< prevent circular inclusions */
#define XIL_SPINLOCK_H /**< by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
@ -61,7 +63,8 @@ u32 Xil_IsSpinLockEnabled(void);
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinLock(); }
#else
#define XIL_SPINLOCK()
#define XIL_SPINLOCK() /**< protect multiple applications running at separate
* CPUs to write to the same register */
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
@ -69,7 +72,7 @@ u32 Xil_IsSpinLockEnabled(void);
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinUnlock(); }
#else
#define XIL_SPINUNLOCK()
#define XIL_SPINUNLOCK() /**< Release the lock previously taken */
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/

94
bsp_z7/ps7_cortexa9_0/include/xil_testio.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -16,6 +17,7 @@
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* 9.00 ml 04/26/23 Updated code to fix sizeof_mismatch coverity warnings.
* </pre>
*
*****************************************************************************/
@ -90,9 +92,9 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
s32 Status = 0;
for (Index = 0; Index < Length; Index++) {
Xil_Out8((INTPTR)Addr, Value);
Xil_Out8((UINTPTR)Addr, Value);
ValueIn = Xil_In8((INTPTR)Addr);
ValueIn = Xil_In8((UINTPTR)Addr);
if ((Value != ValueIn) && (Status == 0)) {
Status = -1;
@ -134,23 +136,24 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
u16 *TempAddr16;
u16 ValueIn = 0U;
s32 Index;
u32 Size_16;
TempAddr16 = Addr;
Xil_AssertNonvoid(TempAddr16 != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out16LE((INTPTR)TempAddr16, Value);
break;
case XIL_TESTIO_BE:
Xil_Out16BE((INTPTR)TempAddr16, Value);
break;
default:
Xil_Out16((INTPTR)TempAddr16, Value);
break;
case XIL_TESTIO_LE:
Xil_Out16LE((UINTPTR)TempAddr16, Value);
break;
case XIL_TESTIO_BE:
Xil_Out16BE((UINTPTR)TempAddr16, Value);
break;
default:
Xil_Out16((UINTPTR)TempAddr16, Value);
break;
}
ValueIn = Xil_In16((INTPTR)TempAddr16);
ValueIn = Xil_In16((UINTPTR)TempAddr16);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap16(ValueIn);
@ -161,18 +164,18 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
}
/* second round */
Xil_Out16((INTPTR)TempAddr16, Value);
Xil_Out16((UINTPTR)TempAddr16, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In16LE((INTPTR)TempAddr16);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In16BE((INTPTR)TempAddr16);
break;
default:
ValueIn = Xil_In16((INTPTR)TempAddr16);
break;
case XIL_TESTIO_LE:
ValueIn = Xil_In16LE((UINTPTR)TempAddr16);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In16BE((UINTPTR)TempAddr16);
break;
default:
ValueIn = Xil_In16((UINTPTR)TempAddr16);
break;
}
@ -183,7 +186,8 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
if (Value != ValueIn) {
return -1;
}
TempAddr16 += sizeof(u16);
Size_16 = sizeof(u16);
TempAddr16 += Size_16;
}
return 0;
}
@ -218,23 +222,24 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
u32 *TempAddr;
u32 ValueIn = 0U;
s32 Index;
u32 Size_32;
TempAddr = Addr;
Xil_AssertNonvoid(TempAddr != NULL);
for (Index = 0; Index < Length; Index++) {
switch (Kind) {
case XIL_TESTIO_LE:
Xil_Out32LE((INTPTR)TempAddr, Value);
break;
case XIL_TESTIO_BE:
Xil_Out32BE((INTPTR)TempAddr, Value);
break;
default:
Xil_Out32((INTPTR)TempAddr, Value);
break;
case XIL_TESTIO_LE:
Xil_Out32LE((UINTPTR)TempAddr, Value);
break;
case XIL_TESTIO_BE:
Xil_Out32BE((UINTPTR)TempAddr, Value);
break;
default:
Xil_Out32((UINTPTR)TempAddr, Value);
break;
}
ValueIn = Xil_In32((INTPTR)TempAddr);
ValueIn = Xil_In32((UINTPTR)TempAddr);
if ((Kind != 0) && (Swap != 0)) {
ValueIn = Swap32(ValueIn);
@ -245,19 +250,19 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
}
/* second round */
Xil_Out32((INTPTR)TempAddr, Value);
Xil_Out32((UINTPTR)TempAddr, Value);
switch (Kind) {
case XIL_TESTIO_LE:
ValueIn = Xil_In32LE((INTPTR)TempAddr);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In32BE((INTPTR)TempAddr);
break;
default:
ValueIn = Xil_In32((INTPTR)TempAddr);
break;
case XIL_TESTIO_LE:
ValueIn = Xil_In32LE((UINTPTR)TempAddr);
break;
case XIL_TESTIO_BE:
ValueIn = Xil_In32BE((UINTPTR)TempAddr);
break;
default:
ValueIn = Xil_In32((UINTPTR)TempAddr);
break;
}
if ((Kind != 0) && (Swap != 0)) {
@ -267,7 +272,8 @@ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
if (Value != ValueIn) {
return -1;
}
TempAddr += sizeof(u32);
Size_32 = sizeof(u32);
TempAddr += Size_32;
}
return 0;
}

224
bsp_z7/ps7_cortexa9_0/include/xil_testmem.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -34,6 +35,10 @@
* 21_2 violation.
* 7.7 sk 01/10/22 Remove arithematic operations on pointer varaible to fix
* misra_c_2012_rule_18_4 violation.
* 9.0 ml 08/30/23 Update Memory tests API in BSP, to not to stress test by
default.
* 9.1 ml 02/02/23 Fix compilation warnings report with
* XIL_ENABLE_MEMORY_STRESS_TEST
* </pre>
*
*****************************************************************************/
@ -46,7 +51,9 @@
/************************** Constant Definitions ****************************/
/************************** Function Prototypes *****************************/
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
static u32 RotateLeft(u32 Input, u8 Width);
#endif
/* define ROTATE_RIGHT to give access to this functionality */
#ifdef ROTATE_RIGHT
@ -86,11 +93,15 @@ static u32 RotateRight(u32 Input, u8 Width);
s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u8 Val;
u8 WordMem8;
s32 Status = 0;
u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
@ -104,14 +115,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
* select the proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from XIL_TESTMEM_INIT_VALUE
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
sbea(Addr+I, Val);
sbea(Addr + I, Val);
Val++;
}
/*
@ -128,7 +139,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = lbuea(Addr+I);
WordMem8 = lbuea(Addr + I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
@ -136,8 +147,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
@ -155,7 +166,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
*/
for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
/* write memory location */
sbea(Addr+I, Val);
sbea(Addr + I, Val);
Val = (u8)RotateLeft(Val, 8U);
}
/*
@ -166,7 +177,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
/* Read the values from each location that was written */
for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
/* read memory location */
WordMem8 = lbuea(Addr+I);
WordMem8 = lbuea(Addr + I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
@ -176,7 +187,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking zeros test
@ -194,7 +205,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
*/
for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
/* write memory location */
sbea(Addr+I, Val);
sbea(Addr + I, Val);
Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
}
/*
@ -205,7 +216,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
/* Read the values from each location that was written */
for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
/* read memory location */
WordMem8 = lbuea(Addr+I);
WordMem8 = lbuea(Addr + I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
@ -216,12 +227,12 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < Words; I++) {
/* write memory location */
Val = (u8) (~((INTPTR) (Addr + I)));
sbea(Addr+I, Val);
sbea(Addr + I, Val);
}
/*
@ -231,8 +242,8 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = lbuea(Addr+I);
Val = (u8) (~((INTPTR) (Addr+I)));
WordMem8 = lbuea(Addr + I);
Val = (u8) (~((INTPTR) (Addr + I)));
if ((WordMem8 ^ Val) != 0x00U) {
Status = -1;
goto End_Label;
@ -240,7 +251,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
@ -248,8 +259,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
if (Pattern == (u8)0) {
Val = 0xA5U;
}
else {
} else {
Val = Pattern;
}
/*
@ -257,7 +267,7 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
*/
for (I = 0U; I < Words; I++) {
/* write memory location */
sbea(Addr+I, Val);
sbea(Addr + I, Val);
}
/*
* Check every word within the words
@ -267,14 +277,14 @@ s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
for (I = 0U; I < Words; I++) {
/* read memory location */
WordMem8 = lbuea(Addr+I);
WordMem8 = lbuea(Addr + I);
if (WordMem8 != Val) {
Status = -1;
goto End_Label;
}
}
}
#endif
End_Label:
return Status;
}
@ -308,14 +318,18 @@ End_Label:
* patterns used not to repeat over the region tested.
*
*****************************************************************************/
s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
s32 Xil_TestMem16(u32 Addrlow, u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u16 Val;
u16 WordMem16;
s32 Status = 0;
u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
@ -329,14 +343,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
* selectthe proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'XIL_TESTMEM_INIT_VALUE'
*/
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
/* write memory location */
shea(Addr+I, Val);
shea(Addr + I, Val);
Val++;
I = I + NUM_OF_BYTES_IN_HW;
}
@ -355,7 +369,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
/* read memory location */
WordMem16 = lhuea(Addr+I);
WordMem16 = lhuea(Addr + I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
@ -364,8 +378,8 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
I = I + NUM_OF_BYTES_IN_HW;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking ones test
@ -385,7 +399,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
/* write memory location */
shea(Addr+I,Val);
shea(Addr + I, Val);
Val = (u16)RotateLeft(Val, 16U);
I = I + NUM_OF_BYTES_IN_HW;
}
@ -397,7 +411,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
/* Read the values from each location that was written */
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
/* read memory location */
WordMem16 = lhuea(Addr+I);
WordMem16 = lhuea(Addr + I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
@ -408,7 +422,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking zeros test
@ -428,7 +442,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
*/
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) {
shea(Addr+I, Val);
shea(Addr + I, Val);
Val = ~((u16)RotateLeft(~Val, 16U));
I = I + NUM_OF_BYTES_IN_HW;
}
@ -439,7 +453,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
Val = ~(1U << j);
/* Read the values from each location that was written */
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
WordMem16= lhuea(Addr+I);
WordMem16 = lhuea(Addr + I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
@ -451,12 +465,12 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
/* write memory location */
Val = (u16) (~((INTPTR)((Addr+I))));
shea(Addr+I, Val);
Val = (u16) (~((INTPTR)((Addr + I))));
shea(Addr + I, Val);
I = I + NUM_OF_BYTES_IN_HW;
}
/*
@ -464,10 +478,10 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
* of tested memory
*/
for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) {
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words); ) {
/* read memory location */
WordMem16 = lhuea(Addr+I);
Val = (u16) (~((INTPTR) ((Addr+I))));
WordMem16 = lhuea(Addr + I);
Val = (u16) (~((INTPTR) ((Addr + I))));
if ((WordMem16 ^ Val) != 0x0000U) {
Status = -1;
goto End_Label;
@ -476,15 +490,14 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
*/
if (Pattern == (u16)0) {
Val = 0xDEADU;
}
else {
} else {
Val = Pattern;
}
@ -492,9 +505,9 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
* Fill the memory with fixed pattern
*/
for (I = 0U; I < (2*Words);) {
for (I = 0U; I < (2 * Words);) {
/* write memory location */
shea(Addr+I, Val);
shea(Addr + I, Val);
I = I + NUM_OF_BYTES_IN_HW;
}
@ -506,7 +519,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
/* read memory location */
WordMem16=lhuea(Addr+I);
WordMem16 = lhuea(Addr + I);
if (WordMem16 != Val) {
Status = -1;
goto End_Label;
@ -514,6 +527,7 @@ s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
I = I + NUM_OF_BYTES_IN_HW;
}
}
#endif
End_Label:
return Status;
}
@ -549,11 +563,15 @@ End_Label:
s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
{
u32 I;
u32 j;
u32 Val;
u32 WordMem32;
s32 Status = 0;
u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
@ -564,13 +582,13 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
Val = XIL_TESTMEM_INIT_VALUE;
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'XIL_TESTMEM_INIT_VALUE'
*/
for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) {
swea(Addr+I, Val);
for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
swea(Addr + I, Val);
Val++;
I = I + NUM_OF_BYTES_IN_WORD;
}
@ -589,7 +607,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
*/
for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) {
WordMem32 = lwea(Addr+I);
WordMem32 = lwea(Addr + I);
if (WordMem32 != Val) {
Status = -1;
@ -600,8 +618,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
I = I + NUM_OF_BYTES_IN_WORD;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
@ -622,7 +640,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) {
/* write memory location */
swea(Addr+I, Val);
swea(Addr + I, Val);
Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD);
I = I + NUM_OF_BYTES_IN_WORD;
}
@ -638,7 +656,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) {
/* read memory location */
WordMem32 = lwea(Addr+I);
WordMem32 = lwea(Addr + I);
if (WordMem32 != Val) {
Status = -1;
@ -651,7 +669,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible
* initial test Patterns for walking zeros test
@ -673,7 +691,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
/* write memory location */
swea(Addr+I, Val);
swea(Addr + I, Val);
Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
I = I + NUM_OF_BYTES_IN_WORD;
}
@ -689,7 +707,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
* written */
for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
/* read memory location */
WordMem32 = lwea(Addr+I);
WordMem32 = lwea(Addr + I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
@ -701,12 +719,12 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
/* write memory location */
Val = (u32) (~((INTPTR) (Addr+I)));
swea(Addr+I, Val);
Val = (u32) (~((INTPTR) (Addr + I)));
swea(Addr + I, Val);
I = I + NUM_OF_BYTES_IN_WORD;
}
@ -717,8 +735,8 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
/* Read the location */
WordMem32 = lwea(Addr+I);
Val = (u32) (~((INTPTR) (Addr+I)));
WordMem32 = lwea(Addr + I);
Val = (u32) (~((INTPTR) (Addr + I)));
if ((WordMem32 ^ Val) != 0x00000000U) {
Status = -1;
@ -728,7 +746,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
@ -736,8 +754,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
if (Pattern == (u32)0) {
Val = 0xDEADBEEFU;
}
else {
} else {
Val = Pattern;
}
@ -747,7 +764,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
/* write memory location */
swea(Addr+I, Val);
swea(Addr + I, Val);
I = I + NUM_OF_BYTES_IN_WORD;
}
@ -761,7 +778,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
/* read memory location */
WordMem32 = lwea(Addr+I);
WordMem32 = lwea(Addr + I);
if (WordMem32 != Val) {
Status = -1;
goto End_Label;
@ -769,7 +786,7 @@ s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
I = I + NUM_OF_BYTES_IN_WORD;
}
}
#endif
End_Label:
return Status;
}
@ -805,11 +822,15 @@ End_Label:
s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
{
u32 i;
u32 j;
u32 Val;
u32 FirtVal;
u32 WordMem32;
s32 Status = 0;
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
@ -821,7 +842,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
FirtVal = XIL_TESTMEM_INIT_VALUE;
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
@ -855,8 +876,8 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
@ -904,7 +925,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible
* initial test Patterns for walking zeros test
@ -952,7 +973,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (i = 0U; i < Words; i++) {
/* write memory location */
@ -977,7 +998,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
@ -985,8 +1006,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
if (Pattern == (u32)0) {
Val = 0xDEADBEEFU;
}
else {
} else {
Val = Pattern;
}
@ -1016,7 +1036,7 @@ s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
}
}
}
#endif
End_Label:
return Status;
}
@ -1051,11 +1071,15 @@ End_Label:
s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
{
u32 i;
u32 j;
u16 Val;
u16 FirtVal;
u16 WordMem16;
s32 Status = 0;
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
@ -1070,7 +1094,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
* selectthe proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
@ -1102,8 +1126,8 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking ones test
@ -1144,7 +1168,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking zeros test
@ -1187,7 +1211,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (i = 0U; i < Words; i++) {
/* write memory location */
@ -1210,15 +1234,14 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
*/
if (Pattern == (u16)0) {
Val = 0xDEADU;
}
else {
} else {
Val = Pattern;
}
@ -1246,7 +1269,7 @@ s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
}
}
}
#endif
End_Label:
return Status;
}
@ -1282,11 +1305,15 @@ End_Label:
s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
{
u32 i;
u32 j;
u8 Val;
u8 FirtVal;
u8 WordMem8;
s32 Status = 0;
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
u32 j;
#else
(void)Pattern;
#endif
Xil_AssertNonvoid(Words != (u32)0);
Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
@ -1301,7 +1328,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
* select the proper Subtest(s)
*/
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
/*
* Fill the memory with incrementing
* values starting from 'FirtVal'
@ -1333,8 +1360,8 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
Val++;
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
/*
* set up to cycle through all possible initial
* test Patterns for walking ones test
@ -1373,7 +1400,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
/*
* set up to cycle through all possible initial test
* Patterns for walking zeros test
@ -1413,7 +1440,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
/* Fill the memory with inverse of address */
for (i = 0U; i < Words; i++) {
/* write memory location */
@ -1437,7 +1464,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
}
}
if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
if ((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
/*
* Generate an initial value for
* memory testing
@ -1445,8 +1472,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
if (Pattern == (u8)0) {
Val = 0xA5U;
}
else {
} else {
Val = Pattern;
}
/*
@ -1471,7 +1497,7 @@ s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
}
}
}
#endif
End_Label:
return Status;
}
@ -1489,6 +1515,7 @@ End_Label:
*
*
*****************************************************************************/
#ifdef XIL_ENABLE_MEMORY_STRESS_TEST
static u32 RotateLeft(u32 Input, u8 Width)
{
u32 Msb;
@ -1524,6 +1551,7 @@ static u32 RotateLeft(u32 Input, u8 Width)
return ReturnVal;
}
#endif
#ifdef ROTATE_RIGHT
/*****************************************************************************/

4
bsp_z7/ps7_cortexa9_0/include/xil_testmem.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -103,7 +104,10 @@ extern "C" {
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/

12
bsp_z7/ps7_cortexa9_0/include/xil_types.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -27,8 +27,9 @@
* 7.00 mus 01/07/19 Add cpp extern macro
* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
* is 64-bit processor
* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types
* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types
* incase of microblaze 32-bit with extended address enabled
* 9.0 ml 14/04/23 Add parenthesis on sub-expression to fix misra-c violation.
* </pre>
*
******************************************************************************/
@ -45,7 +46,10 @@ extern "C" {
#include <stdint.h>
#include <stddef.h>
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -163,6 +167,10 @@ typedef void (*XInterruptHandler) (void *InstancePtr);
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
#if defined (__riscv_xlen) && (__riscv_xlen == 64)
#define __arch64__
#endif
/**
* @brief Returns 32-63 bits of a number.
* @param n : Number being accessed.

287
bsp_z7/ps7_cortexa9_0/include/xil_util.c
View File

@ -1,7 +1,7 @@
/******************************************************************************/
/**
* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -85,6 +85,12 @@
* 8.1 sa 10/20/22 Change the type of first argument passed to Xil_WaitForEvents
* API from u32 to UINTPTR for supporting 64 bit addressing.
* 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* 9.0 ml 04/26/23 Updated code to fix DC.STRING BUFFER and VARARGS coverity warnings.
* 9.0 ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to
* fix MISRA-C violations for Rule 4.6
* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function
*
* </pre>
*
*****************************************************************************/
@ -94,7 +100,7 @@
#include "sleep.h"
/************************** Constant Definitions ****************************/
#define MAX_NIBBLES 8U
#define MAX_NIBBLES 8U /**< maximum nibbles */
/************************** Function Prototypes *****************************/
void (*fptr)(void) = NULL;
@ -119,8 +125,7 @@ static size_t strnlen (const char *StartPtr, size_t StrSize)
EndPtr = memchr(StartPtr, '\0', StrSize);
if (EndPtr == NULL) {
StrLen = StrSize;
}
else {
} else {
StrLen = (size_t) (EndPtr - StartPtr);
}
@ -140,13 +145,13 @@ static size_t strnlen (const char *StartPtr, size_t StrSize)
*******************************************************************************/
s32 Xil_Ceil(float Value)
{
s32 Result = Value;
s32 Result = Value;
if (Value > Result) {
Result = Result + 1;
}
Result = Result + 1;
}
return Result;
return Result;
}
/****************************************************************************/
@ -174,16 +179,13 @@ u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
*Num = InChar - (u8)'0';
Status = XST_SUCCESS;
}
else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
} else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
*Num = InChar - (u8)'a' + 10U;
Status = XST_SUCCESS;
}
else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
} else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
*Num = InChar - (u8)'A' + 10U;
Status = XST_SUCCESS;
}
else {
} else {
Status = XST_FAILURE;
}
@ -218,8 +220,8 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
while (ConvertedLen < Len) {
for (i = 0U; i < MAX_NIBBLES; i++) {
Status = Xil_ConvertCharToNibble((u8)Str[ConvertedLen],
&Nibble[i]);
ConvertedLen = ConvertedLen +1U;
&Nibble[i]);
ConvertedLen = ConvertedLen + 1U;
if (Status != XST_SUCCESS) {
/* Error converting char to nibble */
goto END;
@ -227,9 +229,9 @@ u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
}
buf[index] = (((u32)Nibble[0] << (u8)28U) | ((u32)Nibble[1] << (u8)24U) |
((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) |
((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) |
((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]);
((u32)Nibble[2] << (u8)20U) | ((u32)Nibble[3] << (u8)16U) |
((u32)Nibble[4] << (u8)12U) | ((u32)Nibble[5] << (u8)8U) |
((u32)Nibble[6] << (u8)4U) | (u32)Nibble[7]);
index++;
}
END:
@ -246,7 +248,8 @@ END:
* @return None.
*
*****************************************************************************/
void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) {
void Xil_RegisterPlmHandler(void (*PlmAlive) (void))
{
fptr = PlmAlive;
}
@ -259,7 +262,8 @@ void Xil_RegisterPlmHandler(void (*PlmAlive) (void)) {
* @return None.
*
*****************************************************************************/
void Xil_PlmStubHandler(void) {
void Xil_PlmStubHandler(void)
{
if (fptr != NULL) {
fptr();
}
@ -288,7 +292,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout)
u32 PollCount = Timeout;
u32 Status = XST_FAILURE;
while(PollCount > 0U) {
while (PollCount > 0U) {
EventStatus = Xil_In32(RegAddr) & EventMask;
if (EventStatus == Event) {
Status = XST_SUCCESS;
@ -323,7 +327,7 @@ u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout)
*
******************************************************************************/
u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents,
u32 Timeout, u32* Events)
u32 Timeout, u32 *Events)
{
u32 EventStatus;
u32 PollCount = Timeout;
@ -333,7 +337,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents,
do {
EventStatus = Xil_In32(EventsRegAddr);
EventStatus &= EventsMask;
if((EventStatus & WaitEvents) != 0U) {
if ((EventStatus & WaitEvents) != 0U) {
Status = XST_SUCCESS;
*Events = EventStatus;
break;
@ -343,8 +347,7 @@ u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents,
Xil_PlmStubHandler();
#endif
usleep(1U);
}
while(PollCount > 0U);
} while (PollCount > 0U);
return Status;
}
@ -366,12 +369,12 @@ u32 Xil_IsValidHexChar(const char *Ch)
{
u32 Status = XST_FAILURE;
if(NULL == Ch) {
if (NULL == Ch) {
goto END;
}
if (((*Ch >= '0') && (*Ch <='9'))||
((*Ch >= 'a') && (*Ch <='f'))||
((*Ch >= 'A') && (*Ch <='F'))) {
if (((*Ch >= '0') && (*Ch <= '9')) ||
((*Ch >= 'a') && (*Ch <= 'f')) ||
((*Ch >= 'A') && (*Ch <= 'F'))) {
Status = XST_SUCCESS;
}
@ -399,7 +402,7 @@ u32 Xil_ValidateHexStr(const char *HexStr)
u32 Len;
u32 Status = XST_INVALID_PARAM;
if(NULL == HexStr) {
if (NULL == HexStr) {
goto END;
}
@ -466,21 +469,20 @@ u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
goto END;
}
if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
ConvertedLen = 0U;
while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]),&UpperNibble)
== (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen+1U]),
&LowerNibble) == (u32)XST_SUCCESS)) {
Buf[ConvertedLen/2U] =
if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]), &UpperNibble)
== (u32)XST_SUCCESS) && (Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]),
&LowerNibble) == (u32)XST_SUCCESS)) {
Buf[ConvertedLen / 2U] =
(UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
LowerNibble;
}
else {
LowerNibble;
} else {
Status = (u32)XST_INVALID_PARAM;
goto END;
}
@ -528,7 +530,7 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
goto END;
}
if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
if (Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
Status = XST_INVALID_PARAM;
goto END;
}
@ -537,15 +539,14 @@ u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
ConvertedLen = 0U;
while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
if ((Xil_ConvertCharToNibble(((u8)Str[ConvertedLen]),
&UpperNibble) == XST_SUCCESS) &&
(Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]),
&LowerNibble) == XST_SUCCESS)) {
Buf[StrIndex] =
(UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
LowerNibble;
StrIndex = StrIndex - 1U;
}
else {
&UpperNibble) == XST_SUCCESS) &&
(Xil_ConvertCharToNibble(((u8)Str[ConvertedLen + 1U]),
&LowerNibble) == XST_SUCCESS)) {
Buf[StrIndex] =
(UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
LowerNibble;
StrIndex = StrIndex - 1U;
} else {
Status = XST_INVALID_PARAM;
goto END;
}
@ -580,7 +581,7 @@ u32 Xil_Strnlen(const char *Str, u32 MaxLen)
goto END;
}
while(StrLen < MaxLen) {
while (StrLen < MaxLen) {
if ('\0' == *InStr) {
break;
}
@ -625,7 +626,7 @@ void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
{
int Status = XST_FAILURE;
u32 Count;
@ -665,8 +666,8 @@ END:
* @note None
*
****************************************************************************/
int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen)
s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen)
{
int Status = XST_FAILURE;
u32 SrcLength;
@ -693,7 +694,7 @@ int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
goto END;
}
for (Index = From; (Index <= To) && (Src[Index]!= (u8)'\0'); Index++) {
for (Index = From; (Index <= To) && (Src[Index] != (u8)'\0'); Index++) {
Dest[Index - From] = Src[Index];
}
@ -716,7 +717,7 @@ END:
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size)
{
int Status = XST_FAILURE;
u32 Count = 0U;
@ -761,7 +762,7 @@ END:
* @return XST_SUCCESS on success and error code on failure
*
******************************************************************************/
int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len)
{
int Status = XST_FAILURE;
u8 *Dest = (u8 *)DestPtr;
@ -807,7 +808,7 @@ END:
* 1 if first non-matching character is greater value in Buf1Ptr
*
******************************************************************************/
int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len)
{
volatile int RetVal = 1;
const u8 *Buf1 = Buf1Ptr;
@ -854,7 +855,7 @@ END:
* - XST_SUCCESS: If Zeroization is successful.
* - XST_FAILURE: If Zeroization is not successful.
********************************************************************************/
int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
{
u32 Index;
int Status = XST_FAILURE;
@ -863,7 +864,7 @@ int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
(void)memset(DataPtr, 0, Length);
/* Read it back to verify */
for (Index = 0U; Index < Length; Index++) {
for (Index = 0U; Index < Length; Index++) {
if (DataPtr[Index] != 0x00U) {
goto END;
}
@ -895,18 +896,16 @@ END:
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SMemCmp(const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen)
s32 Xil_SMemCmp(const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen)
{
int Status = XST_FAILURE;
if ((Src1 == NULL) || (Src2 == NULL)) {
Status = XST_INVALID_PARAM;
}
else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) {
} else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
Status = memcmp (Src1, Src2, CmpLen);
if (Status != 0) {
Status = XST_FAILURE;
@ -937,8 +936,8 @@ int Xil_SMemCmp(const void *Src1, const u32 Src1Size,
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen)
s32 Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen)
{
volatile int Status = XST_FAILURE;
volatile int StatusRedundant = XST_FAILURE;
@ -951,13 +950,11 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size,
if ((Src1 == NULL) || (Src2 == NULL)) {
Status = XST_INVALID_PARAM;
}
else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) {
} else if ((CmpLen == 0U) || (Src1Size < CmpLen) || (Src2Size < CmpLen)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
while (Cnt >= sizeof(u32)) {
Data |= (*(const u32 *)Src_1 ^ *(const u32 *)Src_2);
Data |= (*(const u32 *)Src_1 ^ * (const u32 *)Src_2);
DataRedundant &= ~Data;
Src_1 += sizeof(u32);
Src_2 += sizeof(u32);
@ -998,29 +995,26 @@ int Xil_SMemCmp_CT(const void *Src1, const u32 Src1Size,
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SMemCpy(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen)
s32 Xil_SMemCpy(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen)
{
int Status = XST_FAILURE;
const u8 *Src8 = (const u8 *) Src;
const u8 *Dst8 = (u8 *) Dest;
void * volatile DestTemp = Dest;
const void * volatile SrcTemp = Src;
void *volatile DestTemp = Dest;
const void *volatile SrcTemp = Src;
if ((Dest == NULL) || (Src == NULL)) {
Status = XST_INVALID_PARAM;
}
else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) {
} else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) {
Status = XST_INVALID_PARAM;
}
/* Return error for overlap string */
else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) {
Status = XST_INVALID_PARAM;
}
else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) {
} else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
(void)memcpy(DestTemp, SrcTemp, CopyLen);
Status = XST_SUCCESS;
}
@ -1045,15 +1039,14 @@ int Xil_SMemCpy(void *Dest, const u32 DestSize,
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SMemSet(void *Dest, const u32 DestSize,
const u8 Data, const u32 Len)
s32 Xil_SMemSet(void *Dest, const u32 DestSize,
const u8 Data, const u32 Len)
{
int Status = XST_FAILURE;
if ((Dest == NULL) || (DestSize < Len) || (Len == 0U)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
(void)memset(Dest, (s32)Data, Len);
Status = XST_SUCCESS;
}
@ -1077,29 +1070,29 @@ int Xil_SMemSet(void *Dest, const u32 DestSize,
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SStrCat (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize)
s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize)
{
int Status = XST_FAILURE;
u32 SrcLen;
u32 DstLen;
u32 Length;
if ((DestStr == NULL) || (SrcStr == NULL)) {
Status = XST_INVALID_PARAM;
goto END;
}
SrcLen = strnlen((const char*)SrcStr, SrcSize);
DstLen = strnlen((const char*)DestStr, DestSize);
SrcLen = strnlen((const char *)SrcStr, SrcSize);
DstLen = strnlen((const char *)DestStr, DestSize);
Length = SrcLen + DstLen;
if ((DestSize <= DstLen) || (SrcSize <= SrcLen)) {
Status = XST_INVALID_PARAM;
}
else if (DestSize <= (SrcLen + DstLen)) {
} else if (DestSize <= Length) {
Status = XST_INVALID_PARAM;
}
else {
(void)strcat((char*)DestStr, (const char*)SrcStr);
} else {
(void)strncat((char *)DestStr, (const char *)SrcStr, Length);
Status = XST_SUCCESS;
}
@ -1124,8 +1117,8 @@ END:
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size)
s32 Xil_SStrCmp(const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size)
{
int Status = XST_FAILURE;
u32 Str1Len = 0U;
@ -1136,16 +1129,14 @@ int Xil_SStrCmp(const u8 *Str1, const u32 Str1Size,
goto END;
}
Str1Len = strnlen((const char*)Str1, Str1Size);
Str2Len = strnlen((const char*)Str2, Str2Size);
Str1Len = strnlen((const char *)Str1, Str1Size);
Str2Len = strnlen((const char *)Str2, Str2Size);
if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) {
Status = XST_INVALID_PARAM;
}
else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) {
} else if ((Str1Len < Str2Len) || (Str1Len > Str2Len)) {
Status = XST_FAILURE;
}
else {
} else {
Status = memcmp(Str1, Str2, Str1Len);
if (Status != 0) {
Status = XST_FAILURE;
@ -1177,8 +1168,8 @@ END:
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size)
s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size)
{
int Status = XST_FAILURE;
u32 Str1Len = 0U;
@ -1189,16 +1180,14 @@ int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
goto END;
}
Str1Len = strnlen((const char*)Str1, Str1Size);
Str2Len = strnlen((const char*)Str2, Str2Size);
Str1Len = strnlen((const char *)Str1, Str1Size);
Str2Len = strnlen((const char *)Str2, Str2Size);
if ((Str1Size <= Str1Len) || (Str2Size <= Str2Len)) {
Status = XST_INVALID_PARAM;
}
else if (Str1Len != Str2Len) {
} else if (Str1Len != Str2Len) {
Status = XST_FAILURE;
}
else {
} else {
Status = Xil_SMemCmp_CT (Str1, Str1Size, Str2, Str2Size, Str1Len);
}
@ -1222,8 +1211,8 @@ END:
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SStrCpy(u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize)
s32 Xil_SStrCpy(u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize)
{
int Status = XST_FAILURE;
u32 SrcLen = 0U;
@ -1233,12 +1222,11 @@ int Xil_SStrCpy(u8 *DestStr, const u32 DestSize,
goto END;
}
SrcLen = strnlen((const char*)SrcStr, SrcSize);
SrcLen = strnlen((const char *)SrcStr, SrcSize);
if ((DestSize <= SrcLen) || (SrcSize <= SrcLen)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
(void)memcpy(DestStr, SrcStr, SrcLen + 1U);
Status = XST_SUCCESS;
}
@ -1263,19 +1251,17 @@ END:
* XST_INVALID_PARAM - Invalid inputs
*
*****************************************************************************/
int Xil_SMemMove(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen)
s32 Xil_SMemMove(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen)
{
volatile int Status = XST_FAILURE;
const void *Output = NULL;
if ((Dest == NULL) || (Src == NULL)) {
Status = XST_INVALID_PARAM;
}
else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) {
} else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) {
Status = XST_INVALID_PARAM;
}
else {
} else {
Output = memmove(Dest, Src, CopyLen);
if (Output != NULL) {
Status = XST_SUCCESS;
@ -1313,7 +1299,7 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, .
va_start(Event, EventAddr);
/* wait for all events to complete */
for (i = 0; i < NumOfEvents; i++) {
while(PollCount > 0U) {
while (PollCount > 0U) {
if (Xil_In32((UINTPTR)EventAddr)) {
LoopCnt++;
break;
@ -1330,13 +1316,13 @@ u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, .
EventAddr = va_arg(Event, volatile u32 *);
PollCount = Timeout;
}
va_end(Event);
END:
if (LoopCnt == NumOfEvents) {
Status = XST_SUCCESS;
}
va_end(Event);
return Status;
}
@ -1369,9 +1355,58 @@ s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value)
/* verify value written to specified address */
ReadReg = Xil_In32(Addr) & Mask;
if(ReadReg == (Mask & Value)) {
if (ReadReg == (Mask & Value)) {
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
* @brief This function changes the endianness of source data and copies it
* into destination buffer.
*
* @param Dest - Pointer to destination memory
* @param DestSize - Memory available at destination
* @param Src - Pointer to source memory
* @param SrcSize - Maximum data that can be copied from source
* @param CopyLen - Number of bytes to be copied
*
* @return
* XST_SUCCESS - Copy is successful
* XST_INVALID_PARAM - Invalid inputs
* XST_FAILURE - On failure
*
*****************************************************************************/
s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen)
{
s32 Status = XST_FAILURE;
volatile u32 Index;
const u8 *Src8 = (const u8 *) Src;
const u8 *Dst8 = (u8 *) Dest;
u8 *DestTemp = Dest;
const u8 *SrcTemp = Src;
if ((Dest == NULL) || (Src == NULL)) {
Status = XST_INVALID_PARAM;
} else if ((CopyLen == 0U) || (DestSize < CopyLen) || (SrcSize < CopyLen)) {
Status = XST_INVALID_PARAM;
}
/* Return error for overlap string */
else if ((Src8 < Dst8) && (&Src8[CopyLen - 1U] >= Dst8)) {
Status = XST_INVALID_PARAM;
} else if ((Dst8 < Src8) && (&Dst8[CopyLen - 1U] >= Src8)) {
Status = XST_INVALID_PARAM;
} else {
for (Index = 0U; Index < CopyLen; Index++) {
DestTemp[Index] = SrcTemp[CopyLen - Index - 1U];
}
if (Index == CopyLen) {
Status = XST_SUCCESS;
}
}
return Status;
}

174
bsp_z7/ps7_cortexa9_0/include/xil_util.h
View File

@ -1,7 +1,7 @@
/******************************************************************************/
/**
* Copyright (c) 2019 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -61,6 +61,12 @@
* 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs.
* bm 03/14/23 Added XSECURE_REDUNDANT_CALL and XSECURE_REDUNDANT_IMPL macros
* sk 03/14/23 Added Status Check Glitch detect Macro
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* mmd 07/09/23 Added macro to build version
* ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to
* fix MISRA-C violations for Rule 4.6
* 9.1 kpt 02/21/24 Added Xil_SChangeEndiannessAndCpy function
*
* </pre>
*
*****************************************************************************/
@ -72,19 +78,33 @@
extern "C" {
#endif
/******************************* Include Files ********************************/
#include "xil_types.h"
#include "xil_io.h"
#include "xstatus.h"
/*************************** Constant Definitions *****************************/
#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
#define XIL_SIZE_OF_BYTE_IN_BITS 8U
/* Maximum string length handled by Xil_ValidateHexStr function */
#define XIL_MAX_HEX_STR_LEN 512U
#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U /**< size of nibble in bits */
#define XIL_SIZE_OF_BYTE_IN_BITS 8U /**< size of byte in bits */
#define XIL_MAX_HEX_STR_LEN 512U /**< Maximum string length handled by
Xil_ValidateHexStr function */
/****************** Macros (Inline Functions) Definitions *********************/
/******************************************************************************/
/**
*
* Builds version number by concatenates 16-bit Major version and Minor version.
*
* @param Major is the 16-bit major version number
* @param Minor is the 16-bit minor version number
*
* @return 32-bit version number
*
******************************************************************************/
#define XIL_BUILD_VERSION(Major, Minor) ((((u32)Major) << 16U) | (Minor))
#ifdef __GNUC__
/******************************************************************************/
/**
@ -103,12 +123,12 @@ extern "C" {
*
******************************************************************************/
#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
{ \
Var = XST_FAILURE; \
VarTmp = XST_FAILURE; \
Var = Function(__VA_ARGS__); \
VarTmp = Var; \
}
{ \
Var = XST_FAILURE; \
VarTmp = XST_FAILURE; \
Var = Function(__VA_ARGS__); \
VarTmp = Var; \
}
/******************************************************************************/
/**
@ -133,14 +153,14 @@ extern "C" {
volatile int StatusTmp; \
XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
if ((Status != XST_SUCCESS) || \
(StatusTmp != XST_SUCCESS)) { \
(StatusTmp != XST_SUCCESS)) { \
if (((Status) != (StatusTmp)) || \
(Status == XST_SUCCESS)) { \
(Status == XST_SUCCESS)) { \
Status = XST_GLITCH_ERROR; \
}\
goto Label; \
} \
}
}
/******************************************************************************/
/**
@ -163,7 +183,7 @@ extern "C" {
{ \
Status = Function(__VA_ARGS__); \
StatusTmp = Function(__VA_ARGS__); \
}
}
/******************************************************************************/
/**
@ -182,7 +202,7 @@ extern "C" {
{ \
Function(__VA_ARGS__); \
Function(__VA_ARGS__); \
}
}
/******************************************************************************/
/**
@ -204,110 +224,114 @@ extern "C" {
#endif
/*************************** Function Prototypes ******************************/
/* Ceils the provided float value */
/**< Ceils the provided float value */
s32 Xil_Ceil(float Value);
/* Converts input character to nibble */
/**< Converts input character to nibble */
u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
/* Convert input hex string to array of 32-bits integers */
/**< Convert input hex string to array of 32-bits integers */
u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
#ifdef VERSAL_PLM
/* Register PLM handler */
/**< Register PLM handler */
void Xil_RegisterPlmHandler(void (*PlmAlive) (void));
/* Call PLM handler */
/**< Call PLM handler */
void Xil_PlmStubHandler(void);
#endif
/* Waits for specified event */
/**< Waits for specified event */
u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout);
/* Waits for specified events */
/**< Waits for specified events */
u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents,
u32 Timeout, u32* Events);
u32 Timeout, u32 *Events);
/* Validate input hex character */
/**< Validate input hex character */
u32 Xil_IsValidHexChar(const char *Ch);
/* Validate the input string contains only hexadecimal characters */
/**< Validate the input string contains only hexadecimal characters */
u32 Xil_ValidateHexStr(const char *HexStr);
/* Convert string to hex numbers in little enidian format */
/**< Convert string to hex numbers in little enidian format */
u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
/* Returns length of the input string */
/**< Returns length of the input string */
u32 Xil_Strnlen(const char *Str, u32 MaxLen);
/* Convert string to hex numbers in big endian format */
u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
/**< Convert string to hex numbers in big endian format */
u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len);
/*Read, Modify and Write to an address*/
/**< Read, Modify and Write to an address*/
void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
/* Copies source string to destination string */
int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
/**< Copies source string to destination string */
s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
/* Copies specified range from source string to destination string */
int Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen);
/**< Copies specified range from source string to destination string */
s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen);
/* Appends string2 to string1 */
int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
/**< Appends string2 to string1 */
s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size);
/* Copies Len bytes from source memory to destination memory */
int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
/**< Copies Len bytes from source memory to destination memory */
s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len);
/* Compares Len bytes from memory1 and memory2 */
int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
/**< Compares Len bytes from memory1 and memory2 */
s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len);
/* Zeroizes the memory of given length */
int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
/**< Zeroizes the memory of given length */
s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
/* Copies Len bytes from source memory to destination memory */
int Xil_SMemCpy (void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
/**< Copies Len bytes from source memory to destination memory */
s32 Xil_SMemCpy (void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
/* Copies Len bytes from source memory to destination memory, allows
/**< Copies Len bytes from source memory to destination memory, allows
overlapped memory between source and destination */
int Xil_SMemMove(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
s32 Xil_SMemMove(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
/* Compares Len bytes between source and destination memory */
int Xil_SMemCmp (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/**< Compares Len bytes between source and destination memory */
s32 Xil_SMemCmp (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/* Compares Len bytes between source and destination memory with constant time */
int Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/**< Compares Len bytes between source and destination memory with constant time */
s32 Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/* Sets the destination memory of given length with given data */
int Xil_SMemSet (void *Dest, const u32 DestSize,
const u8 Data, const u32 Len);
/**< Sets the destination memory of given length with given data */
s32 Xil_SMemSet (void *Dest, const u32 DestSize,
const u8 Data, const u32 Len);
/* Copies source string to destination string */
int Xil_SStrCpy (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/**< Copies source string to destination string */
s32 Xil_SStrCpy (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/* Compares source string with destination string */
int Xil_SStrCmp (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/**< Compares source string with destination string */
s32 Xil_SStrCmp (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/* Compares source string with destination string with constant time */
int Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/**< Compares source string with destination string with constant time */
s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/* Concatenates source string to destination string */
int Xil_SStrCat (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/**< Concatenates source string to destination string */
s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/* Waits for event timeout */
/**< Waits for event timeout */
u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...);
/* Implements Read Modify Writes securely */
/**< Implements Read Modify Writes securely */
s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value);
/**< Changes byte endianness of source buffer and copies it into destination */
s32 Xil_SChangeEndiannessAndCpy(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
#ifdef __cplusplus
}
#endif

67
bsp_z7/ps7_cortexa9_0/include/xilffs.h Normal file
View File

@ -0,0 +1,67 @@
/******************************************************************************
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilffs.h
* @addtogroup xilffs Overview
* @{
* @details
*
* This file contains declarations specific to AMD's unique requirements and
* functionalities for xilffs.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.2 ht 10/10/23 Added code for versioning of library.
*
*</pre>
*
*@note
*****************************************************************************/
#ifndef XILFFS_H
#define XILFFS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_util.h"
#include "xil_io.h"
#include "xil_types.h"
/************************** Constant Definitions *****************************/
/* Library version info */
#define XILFFS_MAJOR_VERSION 5U
#define XILFFS_MINOR_VERSION 2U
/****************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* @brief This function returns the version number of xilffs library.
*
* @return 32-bit version number
*
******************************************************************************/
static __attribute__((always_inline)) INLINE
u32 Xilffs_GetLibVersion(void)
{
return (XIL_BUILD_VERSION(XILFFS_MAJOR_VERSION, XILFFS_MINOR_VERSION));
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* XILFFS_H */

25
bsp_z7/ps7_cortexa9_0/include/xparameters.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XPARAMETERS_H /* prevent circular inclusions */
@ -7,7 +8,6 @@
/* Definition for CPU ID */
#define XPAR_CPU_ID 0U
//#define USE_AMP 0U TODO having this to 0 breaks xil_cache
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
@ -23,17 +23,8 @@
#include "xparameters_ps.h"
// Default is for Zedboard
#ifndef ZYNQ_USE_UART0
#define STDIN_BASEADDRESS XPS_UART1_BASEADDR
#define STDIN_INT_NR XPAR_XUARTPS_1_INTR
#define STDOUT_BASEADDRESS XPS_UART1_BASEADDR
#else
#define STDIN_BASEADDRESS XPS_UART0_BASEADDR
#define STDIN_INT_NR XPAR_XUARTPS_0_INTR
#define STDOUT_BASEADDRESS XPS_UART0_BASEADDR
#endif
#define STDIN_BASEADDRESS 0xE0001000
#define STDOUT_BASEADDRESS 0xE0001000
/******************************************************************/
@ -357,6 +348,7 @@
#define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_200_DDR_OTAP_DLY 0
/******************************************************************/
@ -380,6 +372,7 @@
#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_200_DDR_OTAP_DLY 0
/******************************************************************/
@ -428,8 +421,8 @@
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_BASEADDR 0xE0000000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0000FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
@ -438,8 +431,8 @@
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_XUARTPS_0_BASEADDR 0xE0000000
#define XPAR_XUARTPS_0_HIGHADDR 0xE0000FFF
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_XUARTPS_0_HAS_MODEM 0

121
bsp_z7/ps7_cortexa9_0/include/xplatform_info.c
View File

@ -43,6 +43,9 @@
* reported with "-Wundef" flag CR#1111453
* 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now
* they are supported only for VERSAL_NET APU and RPU.
* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be
* used to identify type of boot (cold/warm).
* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor.
* </pre>
*
******************************************************************************/
@ -102,17 +105,17 @@ u32 XGet_Zynq_UltraMp_Platform_info(void)
{
#if defined (__aarch64__) && (EL1_NONSECURE == 1)
XSmc_OutVar reg;
/*
/*
* This SMC call will return,
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
*/
reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0);
return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
#else
u32 reg;
reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
& XPLAT_INFO_MASK);
& XPLAT_INFO_MASK);
return reg;
#endif
}
@ -130,24 +133,71 @@ u32 XGet_Zynq_UltraMp_Platform_info(void)
u32 XGetPSVersion_Info(void)
{
#if defined (__aarch64__) && (EL1_NONSECURE == 1)
/*
* This SMC call will return,
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
*/
XSmc_OutVar reg;
reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
XPS_VERSION_INFO_SHIFT);
/*
* This SMC call will return,
* idcode - upper 32 bits of reg.Arg0
* version - lower 32 bits of reg.Arg1
*/
XSmc_OutVar reg;
reg = Xil_Smc(GET_CHIPID_SMC_FID, 0, 0, 0, 0, 0, 0, 0);
return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
XPS_VERSION_INFO_SHIFT);
#else
u32 reg;
reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
& XPS_VERSION_INFO_MASK);
& XPS_VERSION_INFO_MASK);
return (reg >> XPS_VERSION_INFO_SHIFT);
#endif
}
#endif
#if ! defined(__microblaze__) && ! defined(__riscv)
/*****************************************************************************/
/**
*
* @brief This API is used to provide infomation about core id of the
* CPU core from which it is executed.
*
* @return Core id of the core on which API is executed.
*
******************************************************************************/
u8 XGetCoreId(void)
{
UINTPTR CoreId;
#if (defined (__aarch64__) && ! defined (VERSAL_NET))
/* CortexA53 and CortexA72 */
CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK);
CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \
XREG_MPIDR_AFFINITY0_SHIFT);
#elif (defined (__aarch64__) && defined (VERSAL_NET))
/* CortexA78 */
CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK);
CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \
XREG_MPIDR_AFFINITY0_SHIFT);
#else
/* CortexA9, CortexR5 and CortexR52 */
#ifdef __GNUC__
CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_MULTI_PROC_AFFINITY, CoreId);
CoreId &= XREG_MPIDR_MASK;
#else
{
register u32 C15Reg __asm(XREG_CP15_MULTI_PROC_AFFINITY);
CoreId = C15Reg;
}
CoreId &= XREG_MPIDR_MASK;
#endif
CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \
XREG_MPIDR_AFFINITY0_SHIFT);
#endif
return (u8)CoreId;
}
#endif
#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52)
/*****************************************************************************/
/**
@ -165,11 +215,11 @@ u8 XGetClusterId(void)
#if defined (ARMR52)
ClusterId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK);
ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY1_MASK) >> \
XREG_MPIDR_AFFINITY1_SHIFT);
XREG_MPIDR_AFFINITY1_SHIFT);
#else
ClusterId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK);
ClusterId = ((ClusterId & XREG_MPIDR_AFFINITY2_MASK) >> \
XREG_MPIDR_AFFINITY2_SHIFT);
XREG_MPIDR_AFFINITY2_SHIFT);
#endif
return (u8)ClusterId;
@ -178,27 +228,38 @@ u8 XGetClusterId(void)
/*****************************************************************************/
/**
*
* @brief This API is used to provide infomation about core id of the
* CPU core from which it is executed.
* @brief This API returns boot status of core from which it is executed.
* 0th bit of CORE_X_PWRDWN/RPU_PCIL_X_PWRDWN register indicates boot type.
*
* @return Core id of the core on which API is executed.
* @return - 0 for cold boot
* - 1 for warm boot
*
******************************************************************************/
u8 XGetCoreId(void)
u8 XGetBootStatus(void)
{
u64 CoreId;
u32 Status;
UINTPTR Addr;
#if defined (ARMR52)
CoreId = (mfcp(XREG_CP15_MULTI_PROC_AFFINITY) & XREG_MPIDR_MASK);
CoreId = ((CoreId & XREG_MPIDR_AFFINITY0_MASK) >> \
XREG_MPIDR_AFFINITY0_SHIFT);
#if (__aarch64__)
u8 CpuNum;
CpuNum = XGetClusterId();
CpuNum *= XPS_NUM_OF_CORES_PER_CLUSTER;
CpuNum += XGetCoreId();
Addr = XPS_CORE_X_PWRDWN_BASEADDR + (CpuNum * XPS_CORE_X_PWRDWN_OFFSET);
Status = Xil_In32(Addr);
return (Status & XPS_CORE_X_PWRDWN_EN_MASK);
#else
CoreId = (mfcp(MPIDR_EL1) & XREG_MPIDR_MASK);
CoreId = ((CoreId & XREG_MPIDR_AFFINITY1_MASK) >> \
XREG_MPIDR_AFFINITY1_SHIFT);
Addr = (XPS_RPU_PCIL_CLUSTER_OFFSET * XGetClusterId()) + XPS_RPU_PCIL_A0_PWRDWN;
Addr += (XGetCoreId() * XPS_RPU_PCIL_CORE_OFFSET);
Status = Xil_In32(Addr);
return (Status & XPS_RPU_PCIL_X_PWRDWN_EN_MASK);
#endif
return (u8)CoreId;
}
#endif

41
bsp_z7/ps7_cortexa9_0/include/xplatform_info.h
View File

@ -36,6 +36,11 @@
* misra_c_2012_rule_10_4 violation.
* 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now
* they are supported only for VERSAL_NET APU and RPU.
* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be
* used to identify type of boot (cold/warm).
* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor
* 9.0 ml 09/14/23 Added U to numerical to fix MISRA-C violation for Rule
* 10.1 and 10.4
* </pre>
*
******************************************************************************/
@ -60,12 +65,12 @@ extern "C" {
#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
XPAR_PMC_TAP_VERSION_OFFSET)
XPAR_PMC_TAP_VERSION_OFFSET)
#else
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
XPAR_CSU_VER_OFFSET)
XPAR_CSU_VER_OFFSET)
#endif
#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
#define XPLAT_ZYNQ_ULTRA_MP 0x1
@ -84,11 +89,37 @@ extern "C" {
#define XPS_VERSION_INFO_SHIFT 0x8U
#define XPLAT_INFO_SHIFT 0x18U
#else
#define XPS_VERSION_INFO_MASK (0xF)
#define XPS_VERSION_INFO_MASK 0xFU
#define XPS_VERSION_INFO_SHIFT 0x0U
#define XPLAT_INFO_SHIFT 0xCU
#endif
#if defined (VERSAL_NET)
#if defined (ARMR52)
#define XPS_NUM_OF_CORES_PER_CLUSTER 2U
#define XPS_RPU_PCIL_A0_PWRDWN 0xEB4200C0U
/*
* Offset between RPU_PCIL_X_PWRDWN registers of consecutive
* CPU cores in given cluster
*/
#define XPS_RPU_PCIL_CORE_OFFSET 0x100U
/*
* Offset between RPU_PCIL_A0_PWRDWN registers of 2 clusters
*/
#define XPS_RPU_PCIL_CLUSTER_OFFSET 0x1000U
#define XPS_RPU_PCIL_X_PWRDWN_EN_MASK 1U
#else
#define XPS_NUM_OF_CORES_PER_CLUSTER 4U
#define XPS_CORE_X_PWRDWN_BASEADDR 0xECB10000U
/*
* Offset between CORE_X_PWRDWN registers of consecutive
* CPU cores
*/
#define XPS_CORE_X_PWRDWN_OFFSET 48U
#define XPS_CORE_X_PWRDWN_EN_MASK 1U
#endif
#endif
/**************************** Type Definitions *******************************/
/**
*@endcond
@ -97,6 +128,9 @@ extern "C" {
u32 XGetPlatform_Info(void);
#if ! defined(__microblaze__) && ! defined(__riscv)
u8 XGetCoreId(void);
#endif
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
u32 XGetPSVersion_Info(void);
@ -109,6 +143,7 @@ u32 XGet_Zynq_UltraMp_Platform_info(void);
#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52)
u8 XGetClusterId(void);
u8 XGetCoreId(void);
u8 XGetBootStatus(void);
#endif
/************************** Function Prototypes ******************************/

46
bsp_z7/ps7_cortexa9_0/include/xpm_init.h Normal file
View File

@ -0,0 +1,46 @@
/******************************************************************************
*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
*SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpm_init.h
* @addtogroup xpm_init xpm_init APIs
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.0 gm 14/06/23 Initial release.
* </pre>
******************************************************************************/
#ifndef XPM_INIT_H
#define XPM_INIT_H
/************************** Constant Definitions *****************************/
#if defined (XPM_SUPPORT)
#ifdef VERSAL_NET
#define MAX_NODE_COUNT 38
#elif defined(versal)
#define MAX_NODE_COUNT 33
#endif
/**************************** Type Definitions *******************************/
typedef struct {
UINTPTR BaseAddress;
UINTPTR NodeId;
UINTPTR ResetId;
} XpmNodeInfo;
/************************** Function Prototypes ******************************/
UINTPTR XpmGetNodeId(UINTPTR BaseAddress);
UINTPTR XpmGetResetId(UINTPTR BaseAddress);
#endif
#endif

188
bsp_z7/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -23,6 +23,7 @@
* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
* 8.0 mus 02/24/22 Added macro mfcpnotoken and mtcpnotoken.
* 8.1 asa 02/13/23 Create macros to read ESR, FAR and ELR registers.
* 9.1 ml 11/15/23 Fix compilation errors reported with -std=c2x compiler flag
* </pre>
*
******************************************************************************/
@ -56,9 +57,9 @@ extern "C" {
#if defined (__aarch64__)
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval = 0U; \
asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
@ -68,12 +69,10 @@ extern "C" {
#define cpsief() //__asm__ __volatile__("cpsie f\n")
#define cpsidf() //__asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) /*__asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)*/
)*/
#define mfgpr(rn) /*({u32 rval; \
__asm__ __volatile__(\
@ -81,7 +80,7 @@ extern "C" {
: "=r" (rval)\
);\
rval;\
})*/
})*/
/* memory synchronization operations */
@ -94,47 +93,45 @@ extern "C" {
/* Data Memory Barrier */
#define dmb() __asm__ __volatile__("dmb sy")
/* Memory Operations */
#define ldr(adr) ({u64 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#if (EL3 == 1)
#define mfelrel3() ({u64 rval = 0U; \
asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
rval;\
})
#define mfesrel3() ({u64 rval = 0U; \
asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\
rval;\
})
#define mffarel3() ({u64 rval = 0U; \
asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\
rval;\
})
#else
#define mfelrel1() ({u64 rval = 0U; \
asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\
rval;\
})
#define mfesrel1() ({u64 rval = 0U; \
asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\
rval;\
})
#define mffarel1() ({u64 rval = 0U; \
asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\
rval;\
})
__asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\
rval;\
})
#endif
@ -144,17 +141,17 @@ extern "C" {
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval = 0U; \
__asm__ __volatile__(\
"mrs %0, cpsr\n"\
: "=r" (rval)\
);\
rval;\
})
__asm__ __volatile__(\
"mrs %0, cpsr\n"\
: "=r" (rval)\
);\
rval;\
})
#define mtcpsr(v) __asm__ __volatile__(\
"msr cpsr,%0\n"\
: : "r" (v) : "cc" \
)
"msr cpsr,%0\n"\
: : "r" (v) : "cc" \
)
#define cpsiei() __asm__ __volatile__("cpsie i\n")
#define cpsidi() __asm__ __volatile__("cpsid i\n")
@ -162,20 +159,18 @@ extern "C" {
#define cpsief() __asm__ __volatile__("cpsie f\n")
#define cpsidf() __asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) __asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)
#define mfgpr(rn) ({u32 rval; \
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})
/* memory synchronization operations */
@ -188,44 +183,43 @@ extern "C" {
/* Data Memory Barrier */
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
/* Memory Operations */
#define ldr(adr) ({u32 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#endif
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
__asm__ __volatile__(\
"ldrb %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define strw(adr, val) __asm__ __volatile__(\
"str %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
"str %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
#define strb(adr, val) __asm__ __volatile__(\
"strb %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
"strb %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
/* Count leading zeroes (clz) */
#define clz(arg) ({u8 rval; \
__asm__ __volatile__(\
"clz %0,%1"\
: "=r" (rval) : "r" (arg)\
);\
rval;\
})
__asm__ __volatile__(\
"clz %0,%1"\
: "=r" (rval) : "r" (arg)\
);\
rval;\
})
#if defined (__aarch64__)
#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
@ -236,14 +230,14 @@ extern "C" {
#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
/* CP15 operations */
#define mfcp(reg) ({u64 rval = 0U;\
__asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
rval;\
})
__asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
rval;\
})
#define mfcpnotoken(reg) ({u64 rval = 0U;\
__asm__ __volatile__("mrs %0, " reg : "=r" (rval));\
rval;\
})
__asm__ __volatile__("mrs %0, " reg : "=r" (rval));\
rval;\
})
#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
#define mtcpnotoken(reg,val) __asm__ __volatile__("msr " reg ",%0" : : "r" (val))
@ -251,22 +245,22 @@ extern "C" {
#else
/* CP15 operations */
#define mtcp(rn, v) __asm__ __volatile__(\
"mcr " rn "\n"\
: : "r" (v)\
);
"mcr " rn "\n"\
: : "r" (v)\
);
#define mfcp(rn) ({u32 rval = 0U; \
__asm__ __volatile__(\
"mrc " rn "\n"\
: "=r" (rval)\
);\
rval;\
})
__asm__ __volatile__(\
"mrc " rn "\n"\
: "=r" (rval)\
);\
rval;\
})
#define mtcp2(rn, v) __asm__ __volatile__(\
"mcrr " rn "\n"\
: : "r" (v), "r" (0)\
);
"mcrr " rn "\n"\
: : "r" (v), "r" (0)\
);
#endif

59
bsp_z7/ps7_cortexa9_0/include/xqspips.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips.h
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
* @details
*
@ -270,6 +271,8 @@
* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
* data when RX buffer is not NULL.
* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow.
* 3.12 sb 02/20/24 Add missing parenthesis for macro expansions.
*
* </pre>
*
@ -478,16 +481,26 @@ extern "C" {
* requested if the status event indicates an error.
*/
typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
unsigned ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
#ifdef SDT
u32 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XQspiPs_Config;
/**
@ -571,7 +584,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET, (RegisterValue))
XQSPIPS_SICR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -589,7 +602,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_GetSlaveIdle(InstancePtr) \
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET)
XQSPIPS_SICR_OFFSET)
/****************************************************************************/
/**
@ -608,7 +621,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_TXWR_OFFSET, (RegisterValue))
XQSPIPS_TXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -625,7 +638,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetTXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
@ -644,7 +657,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_RXWR_OFFSET, (RegisterValue))
XQSPIPS_RXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -661,7 +674,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetRXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
@ -677,8 +690,8 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_Enable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
/**
@ -694,7 +707,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_Disable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
/****************************************************************************/
/**
@ -714,7 +727,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -731,35 +744,39 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
/************************** Function Prototypes ******************************/
/*
* Initialization function, implemented in xqspips_sinit.c
*/
#ifndef SDT
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
#else
XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Functions implemented in xqspips.c
*/
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
u32 EffectiveAddr);
u32 EffectiveAddr);
void XQspiPs_Reset(XQspiPs *InstancePtr);
void XQspiPs_Abort(XQspiPs *InstancePtr);
s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount);
u32 ByteCount);
s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount);
u8 *RecvBufPtr, u32 ByteCount);
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
u32 Address, unsigned ByteCount);
u32 Address, unsigned ByteCount);
int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
XQspiPs_StatusHandler FuncPtr);
XQspiPs_StatusHandler FuncPtr);
void XQspiPs_InterruptHandler(void *InstancePtr);
/*
@ -777,9 +794,9 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
u8 DelayAfter, u8 DelayInit);
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
u8 *DelayAfter, u8 *DelayInit);
#ifdef __cplusplus
}
#endif

25
bsp_z7/ps7_cortexa9_0/include/xqspips_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_hw.h
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* This header file contains the identifiers and basic HW access driver
@ -117,18 +118,18 @@ extern "C" {
/* Deselect the Slave select line and set the transfer size to 32 at reset */
#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
XQSPIPS_CR_SSCTRL_MASK | \
XQSPIPS_CR_DATA_SZ_MASK | \
XQSPIPS_CR_MSTREN_MASK | \
XQSPIPS_CR_SSFORCE_MASK | \
XQSPIPS_CR_HOLD_B_MASK
XQSPIPS_CR_SSCTRL_MASK | \
XQSPIPS_CR_DATA_SZ_MASK | \
XQSPIPS_CR_MSTREN_MASK | \
XQSPIPS_CR_SSFORCE_MASK | \
XQSPIPS_CR_HOLD_B_MASK
#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
XQSPIPS_CR_CPHA_MASK | \
XQSPIPS_CR_PRESC_MASK | \
XQSPIPS_CR_MANSTRTEN_MASK | \
XQSPIPS_CR_MANSTRT_MASK | \
XQSPIPS_CR_ENDIAN_MASK | \
XQSPIPS_CR_REF_CLK_MASK
XQSPIPS_CR_CPHA_MASK | \
XQSPIPS_CR_PRESC_MASK | \
XQSPIPS_CR_MANSTRTEN_MASK | \
XQSPIPS_CR_MANSTRT_MASK | \
XQSPIPS_CR_ENDIAN_MASK | \
XQSPIPS_CR_REF_CLK_MASK
/* @} */

7
bsp_z7/ps7_cortexa9_0/include/xreg_cortexa9.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -20,6 +21,7 @@
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 10/20/09 First release
* 9.0 mus 07/29/23 Added definitions for processor affinity register.
* </pre>
*
******************************************************************************/
@ -489,7 +491,10 @@ extern "C" {
#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
#endif
/* Affinity register bits */
#define XREG_MPIDR_MASK 0xFFFFFFFFU
#define XREG_MPIDR_AFFINITY0_MASK 0x3U
#define XREG_MPIDR_AFFINITY0_SHIFT 0x0U
/* MPE register definitions */
#define XREG_FPSID c0
#define XREG_FPSCR c1

239
bsp_z7/ps7_cortexa9_0/include/xscugic.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,56 +8,10 @@
/**
*
* @file xscugic.h
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
* @details
*
* The generic interrupt controller driver component.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 1 and 31 inclusive with
* default of 1 being the highest priority interrupt source. The priorities
* of the various sources can be dynamically altered as needed through
* hardware configuration.
*
* The generic interrupt controller supports the following
* features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - assigning desired priority to interrupt source if default is not
* acceptable.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xscugic_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table. The user should populate the
* vector table with handlers and callbacks at run-time using the
* XScuGic_Connect() and XScuGic_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an
* argument to be passed to the handler when an interrupt occurs. The
* user must use XScuGic_Connect() when the interrupt handler takes an
* argument other than the base address.
*
* <b>Nested Interrupts Processing</b>
*
* Nested interrupts are not supported by this driver.
*
* NOTE:
* The generic interrupt controller is not a part of the snoop control unit
* as indicated by the prefix "scu" in the name of the driver.
* It is an independent module in APU.
*
* <pre>
* MODIFICATION HISTORY:
@ -190,12 +144,14 @@
* executed, redistributor address will be stored in newly
* added member of XScuGic data structure "RedistBaseAddr".
* It fixes CR#1150432.
* 5.2 ml 03/02/23 Add description to fix Doxygen warnings.
* 5.2 adk 04/14/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_H /* prevent circular inclusions */
#define XSCUGIC_H /* by using protection macros */
#ifndef XSCUGIC_H /**< prevent circular inclusions */
#define XSCUGIC_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -212,13 +168,23 @@ extern "C" {
/************************** Constant Definitions *****************************/
/**
* @name EFUSE status Register information
* EFUSE Status Register
* @{
*/
#define EFUSE_STATUS_OFFSET 0x10
#define EFUSE_STATUS_CPU_MASK 0x80
#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
#define ARMA9
#define ARMA9 /**< ARMA9 macro to identify cortexA9 */
#endif
/**
* @name GICD_CTLR Register information
* GICD_CTLR Status Register
* @{
*/
#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
@ -245,8 +211,12 @@ extern "C" {
*/
typedef struct
{
Xil_InterruptHandler Handler;
void *CallBackRef;
Xil_InterruptHandler Handler; /**< Interrupt Handler */
void *CallBackRef; /**< CallBackRef is the callback reference passed in
by the upper layer when setting the Interrupt
handler for specific interrupt ID, and it will
passed back to Interrupt handler when it is
invoked. */
} XScuGic_VectorTableEntry;
/**
@ -254,9 +224,15 @@ typedef struct
*/
typedef struct
{
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 CpuBaseAddress; /**< CPU Interface Register base address */
u32 DistBaseAddress; /**< Distributor Register base address */
#else
char *Name; /**< Compatible string */
u32 DistBaseAddress; /**< Distributor Register base address */
u32 CpuBaseAddress; /**< CPU Interface Register base address */
#endif
XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
Vector table of interrupt handlers */
} XScuGic_Config;
@ -285,17 +261,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given CPU Interface register
* Writes the given CPU Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
@ -305,16 +280,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given CPU Interface register
* Reads the given CPU Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Rregister offset to be read.
*
* @return The 32-bit value of the register
* @return 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
@ -323,17 +297,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given Distributor Interface register
* Writes the given Distributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
@ -343,16 +316,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given Distributor Interface register
* Reads the given Distributor Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
* @return The 32-bit value of the register.
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
@ -362,17 +334,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given ReDistributor Interface register
* Writes the given ReDistributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
@ -381,16 +352,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given ReDistributor Interface register
* Reads the given ReDistributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
* @return 32-bit value of the register.
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
@ -399,17 +369,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given ReDistributor SGI PPI Interface register
* Writes the given ReDistributor SGI PPI Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
@ -419,16 +388,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given ReDistributor SGI PPI Interface register
* Reads the given ReDistributor SGI PPI Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
@ -443,9 +411,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#define XREG_ICC_SGI1R_EL1 "p15, 0, %0, %1, c12"
#define XREG_ICC_PMR_EL1 "p15, 0, %0, c4, c6, 0"
#define XREG_ICC_IAR0_EL1 "p15, 0, %0, c12, c8, 0"
#define XREG_ICC_IAR1_EL1 "p15, 0, %0, c12, c12, 0"
#define XREG_ICC_EOIR0_EL1 "p15, 0, %0, c12, c8, 1"
#define XREG_ICC_EOIR1_EL1 "p15, 0, %0, c12, c12, 1"
#define XREG_IMP_CBAR "p15, 1, %0, c15, c3, 0"
#define XREG_ICC_BPR0_EL1 "p15, 0, %0, c12, c8, 3"
#define XREG_ICC_BPR1_EL1 "p15, 0, %0, c12, c12, 3"
#define XREG_ICC_RPR_EL1 "p15, 0, %0, c12, c11, 3"
#else
#define XREG_ICC_SRE_EL1 "S3_0_C12_C12_5"
@ -463,13 +434,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function enables system register interface for GIC CPU Interface
* Enables system register interface for GIC CPU Interface.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (__aarch64__)
@ -480,13 +450,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function enables Grou0 interrupts
* Enable Grou0 interrupts.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -502,7 +471,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -518,13 +486,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function writes to ICC_SGI0R_EL1
* Writes to ICC_SGI0R_EL1.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -535,13 +502,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
* This function writes to ICC_SGI1R_EL1
* Writes to ICC_SGI1R_EL1.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -552,13 +518,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
* This function reads ICC_SGI1R_EL1 register
* Reads ICC_SGI1R_EL1 register.
*
* @param None
*
* @return Value of ICC_SGI1R_EL1 register
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -568,13 +533,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function sets interrupt priority filter
* Sets interrupt priority filter.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -584,17 +548,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function returns interrupt id of highest priority pending interrupt
* Returns interrupt ID of highest priority pending interrupt.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR0_EL1)
#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR1_EL1)
#elif EL3
#define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR0_EL1)
#else
@ -602,17 +565,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function acks the interrupt
* Acknowledges the interrupt.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR0_EL1,val)
#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR1_EL1,val)
#elif EL3
#define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR0_EL1,val)
#else
@ -627,7 +589,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) ((Int_Id%16) * 2U)
@ -660,12 +621,23 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
void XScuGic_Stop(XScuGic *InstancePtr);
void XScuGic_SetCpuID(u32 CpuCoreId);
u32 XScuGic_GetCpuID(void);
#ifndef SDT
u8 XScuGic_IsInitialized(u32 DeviceId);
#else
u8 XScuGic_IsInitialized(u32 BaseAddress);
#endif
#ifndef SDT
/*
* Initialization functions in xscugic_sinit.c
* Lookup configuration by using DeviceId
*/
XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
/*
* Lookup configuration by using BaseAddress
*/
XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress);
#else
XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddr);
#endif
/*
* Interrupt functions in xscugic_intr.c
@ -685,5 +657,6 @@ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
}
#endif
#endif /* end of protection macro */
#endif
/* end of protection macro */
/** @} */

134
bsp_z7/ps7_cortexa9_0/include/xscugic_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,11 +8,11 @@
/**
*
* @file xscugic_hw.h
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* This header file contains identifiers and HW access functions (or
* macros) that can be used to access the device. The user should refer to the
* The xscugic_hw.h header file contains identifiers and hardware access functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* The driver functions/APIs are defined in xscugic.h.
*
@ -69,13 +69,14 @@
* based address for specific CPU core. Also, added new macro
* XScuGic_ReadReg64 to read 64 bit value from specific address.
* 5.1 mus 02/15/23 Added support for VERSAL_NET APU and RPU GIC.
*
* 5.2 ml 03/02/23 Add description to fix Doxygen warnings.
* 5.2 mus 03/26/23 Fixed calculation for XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC.
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
#define XSCUGIC_HW_H /* by using protection macros */
#ifndef XSCUGIC_HW_H /**< prevent circular inclusions */
#define XSCUGIC_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -110,24 +111,31 @@ extern "C" {
* The maximum number of interrupts supported by the hardware.
*/
#ifdef PLATFORM_ZYNQ
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /**< Maximum number of
interrupt defined by
Zynq */
#elif defined (VERSAL_NET)
#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /* Maximum number of interrupt sources in VERSAL NET */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /**< Maximum number of
interrupt sources in
VERSAL NET */
#elif defined (versal)
#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U /**< Maximum number of
interrupt sources in
VERSAL */
#else
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /**< Maximum number of
interrupt defined by
Zynq Ultrascale Mp */
#endif
/*
* First Interrupt Id for SPI interrupts.
*/
#define XSCUGIC_SPI_INT_ID_START 0x20U
/*
* The maximum priority value that can be used in the GIC.
*/
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
#define XSCUGIC_SPI_INT_ID_START 0x20U /**< First Interrupt Id for
SPI interrupts. */
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U /**< The maximum priority value
that can be used in
the GIC. */
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /**< The Interrupt
priority mask value */
/** @name Distributor Interface Register Map
*
@ -338,7 +346,7 @@ extern "C" {
* There are up to 255 of these registers staring at location 0xC08.
* @{
*/
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< Interrupt configuration Mask */
/* @} */
/** @name PPI Status Register
@ -523,6 +531,7 @@ extern "C" {
#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
#define XSCUGIC_RDIST_TYPER_OFFSET 0x8U
@ -535,7 +544,7 @@ extern "C" {
/*
* GICR_IGROUPR register definitions
*/
#if (defined(ARMR52) || EL3)
#if EL3
#define XSCUGIC_DEFAULT_SECURITY 0x0U
#else
#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
@ -551,13 +560,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Configuration Register offset for an interrupt id.
* Reads the Interrupt Configuration Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
@ -566,13 +574,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Priority Register offset for an interrupt id.
* Reads the Interrupt Priority Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
@ -581,13 +588,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Routing Register offset for an interrupt id.
* Reads the Interrupt Routing Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
@ -596,13 +602,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the SPI Target Register offset for an interrupt id.
* Reads the SPI Target Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
* @return The 32-bit value of the offset.
*
* @note
*
*****************************************************************************/
#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
@ -610,13 +615,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the SPI Target Register offset for an interrupt id.
* Reads the SPI Target Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
@ -625,13 +629,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Re-distributor Interrupt configuration register offset
* Reads the Re-distributor Interrupt configuration register offset.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
@ -640,28 +643,26 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Re-distributor Interrupt Priority register offset
* Reads the Re-distributor Interrupt Priority register offset.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + ((InterruptID/4) * 4))
/****************************************************************************/
/**
*
* Read the Interrupt Clear-Enable Register offset for an interrupt ID
* Reads the Interrupt Clear-Enable Register offset for an interrupt ID.
*
* @param Register is the register offset for the clear/enable bank.
* @param InterruptID is the interrupt number.
* @param Register Register offset for the clear/enable bank.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
@ -670,16 +671,15 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the given Intc register.
* Reads the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be read
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg(BaseAddress, RegOffset) \
@ -688,16 +688,15 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the given Intc register.
* Reads the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be read
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be read.
*
* @return The 64-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg64(BaseAddress, RegOffset) \
@ -706,17 +705,16 @@ extern "C" {
/****************************************************************************/
/**
*
* Write the given Intc register.
* Writes the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be written
* @param Data 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \

62
bsp_z7/ps7_cortexa9_0/include/xscutimer.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer.h
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
* @details
*
@ -82,6 +83,7 @@
* 2.3 mus 08/31/20 Updated makefile to support parallel make and
* incremental builds, it would help to reduce compilation
* time.
* 2.5 dp 07/11/23 Add support for system device tree flow
* </pre>
*
******************************************************************************/
@ -106,7 +108,11 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef XIL_INTERRUPT
u32 IntrId;
@ -145,9 +151,9 @@ typedef struct {
******************************************************************************/
#define XScuTimer_IsExpired(InstancePtr) \
((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET) & \
XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
XSCUTIMER_ISR_EVENT_FLAG_MASK)
XSCUTIMER_ISR_OFFSET) & \
XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
XSCUTIMER_ISR_EVENT_FLAG_MASK)
/****************************************************************************/
/**
@ -165,8 +171,8 @@ typedef struct {
******************************************************************************/
#define XScuTimer_RestartTimer(InstancePtr) \
XScuTimer_LoadTimer((InstancePtr), \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET))
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET))
/****************************************************************************/
/**
@ -186,7 +192,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_LoadTimer(InstancePtr, Value) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET, (Value))
XSCUTIMER_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
@ -204,7 +210,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_GetCounterValue(InstancePtr) \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_COUNTER_OFFSET)
XSCUTIMER_COUNTER_OFFSET)
/****************************************************************************/
/**
@ -221,10 +227,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_EnableAutoReload(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
/****************************************************************************/
/**
@ -241,10 +247,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_DisableAutoReload(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
/****************************************************************************/
/**
@ -261,10 +267,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_EnableInterrupt(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
/****************************************************************************/
/**
@ -281,10 +287,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_DisableInterrupt(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
/*****************************************************************************/
/**
@ -301,7 +307,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_GetInterruptStatus(InstancePtr) \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET)
XSCUTIMER_ISR_OFFSET)
/*****************************************************************************/
/**
@ -318,14 +324,18 @@ typedef struct {
******************************************************************************/
#define XScuTimer_ClearInterruptStatus(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
/************************** Function Prototypes ******************************/
/*
* Lookup configuration in xscutimer_sinit.c
*/
#ifndef SDT
XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
#else
XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr);
#endif
/*
* Selftest function in xscutimer_selftest.c

3
bsp_z7/ps7_cortexa9_0/include/xscutimer_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer_hw.h
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* This file contains the hardware interface to the Timer.

49
bsp_z7/ps7_cortexa9_0/include/xscuwdt.h
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@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt.h
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
* @details
*
@ -106,6 +107,8 @@
* time.
* 2.3 sne 09/16/20 Fixed MISRA-C violations.
* 2.4 sne 02/04/21 Fixed Doxygen warnings.
* 2.5 asa 07/18/23 Added support for system device tree based workflow
* decoupling flow.
* </pre>
*
******************************************************************************/
@ -129,8 +132,18 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Base address of the device */
#else
char *Name; /**< Unique name of the device */
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XScuWdt_Config;
/**
@ -168,7 +181,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_IsWdtExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_RST_STS_OFFSET) & \
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
/****************************************************************************/
/**
@ -189,7 +202,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_IsTimerExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_ISR_OFFSET) & \
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
/****************************************************************************/
/**
@ -230,7 +243,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
******************************************************************************/
#define XScuWdt_LoadWdt(InstancePtr, Value) \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_LOAD_OFFSET, (Value))
XSCUWDT_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
@ -250,7 +263,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET, \
(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET) | \
XSCUWDT_CONTROL_OFFSET) | \
(XSCUWDT_CONTROL_WD_MODE_MASK)))
/****************************************************************************/
@ -271,14 +284,14 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
*
******************************************************************************/
#define XScuWdt_SetTimerMode(InstancePtr) \
{ \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE1); \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE2); \
}
{ \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE1); \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE2); \
}
/****************************************************************************/
/**
@ -332,14 +345,18 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_EnableAutoReload(InstancePtr) \
XScuWdt_SetControlReg((InstancePtr), \
(XScuWdt_GetControlReg(InstancePtr) | \
XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
/************************** Function Prototypes ******************************/
/*
* Lookup configuration in xscuwdt_sinit.c.
*/
#ifndef SDT
XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
#else
XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xscuwdt_selftest.c

5
bsp_z7/ps7_cortexa9_0/include/xscuwdt_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt_hw.h
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* This file contains the hardware interface to the Xilinx SCU private Watch Dog

111
bsp_z7/ps7_cortexa9_0/include/xsdps.h
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@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,75 +8,10 @@
/**
*
* @file xsdps.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
* @details
*
* This section explains the implementation of the XSdPs driver.
* See xsdps.h for a detailed description of the device and driver.
*
* This driver is used initialize read from and write to the SD card.
* Features such as switching bus width to 4-bit and switching to high speed,
* changing clock frequency, block size etc. are supported.
* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
* is done using 1-bit bus width and 400KHz clock frequency.
* SD commands are classified as broadcast and addressed. Commands can be
* those with response only (using only command line) or
* response + data (using command and data lines).
* Only one command can be sent at a time. During a data transfer however,
* when dsta lines are in use, certain commands (which use only the command
* line) can be sent, most often to obtain status.
* This driver does not support multi card slots at present.
*
* <b>Initialization & Configuration</b>
*
* This includes initialization on the host controller side to select
* clock frequency, bus power and default transfer related parameters.
* The default voltage is 3.3V.
* On the SD card side, the initialization and identification state diagram is
* implemented. This resets the card, gives it a unique address/ID and
* identifies key card related specifications.
*
* <b>Data transfer</b>
*
* The SD card is put in transfer state to read from or write to it.
* The default block size is 512 bytes and if supported,
* default bus width is 4-bit and bus speed is High speed.
* The read and write functions are implemented in polled mode using ADMA2.
*
* At any point, when key parameters such as block size or
* clock/speed or bus width are modified, this driver takes care of
* maintaining the same selection on host and card.
* All error bits in host controller are monitored by the driver and in the
* event one of them is set, driver will clear the interrupt status and
* communicate failure to the upper layer.
*
* <b>File system use</b>
*
* This driver can be used with xilffs library to read and write files to SD.
* (Please refer to procedure in diskio.c). The file system read/write example
* in polled mode can used for reference.
*
* There is no example for using SD driver without file system at present.
* However, the driver can be used without the file system. The glue layer
* in filesystem can be used as reference for the same. The block count
* passed to the read/write function in one call is limited by the ADMA2
* descriptor table and hence care will have to be taken to call read/write
* API's in a loop for large file sizes.
*
* Interrupt mode is not supported because it offers no improvement when used
* with file system.
*
* <b>eMMC support</b>
*
* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
* The features of eMMC supported by the driver will depend on those supported
* by the host controller. The current driver supports read/write on eMMC card
* using 4-bit and high speed mode currently.
*
* Features not supported include - card write protect, password setting,
* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
* 64-bit addressed ADMA2, erase/pre-erase commands.
*
* <pre>
* MODIFICATION HISTORY:
@ -161,6 +96,11 @@
* 4.1 sa 01/03/23 Report error if Transfer size is greater than 2MB.
* 4.1 sa 12/19/22 Enable eMMC HS400 mode for Versal Net.
* sa 01/25/23 Use instance structure to store DMA descriptor tables.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
* 4.2 ap 08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions
* 4.3 ap 10/11/23 Resolved compilation errors with Microblaze RISC-V
* 4.3 ap 11/29/23 Add support for Sanitize feature.
* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
*
* </pre>
*
@ -243,8 +183,12 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
#else
char *Name;
#endif
UINTPTR BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u32 CardDetect; /**< Card Detect */
u32 WriteProtect; /**< Write Protect */
@ -253,7 +197,7 @@ typedef struct {
u32 HasEMIO; /**< If SD is connected to EMIO */
u8 SlotType; /**< Slot type */
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
#if defined (XCLOCKING)
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clocks */
#endif
u32 ITapDly_SDR_Clk50; /**< Input Tap delay for HSD/SDR25 modes */
@ -262,6 +206,7 @@ typedef struct {
u32 OTapDly_DDR_Clk50; /**< Output Tap delay for DDR50 modes */
u32 OTapDly_SDR_Clk100; /**< Input Tap delay for SDR50 modes */
u32 OTapDly_SDR_Clk200; /**< Input Tap delay for SDR104/HS200 modes */
u32 OTapDly_DDR_Clk200; /**< Input Tap delay for HS400 modes */
} XSdPs_Config;
/**
@ -275,7 +220,8 @@ typedef struct {
#pragma data_alignment = 32
} XSdPs_Adma2Descriptor32;
#else
} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
}
__attribute__((__packed__))XSdPs_Adma2Descriptor32;
#endif
/**
@ -325,11 +271,11 @@ typedef struct {
u8 IsTuningDone; /**< Flag to indicate HS200 tuning complete */
#ifdef __ICCARM__
#pragma data_alignment = 32
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32];
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32];
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; /**< ADMA descriptor table 32 Bit */
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; /**< ADMA descriptor table 64 Bit */
#else
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32)));
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32)));
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 32 Bit */
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 64 Bit */
#endif
} XSdPs;
@ -355,10 +301,24 @@ typedef struct {
*/
#define ENABLE_HS400_MODE
/************************** Variable Definitions *****************************/
/**
* XSdPs Configuration Table
*/
#ifndef SDT
extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
#else
extern XSdPs_Config XSdPs_ConfigTable[];
#endif
/************************** Function Prototypes ******************************/
#ifndef SDT
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
#else
XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress);
#endif
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr);
UINTPTR EffectiveAddr);
s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
@ -380,6 +340,7 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr);
s32 XSdPs_Sanitize(XSdPs *InstancePtr);
#ifdef __cplusplus
}

11
bsp_z7/ps7_cortexa9_0/include/xsdps_core.h
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@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,10 +8,10 @@
/**
*
* @file xsdps_core.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* The xsdps_core.h header file contains the identifiers and basic HW access driver
* The xsdps_core.h header file contains the identifiers and basic hardware access driver
* functions (or macros) that can be used to access the device. Other driver
* functions are defined in xsdps.h.
*
@ -27,6 +27,7 @@
* mn 11/28/21 Fix MISRA-C violations.
* 4.0 sk 02/25/22 Add support for eMMC5.1.
* 4.1 sa 01/06/23 Include xil_util.h in this file.
* 4.2 ap 08/09/23 Add XSdPs_SetTapDelay APIs.
* </pre>
*
******************************************************************************/
@ -110,6 +111,10 @@ void XSdPs_ConfigInterrupt(XSdPs *InstancePtr);
s32 XSdPs_SendErase(XSdPs *InstancePtr);
s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr);
s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr);
void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr);
#ifdef VERSAL_NET
u32 XSdPs_Select_HS400(XSdPs *InstancePtr);
#endif

215
bsp_z7/ps7_cortexa9_0/include/xsdps_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +8,7 @@
/**
*
* @file xsdps_hw.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{{
*
* The xsdps_hw.h header file contains the identifiers and basic HW access driver
@ -45,6 +45,9 @@
* 4.0 sk 02/25/22 Add support for eMMC5.1.
* sk 04/07/22 Fix typo in 'XSDPS_MMC_1_BIT_BUS_ARG' macro definition.
* 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
* 4.3 ap 11/29/23 Add support for Sanitize feature.
* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
*
* </pre>
*
@ -63,8 +66,8 @@ extern "C" {
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "bspconfig.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
@ -76,8 +79,8 @@ extern "C" {
#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
Register */
#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
/**< SDMA System Address
Low Register */
/**< SDMA System Address
Low Register */
#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
High Register */
@ -87,7 +90,7 @@ extern "C" {
#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
/**< Argument1 Register */
/**< Argument1 Register */
#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
@ -714,16 +717,16 @@ extern "C" {
#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
(u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
/** @} */
@ -929,18 +932,24 @@ extern "C" {
#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
#define EXT_CSD_SANITIZE_START (0x1U)
#define EXT_CSD_PART_CONFIG_BYTE (179U)
#define EXT_CSD_SANIT_CONFIG_BYTE (165U)
#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)(0U) << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)(0U) << 8U))
#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
#define XSDPS_MMC_START_SANITIZE_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_SANIT_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_SANITIZE_START << 8U))
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
@ -952,14 +961,14 @@ extern "C" {
#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
/* DDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
/* SDR mode @1.2V I/O */
#define EXT_CSD_BUS_WIDTH_BYTE 183U
#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
@ -992,44 +1001,44 @@ extern "C" {
* SD/MMC Arguments for Bus Speed and Bus Width.
*/
#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
#define XSDPS_MMC_HS400_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS400 << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS400 << 8))
#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8))
#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
| ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
| ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
| ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
@ -1196,6 +1205,8 @@ extern "C" {
#define SD_ITAPCHGWIN 0x00000200U
#define SD_ITAPDLYENA 0x00000100U
#define SD_OTAPDLYENA 0x00000040U
#define SD_OTAPDLYSEL_SD104_B0 0x00000002U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000007U
#define SD_OTAPDLYSEL_HS200_B2 0x00000007U
#define SD_OTAPDLYSEL_HS400 0x00000004U
@ -1224,6 +1235,8 @@ extern "C" {
#define SD_ITAPCHGWIN 0x00000200U
#define SD_ITAPDLYENA 0x00000100U
#define SD_OTAPDLYENA 0x00000040U
#define SD_OTAPDLYSEL_SD104_B0 0x00000002U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
#define SD_ITAPDLYSEL_SD50 0x0000000EU
@ -1255,6 +1268,8 @@ extern "C" {
#define SD1_ITAPCHGWIN 0x02000000U
#define SD1_ITAPDLYENA 0x01000000U
#define SD1_OTAPDLYENA 0x00400000U
#define SD_OTAPDLYSEL_SD104_B0 0x00000003U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
#define SD_ITAPDLYSEL_SD50 0x00000014U
@ -1273,7 +1288,7 @@ extern "C" {
#endif
/** @} */
#ifdef __MICROBLAZE__
#if defined (__MICROBLAZE__) || defined (__riscv)
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
#endif
@ -1294,16 +1309,16 @@ extern "C" {
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param InstancePtr is the pointer to the sdps instance.
* @param RegOffset contains the offset from the 1st register of the
* @param InstancePtr Pointer to the sdps instance.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
@ -1311,36 +1326,36 @@ extern "C" {
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param InstancePtr is the pointer to the sdps instance.
* @param RegOffset contains the offset from the 1st register of the
* @param InstancePtr Pointer to the sdps instance.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
* u64 RegisterValue)
* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
* u64 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
(RegisterValue))
(RegisterValue))
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u32 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg(BaseAddress, RegOffset) \
@ -1348,18 +1363,18 @@ extern "C" {
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
@ -1367,25 +1382,25 @@ extern "C" {
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u16 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
static INLINE u16 XSdPs_ReadReg16(UINTPTR BaseAddress, u8 RegOffset)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg >>= ((RegOffset & 0x3)*8);
Reg >>= ((RegOffset & 0x3) * 8);
return (u16)Reg;
#else
return XSdPs_In16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset));
@ -1394,29 +1409,29 @@ static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u16 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
static INLINE void XSdPs_WriteReg16(UINTPTR BaseAddress, u8 RegOffset, u16 RegisterValue)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
Reg &= ~(0xFFFFU << ((RegOffset & 0x3) * 8));
Reg |= RegisterValue << ((RegOffset & 0x3) * 8);
XSdPs_Out32(BaseAddress, Reg);
#else
XSdPs_Out16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue));
@ -1425,25 +1440,25 @@ static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterV
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u8 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
static INLINE u8 XSdPs_ReadReg8(UINTPTR BaseAddress, u8 RegOffset)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg >>= ((RegOffset & 0x3)*8);
Reg >>= ((RegOffset & 0x3) * 8);
return (u8)Reg;
#else
return XSdPs_In8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset));
@ -1451,28 +1466,28 @@ static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
}
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
static INLINE void XSdPs_WriteReg8(UINTPTR BaseAddress, u8 RegOffset, u8 RegisterValue)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
Reg &= ~(0xFFU << ((RegOffset & 0x3) * 8));
Reg |= RegisterValue << ((RegOffset & 0x3) * 8);
XSdPs_Out32(BaseAddress, Reg);
#else
XSdPs_Out8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue));
@ -1480,19 +1495,19 @@ static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterVal
}
/***************************************************************************/
/**
* Macro to get present status register
* Macro to get present status register.
*
* @param BaseAddress contains the base address of the device.
* @param BaseAddress Contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
#define XSdPs_GetPresentStatusReg(BaseAddress) \
XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
/************************** Function Prototypes ******************************/

1
bsp_z7/ps7_cortexa9_0/include/xstatus.h
View File

@ -32,6 +32,7 @@ extern "C" {
#include "xil_types.h"
#include "xil_assert.h"
#include "bspconfig.h"
/************************** Constant Definitions *****************************/

20
bsp_z7/ps7_cortexa9_0/include/xttcps.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -149,6 +149,7 @@
* It fixes CR#1084697.
* 3.16 adk 04/19/22 Fix infinite loop in the examples by adding polled
* timeout loop.
* 3.18 adk 04/14/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -181,6 +182,7 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent);
#define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
#endif
#define XTTCPS_NUM_COUNTERS 3U
/** @name Configuration options
*
* Options for the device. Each of the options is bit field, so more than one
@ -203,11 +205,18 @@ typedef void (*XTtcPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent);
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID for device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address for device */
u32 InputClockHz; /**< Input clock frequency */
#ifdef XIL_INTERRUPT
u16 IntrId;
#if !defined(SDT) && defined(XIL_INTERRUPT)
u32 IntrId;
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */
#elif defined(SDT)
u32 IntrId[XTTCPS_NUM_COUNTERS]; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */
#endif
} XTtcPs_Config;
@ -487,7 +496,11 @@ typedef u32 XMatchRegValue;
/*
* Initialization functions in xttcps_sinit.c
*/
#ifndef SDT
XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
#else
XTtcPs_Config *XTtcPs_LookupConfig(u32 BaseAddress);
#endif
/*
* Required functions, in xttcps.c
@ -495,6 +508,7 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
u32 XTtcPs_Release(XTtcPs *InstancePtr);
void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);

21
bsp_z7/ps7_cortexa9_0/include/xuartps.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -149,6 +149,7 @@
* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
* 3.9 sd 02/06/20 Added clock support
* 3.12 gm 11/04/22 Added timeout support using Xil_WaitForEvent
* 3.13 adk 14/04/23 Added support for system device-tree flow.
*
* </pre>
*
@ -272,13 +273,23 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of device (IPIF) */
u32 InputClockHz;/**< Input clock frequency */
s32 ModemPinsConnected; /** Specifies whether modem pins are connected
* to MIO or FMIO */
#if defined (XCLOCKING)
u32 RefClk; /**< Input clock frequency */
#if defined (XCLOCKING) || defined(SDT)
u32 RefClk; /**< Input clock frequency */
#endif
#if defined(SDT)
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XUartPs_Config;
@ -444,7 +455,11 @@ typedef struct {
/************************** Function Prototypes *****************************/
/* Static lookup function implemented in xuartps_sinit.c */
#ifndef SDT
XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
#else
XUartPs_Config *XUartPs_LookupConfig(u32 BaseAddress);
#endif
/* Interface functions implemented in xuartps.c */
s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,

37
bsp_z7/ps7_cortexa9_0/include/xuartps_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -32,6 +32,8 @@
* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
* 3.6 ms 02/16/18 Updates flow control mode offset value in
* modem control register.
* 4.0 sd 02/02/24 Added macros for transmission FIFO empty check
* and transmission active state check
*
* </pre>
*
@ -48,6 +50,7 @@ extern "C" {
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
@ -408,6 +411,36 @@ extern "C" {
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
/****************************************************************************/
/**
* Check if transmission FIFO is empty
*
* @return TRUE if the TX FIFO is empty, FALSE if Tx FIFO is not empty
*
* @note C-Style signature:
* u32 XUartPs_IsTransmitEmpty(u32 BaseAddress)
*
******************************************************************************/
#define XUartPs_IsTransmitEmpty(BaseAddress) \
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
/****************************************************************************/
/**
* Check if transmission state machine is active
*
* @return TRUE if the TX state machine is active, FALSE if Tx state machine
* is In-active
*
* @note C-Style signature:
* u32 XUartPs_IsTransmitActive(u32 BaseAddress)
*
******************************************************************************/
#define XUartPs_IsTransmitActive(BaseAddress) \
((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
(u32)XUARTPS_SR_TACTIVE) == (u32)XUARTPS_SR_TACTIVE)
/************************** Function Prototypes ******************************/
void XUartPs_SendByte(u32 BaseAddress, u8 Data);
@ -416,6 +449,8 @@ u8 XUartPs_RecvByte(u32 BaseAddress);
void XUartPs_ResetHw(u32 BaseAddress);
void XUartPs_WaitTransmitDone(u32 BaseAddress);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus

223
bsp_z7/ps7_cortexa9_0/include/xusbps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xusbps.h
* @addtogroup usbps_v2_7
* @addtogroup usbps Overview
* @{
* @details
*
@ -163,6 +164,7 @@
* examples.
* 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
* calls.
* 2.8 pm 07/07/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -256,13 +258,13 @@ extern "C" {
#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
/* @} */
/*
* Device Speeds
*/
#define XUSBPS_SPEED_UNKNOWN 0U
#define XUSBPS_SPEED_LOW 1U
#define XUSBPS_SPEED_FULL 2U
#define XUSBPS_SPEED_HIGH 3U
/*
* Device Speeds
*/
#define XUSBPS_SPEED_UNKNOWN 0U
#define XUSBPS_SPEED_LOW 1U
#define XUSBPS_SPEED_FULL 2U
#define XUSBPS_SPEED_HIGH 3U
/**
* @name USB Default alternate setting
@ -272,15 +274,15 @@ extern "C" {
#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
/* @} */
/*
* Device States
*/
#define XUSBPS_STATE_ATTACHED 0U
#define XUSBPS_STATE_POWERED 1U
#define XUSBPS_STATE_DEFAULT 2U
#define XUSBPS_STATE_ADDRESS 3U
#define XUSBPS_STATE_CONFIGURED 4U
#define XUSBPS_STATE_SUSPENDED 5U
/*
* Device States
*/
#define XUSBPS_STATE_ATTACHED 0U
#define XUSBPS_STATE_POWERED 1U
#define XUSBPS_STATE_DEFAULT 2U
#define XUSBPS_STATE_ADDRESS 3U
#define XUSBPS_STATE_CONFIGURED 4U
#define XUSBPS_STATE_SUSPENDED 5U
/**
* @name Endpoint event types
@ -290,11 +292,11 @@ extern "C" {
* @{
*/
#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
/**< Setup data has been received on the endpoint. */
/**< Setup data has been received on the endpoint. */
#define XUSBPS_EP_EVENT_DATA_RX 0x02
/**< Data frame has been received on the endpoint. */
/**< Data frame has been received on the endpoint. */
#define XUSBPS_EP_EVENT_DATA_TX 0x03
/**< Data frame has been sent on the endpoint. */
/**< Data frame has been sent on the endpoint. */
/* @} */
@ -303,7 +305,7 @@ extern "C" {
* @{
*/
#define XUSBPS_MAX_PACKET_SIZE 1024
/**< Maximum value can be put into the queue head */
/**< Maximum value can be put into the queue head */
/* @} */
/**************************** Type Definitions *******************************/
@ -320,7 +322,7 @@ extern "C" {
* was registered.
*/
typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
u8 EpNum, u8 EventType, void *Data);
u8 EpNum, u8 EventType, void *Data);
/******************************************************************************
* This data type defines the callback function to be used for Endpoint
@ -369,24 +371,24 @@ typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
*/
typedef struct {
XUsbPs_dQH *dQH;
/**< Pointer to the Queue Head structure of the endpoint. */
/**< Pointer to the Queue Head structure of the endpoint. */
XUsbPs_dTD *dTDs;
/**< Pointer to the first dTD of the dTD list for this
* endpoint. */
/**< Pointer to the first dTD of the dTD list for this
* endpoint. */
XUsbPs_dTD *dTDCurr;
/**< Buffer to the currently processed descriptor. */
/**< Buffer to the currently processed descriptor. */
u8 *dTDBufs;
/**< Pointer to the first buffer of the buffer list for this
* endpoint. */
/**< Pointer to the first buffer of the buffer list for this
* endpoint. */
XUsbPs_EpHandlerFunc HandlerFunc;
XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
/**< Handler function for this endpoint. */
/**< Handler function for this endpoint. */
void *HandlerRef;
/**< User data reference for the handler. */
/**< User data reference for the handler. */
u32 RequestedBytes; /**< RequestedBytes for transfer */
u32 BytesTxed; /**< Actual Bytes transferred */
u8 *BufferPtr; /**< Buffer location */
@ -400,23 +402,23 @@ typedef struct {
*/
typedef struct {
XUsbPs_dQH *dQH;
/**< Pointer to the Queue Head structure of the endpoint. */
/**< Pointer to the Queue Head structure of the endpoint. */
XUsbPs_dTD *dTDs;
/**< List of pointers to the Transfer Descriptors of the
* endpoint. */
/**< List of pointers to the Transfer Descriptors of the
* endpoint. */
XUsbPs_dTD *dTDHead;
/**< Buffer to the next available descriptor in the list. */
/**< Buffer to the next available descriptor in the list. */
XUsbPs_dTD *dTDTail;
/**< Buffer to the last unsent descriptor in the list*/
/**< Buffer to the last unsent descriptor in the list*/
XUsbPs_EpHandlerFunc HandlerFunc;
XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
/**< Handler function for this endpoint. */
/**< Handler function for this endpoint. */
void *HandlerRef;
/**< User data reference for the handler. */
/**< User data reference for the handler. */
u32 RequestedBytes; /**< RequestedBytes for transfer */
u32 BytesTxed; /**< Actual Bytes transferred */
u8 *BufferPtr; /**< Buffer location */
@ -462,21 +464,21 @@ XUsbPs_SetupData;
*/
typedef struct {
u32 Type;
/**< Endpoint type:
- XUSBPS_EP_TYPE_CONTROL
- XUSBPS_EP_TYPE_ISOCHRONOUS
- XUSBPS_EP_TYPE_BULK
- XUSBPS_EP_TYPE_INTERRUPT */
/**< Endpoint type:
- XUSBPS_EP_TYPE_CONTROL
- XUSBPS_EP_TYPE_ISOCHRONOUS
- XUSBPS_EP_TYPE_BULK
- XUSBPS_EP_TYPE_INTERRUPT */
u32 NumBufs;
/**< Number of buffers to be handled by this endpoint. */
/**< Number of buffers to be handled by this endpoint. */
u32 BufSize;
/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
u16 MaxPacketSize;
/**< Maximum packet size for this endpoint. This number will
* define the maximum number of bytes sent on the wire per
* transaction. Range: 0..1024 */
/**< Maximum packet size for this endpoint. This number will
* define the maximum number of bytes sent on the wire per
* transaction. Range: 0..1024 */
} XUsbPs_EpSetup;
@ -502,7 +504,7 @@ typedef struct {
in the core. */
XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
/**< List of endpoint configurations. */
/**< List of endpoint configurations. */
u32 DMAMemPhys; /**< Physical base address of DMAable memory
@ -518,7 +520,7 @@ typedef struct {
* structure which is allocated by the caller.
*/
XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
/**< List of endpoint metadata structures. */
/**< List of endpoint metadata structures. */
u32 PhysAligned; /**< 64 byte aligned base address of the DMA
memory block. Will be computed and set by
@ -536,8 +538,17 @@ typedef struct {
* XUsbPs_ConfigureDevice() function call
*/
typedef struct {
#ifndef SDT
u16 DeviceID; /**< Unique ID of controller. */
#else
char *Name; /**< Unique Name of controller */
#endif
u32 BaseAddress; /**< Core register base address. */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type */
/** level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] */
#endif
} XUsbPs_Config;
typedef XUsbPs_Config Usb_Config;
@ -556,7 +567,7 @@ struct Usb_DevData {
*/
typedef struct {
XUsbPs_SetupData SetupData;
/**< Setup Packet buffer */
/**< Setup Packet buffer */
XUsbPs_Config Config; /**< Configuration structure */
int CurrentAltSetting; /**< Current alternative setting of interface */
@ -573,15 +584,15 @@ typedef struct {
* XUsbPs_ConfigureDevice() function call.
*/
XUsbPs_DeviceConfig DeviceConfig;
/**< Configuration for the DEVICE mode. */
/**< Configuration for the DEVICE mode. */
XUsbPs_IntrHandlerFunc HandlerFunc;
/**< Handler function for the controller. */
/**< Handler function for the controller. */
void *HandlerRef;
/**< User data reference for the handler. */
/**< User data reference for the handler. */
u32 HandlerMask;
/**< User interrupt mask. Defines which interrupts will cause
* the callback to be called. */
/**< User interrupt mask. Defines which interrupts will cause
* the callback to be called. */
struct Usb_DevData *AppData;
u8 IsConfigDone;
void *data_ptr; /* pointer for storing applications data */
@ -655,7 +666,7 @@ typedef struct {
******************************************************************************/
#define XUsbPs_ForceFS(InstancePtr) \
XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
XUSBPS_PORTSCR_PFSC_MASK)
XUSBPS_PORTSCR_PFSC_MASK)
/*****************************************************************************/
@ -671,14 +682,14 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_StartTimer0(InstancePtr, Interval) \
{ \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
XUSBPS_TIMER_RUN_MASK | \
XUSBPS_TIMER_RESET_MASK | \
XUSBPS_TIMER_REPEAT_MASK); \
} \
{ \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
XUSBPS_TIMER_RUN_MASK | \
XUSBPS_TIMER_RESET_MASK | \
XUSBPS_TIMER_REPEAT_MASK); \
} \
/*****************************************************************************/
@ -693,7 +704,7 @@ typedef struct {
******************************************************************************/
#define XUsbPs_StopTimer0(InstancePtr) \
XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
XUSBPS_TIMER_RUN_MASK)
XUSBPS_TIMER_RUN_MASK)
/*****************************************************************************/
@ -708,8 +719,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_ReadTimer0(InstancePtr) \
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_TIMER0_CTL_OFFSET) & \
XUSBPS_TIMER_COUNTER_MASK
XUSBPS_TIMER0_CTL_OFFSET) & \
XUSBPS_TIMER_COUNTER_MASK
/*****************************************************************************/
@ -724,7 +735,7 @@ typedef struct {
******************************************************************************/
#define XUsbPs_RemoteWakeup(InstancePtr) \
XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
XUSBPS_PORTSCR_FPR_MASK)
XUSBPS_PORTSCR_FPR_MASK)
/******************************************************************************
@ -749,8 +760,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
/*****************************************************************************/
@ -770,8 +781,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
/*****************************************************************************/
@ -792,8 +803,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
/*****************************************************************************/
@ -813,8 +824,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
/*****************************************************************************/
@ -834,8 +845,8 @@ typedef struct {
******************************************************************************/
#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
/*****************************************************************************/
/**
@ -849,7 +860,7 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
/*****************************************************************************/
@ -865,7 +876,7 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
/*****************************************************************************/
@ -914,7 +925,7 @@ typedef struct {
******************************************************************************/
#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
@ -940,8 +951,8 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET, (Threshold))\
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET, (Threshold))\
/*****************************************************************************/
@ -955,8 +966,8 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_SetSetupTripwire(InstancePtr) \
XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
/*****************************************************************************/
@ -970,8 +981,8 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_ClrSetupTripwire(InstancePtr) \
XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
XUSBPS_CMD_SUTW_MASK)
/*****************************************************************************/
@ -989,9 +1000,9 @@ typedef struct {
*
******************************************************************************/
#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET) & \
XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XUSBPS_CMD_OFFSET) & \
XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
/******************************************************************************
@ -1015,8 +1026,8 @@ typedef struct {
*****************************************************************************/
#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) | (Bits));
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) | (Bits));
/****************************************************************************/
@ -1037,8 +1048,8 @@ typedef struct {
*****************************************************************************/
#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) & ~(Bits));
XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
RegOffset) & ~(Bits));
/************************** Function Prototypes ******************************/
@ -1049,10 +1060,10 @@ typedef struct {
* Implemented in file xusbps.c
*/
int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
const XUsbPs_DeviceConfig *CfgPtr);
const XUsbPs_DeviceConfig *CfgPtr);
/**
* Common functions used for DEVICE/HOST mode.
@ -1086,23 +1097,23 @@ int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
const u8 *BufferPtr, u32 BufferLen);
int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
const u8 *BufferPtr, u32 BufferLen);
const u8 *BufferPtr, u32 BufferLen);
int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
void XUsbPs_EpBufferRelease(u32 Handle);
int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
XUsbPs_EpHandlerFunc CallBackFunc,
void *CallBackRef);
s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
XUsbPs_EpIsoHandlerFunc CallBackFunc);
XUsbPs_EpIsoHandlerFunc CallBackFunc);
int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
XUsbPs_SetupData *SetupDataPtr);
XUsbPs_SetupData *SetupDataPtr);
int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
int EpNum, unsigned short NewDirection, int DirectionChanged);
int EpNum, unsigned short NewDirection, int DirectionChanged);
/*
* Interrupt handling functions
@ -1112,17 +1123,21 @@ int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
void XUsbPs_IntrHandler(void *InstancePtr);
int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
XUsbPs_IntrHandlerFunc CallBackFunc,
void *CallBackRef, u32 Mask);
XUsbPs_IntrHandlerFunc CallBackFunc,
void *CallBackRef, u32 Mask);
void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
u8 *BufferPtr, u32 BufferLen);
u8 *BufferPtr, u32 BufferLen);
/*
* Helper functions for static configuration.
* Implemented in xusbps_sinit.c
*/
#ifndef SDT
XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
#else
XUsbPs_Config *XUsbPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}

95
bsp_z7/ps7_cortexa9_0/include/xusbps_endpoint.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xusbps_endpoint.h
* @addtogroup usbps_v2_7
* @addtogroup usbps Overview
* @{
*
* This is an internal file containung the definitions for endpoints. It is
@ -67,9 +68,9 @@ extern "C" {
* @{
*/
#define XUSBPS_dTDNLP_T_MASK 0x00000001
/**< USB dTD Next Link Pointer Terminate Bit */
/**< USB dTD Next Link Pointer Terminate Bit */
#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
/**< USB dTD Next Link Pointer Address [31:5] */
/**< USB dTD Next Link Pointer Address [31:5] */
/* @} */
@ -108,16 +109,16 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDInvalidateCache(dTDPtr) \
Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
#define XUsbPs_dTDFlushCache(dTDPtr) \
Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
#define XUsbPs_dQHInvalidateCache(dQHPtr) \
Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
#define XUsbPs_dQHFlushCache(dQHPtr) \
Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
/*****************************************************************************/
/**
@ -132,9 +133,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
/*****************************************************************************/
@ -151,8 +152,8 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDGetNLP(dTDPtr) \
(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
& XUSBPS_dTDNLP_ADDR_MASK))
(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
& XUSBPS_dTDNLP_ADDR_MASK))
/*****************************************************************************/
@ -168,10 +169,10 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
~XUSBPS_dTDNLP_ADDR_MASK) | \
((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
~XUSBPS_dTDNLP_ADDR_MASK) | \
((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
/*****************************************************************************/
@ -188,8 +189,8 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDGetTransferLen(dTDPtr) \
(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
/*****************************************************************************/
@ -205,9 +206,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetIOC(dTDPtr) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
XUSBPS_dTDTOKEN_IOC_MASK)
XUSBPS_dTDTOKEN_IOC_MASK)
/*****************************************************************************/
@ -222,9 +223,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetTerminate(dTDPtr) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
XUSBPS_dTDNLP_T_MASK)
XUSBPS_dTDNLP_T_MASK)
/*****************************************************************************/
@ -239,9 +240,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDClrTerminate(dTDPtr) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
~XUSBPS_dTDNLP_T_MASK)
~XUSBPS_dTDNLP_T_MASK)
/*****************************************************************************/
@ -260,8 +261,8 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDIsActive(dTDPtr) \
((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
/*****************************************************************************/
@ -276,9 +277,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetActive(dTDPtr) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
XUSBPS_dTDTOKEN_ACTIVE_MASK)
XUSBPS_dTDTOKEN_ACTIVE_MASK)
/*****************************************************************************/
/**
@ -293,9 +294,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dTDSetMultO(dTDPtr, val) \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
(~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
(~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
/*****************************************************************************/
@ -326,7 +327,7 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
/******************************************************************************/
@ -368,17 +369,17 @@ extern "C" {
* @{
*/
#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
/**< USB dQH Interrupt on Setup Bit */
/**< USB dQH Interrupt on Setup Bit */
#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
/**< USB dQH Maximum Packet Length
* Field [10:0] */
/**< USB dQH Maximum Packet Length
* Field [10:0] */
#define XUSBPS_dQHCFG_MPL_SHIFT 16
#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
/**< USB dQH Zero Length Termination
* Select Bit */
/**< USB dQH Zero Length Termination
* Select Bit */
#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
/* USB dQH Number of Transactions Field
* [1:0] */
/* USB dQH Number of Transactions Field
* [1:0] */
#define XUSBPS_dQHCFG_MULT_SHIFT 30
/* @} */
@ -396,9 +397,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
/*****************************************************************************/
/**
@ -412,9 +413,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dQHSetIOS(dQHPtr) \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
XUSBPS_dQHCFG_IOS_MASK)
XUSBPS_dQHCFG_IOS_MASK)
/*****************************************************************************/
/**
@ -428,9 +429,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dQHClrIOS(dQHPtr) \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_IOS_MASK)
~XUSBPS_dQHCFG_IOS_MASK)
/*****************************************************************************/
/**
@ -445,9 +446,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dQHEnableZLT(dQHPtr) \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
~XUSBPS_dQHCFG_ZLT_MASK)
~XUSBPS_dQHCFG_ZLT_MASK)
/*****************************************************************************/
@ -463,9 +464,9 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_dQHDisableZLT(dQHPtr) \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
XUSBPS_dQHCFG_ZLT_MASK)
XUSBPS_dQHCFG_ZLT_MASK)
/*****************************************************************************/
/**
@ -495,7 +496,7 @@ extern "C" {
*
******************************************************************************/
#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))

91
bsp_z7/ps7_cortexa9_0/include/xusbps_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xusbps_hw.h
* @addtogroup usbps_v2_7
* @addtogroup usbps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or
@ -22,7 +23,7 @@
* 1.00a wgr 10/10/10 First release
* 1.04a nm 10/23/12 Fixed CR# 679106.
* 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
* 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
* 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
* 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
* </pre>
*
@ -110,7 +111,7 @@ extern "C" {
/* NOTE: The Port Control / Status Register index is 1-based. */
#define XUSBPS_PORTSCRn_OFFSET(n) \
(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
@ -133,7 +134,7 @@ extern "C" {
#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
* registers */
#define XUSBPS_EPCRn_OFFSET(n) \
(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
#define XUSBPS_EPFLUSH_RX_SHIFT 0
#define XUSBPS_EPFLUSH_TX_SHIFT 16
@ -251,24 +252,24 @@ extern "C" {
#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
XUSBPS_IXR_UE_MASK | \
XUSBPS_IXR_PC_MASK | \
XUSBPS_IXR_FRE_MASK | \
XUSBPS_IXR_AA_MASK | \
XUSBPS_IXR_UR_MASK | \
XUSBPS_IXR_SR_MASK | \
XUSBPS_IXR_SLE_MASK | \
XUSBPS_IXR_ULPI_MASK | \
XUSBPS_IXR_HCH_MASK | \
XUSBPS_IXR_RCL_MASK | \
XUSBPS_IXR_PS_MASK | \
XUSBPS_IXR_AS_MASK | \
XUSBPS_IXR_NAK_MASK | \
XUSBPS_IXR_UA_MASK | \
XUSBPS_IXR_UP_MASK | \
XUSBPS_IXR_TI0_MASK | \
XUSBPS_IXR_TI1_MASK)
/**< Mask for ALL IRQ types */
XUSBPS_IXR_UE_MASK | \
XUSBPS_IXR_PC_MASK | \
XUSBPS_IXR_FRE_MASK | \
XUSBPS_IXR_AA_MASK | \
XUSBPS_IXR_UR_MASK | \
XUSBPS_IXR_SR_MASK | \
XUSBPS_IXR_SLE_MASK | \
XUSBPS_IXR_ULPI_MASK | \
XUSBPS_IXR_HCH_MASK | \
XUSBPS_IXR_RCL_MASK | \
XUSBPS_IXR_PS_MASK | \
XUSBPS_IXR_AS_MASK | \
XUSBPS_IXR_NAK_MASK | \
XUSBPS_IXR_UA_MASK | \
XUSBPS_IXR_UP_MASK | \
XUSBPS_IXR_TI0_MASK | \
XUSBPS_IXR_TI1_MASK)
/**< Mask for ALL IRQ types */
/* @} */
@ -291,13 +292,13 @@ extern "C" {
* @{
*/
#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
/**< Device Addr Auto Advance */
/**< Device Addr Auto Advance */
#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
/**< Device Address */
/**< Device Address */
#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
/**< Address shift */
/**< Address shift */
#define XUSBPS_DEVICEADDR_MAX 127
/**< Biggest allowed address */
/**< Biggest allowed address */
/* @} */
/** @name USB TT Control Register (TTCTRL) bit positions.
@ -319,11 +320,11 @@ extern "C" {
* @{
*/
#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
/**< Scheduler Overhead */
/**< Scheduler Overhead */
#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
/**< Scheduler Health Cntr */
/**< Scheduler Health Cntr */
#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
/**< FIFO Burst Threshold */
/**< FIFO Burst Threshold */
/* @} */
@ -411,22 +412,22 @@ extern "C" {
* Enable Bit */
#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
XUSBPS_OTGSC_AVVIS_MASK | \
XUSBPS_OTGSC_ASVIS_MASK | \
XUSBPS_OTGSC_BSVIS_MASK | \
XUSBPS_OTGSC_BSEIS_MASK | \
XUSBPS_OTGSC_1MSS_MASK | \
XUSBPS_OTGSC_DPIS_MASK)
/** Mask for All IRQ status masks */
XUSBPS_OTGSC_AVVIS_MASK | \
XUSBPS_OTGSC_ASVIS_MASK | \
XUSBPS_OTGSC_BSVIS_MASK | \
XUSBPS_OTGSC_BSEIS_MASK | \
XUSBPS_OTGSC_1MSS_MASK | \
XUSBPS_OTGSC_DPIS_MASK)
/** Mask for All IRQ status masks */
#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
XUSBPS_OTGSC_AVVIE_MASK | \
XUSBPS_OTGSC_ASVIE_MASK | \
XUSBPS_OTGSC_BSVIE_MASK | \
XUSBPS_OTGSC_BSEE_IEB_MASK | \
XUSBPS_OTGSC_1MSE_MASK | \
XUSBPS_OTGSC_DPIE_MASK)
/** Mask for All IRQ Enable masks */
XUSBPS_OTGSC_AVVIE_MASK | \
XUSBPS_OTGSC_ASVIE_MASK | \
XUSBPS_OTGSC_BSVIE_MASK | \
XUSBPS_OTGSC_BSEE_IEB_MASK | \
XUSBPS_OTGSC_1MSE_MASK | \
XUSBPS_OTGSC_DPIE_MASK)
/** Mask for All IRQ Enable masks */
/* @} */
@ -468,7 +469,7 @@ extern "C" {
*
*****************************************************************************/
#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32(BaseAddress + (RegOffset))
Xil_In32(BaseAddress + (RegOffset))
/****************************************************************************/
@ -487,7 +488,7 @@ extern "C" {
*
*****************************************************************************/
#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32(BaseAddress + (RegOffset), (Data))
Xil_Out32(BaseAddress + (RegOffset), (Data))
/************************** Function Prototypes ******************************/

3
bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xcpu_cortexa9.h
* @addtogroup cpu_cortexa9_v2_11
* @addtogroup cpu_cortexa9 Overview
* @{
* @details
*

123
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the implementation of the interface functions for XDcfg
@ -55,7 +56,7 @@
* XDCFG_INT_STS_OFFSET) &
* XDCFG_IXR_D_P_DONE_MASK) !=
* XDCFG_IXR_D_P_DONE_MASK);
*
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
*
* </pre>
*
@ -106,7 +107,7 @@
*
******************************************************************************/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
@ -124,7 +125,9 @@ int XDcfg_CfgInitialize(XDcfg *InstancePtr,
/*
* Copy configuration into instance.
*/
#ifndef SDT
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
#endif
/*
* Save the base address pointer such that the registers of the block
@ -172,10 +175,10 @@ void XDcfg_EnablePCAP(XDcfg *InstancePtr)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
}
@ -203,10 +206,10 @@ void XDcfg_DisablePCAP(XDcfg *InstancePtr)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
}
@ -235,10 +238,10 @@ void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg | Mask));
(CtrlReg | Mask));
}
@ -266,10 +269,10 @@ void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg & ~Mask));
(CtrlReg & ~Mask));
}
@ -488,7 +491,7 @@ void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
Data);
Data);
}
@ -545,10 +548,10 @@ void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
(RegData | Mask));
(RegData | Mask));
}
/****************************************************************************/
@ -601,10 +604,10 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
/* Read the PCAP status register for DMA status */
RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_STATUS_OFFSET);
XDCFG_STATUS_OFFSET);
if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
XDCFG_STATUS_DMA_CMD_Q_F_MASK){
XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
return XST_SUCCESS;
}
@ -637,24 +640,24 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
*
****************************************************************************/
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength)
u32 SrcWordLength, u32 DestWordLength)
{
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_SRC_ADDR_OFFSET,
SourcePtr);
XDCFG_DMA_SRC_ADDR_OFFSET,
SourcePtr);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_DEST_ADDR_OFFSET,
DestPtr);
XDCFG_DMA_DEST_ADDR_OFFSET,
DestPtr);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_SRC_LEN_OFFSET,
SrcWordLength);
XDCFG_DMA_SRC_LEN_OFFSET,
SrcWordLength);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_DEST_LEN_OFFSET,
DestWordLength);
XDCFG_DMA_DEST_LEN_OFFSET,
DestWordLength);
}
/******************************************************************************/
@ -680,8 +683,8 @@ void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
*
****************************************************************************/
static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
u32 SrcWordLength, u32 DestPtr,
u32 DestWordLength)
u32 SrcWordLength, u32 DestPtr,
u32 DestWordLength)
{
u32 IntrReg;
@ -689,7 +692,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
* Send READ Frame command to FPGA
*/
XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
SrcWordLength, 0);
SrcWordLength, 0);
/*
* Store the enabled interrupts to enable before the actual read
@ -701,10 +704,10 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
/*
* Wait till you get the DMA done for the read command sent
*/
while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET) &
XDCFG_IXR_D_P_DONE_MASK) !=
XDCFG_IXR_D_P_DONE_MASK);
while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET) &
XDCFG_IXR_D_P_DONE_MASK) !=
XDCFG_IXR_D_P_DONE_MASK);
/*
* Enable the previously stored Interrupts .
*/
@ -714,7 +717,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
* Initiate the DMA write command.
*/
XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
0, DestWordLength);
0, DestWordLength);
return XST_SUCCESS;
}
@ -762,9 +765,9 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
*
*****************************************************************************/
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType)
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType)
{
u32 CtrlReg;
@ -781,7 +784,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* Check whether the fabric is in initialized state
*/
if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
& XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
& XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
/*
* We don't need to check PCFG_INIT to be high for
* non-encrypted loopback transfers.
@ -792,7 +795,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
}
if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
(TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
(TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
/* Check for valid source pointer and length */
if ((!SourcePtr) || (SrcWordLength == 0)) {
@ -803,8 +806,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
/*
@ -815,8 +818,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
}
if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
@ -828,11 +831,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* operation.
*/
XDcfg_SetControlRegister(InstancePtr,
XDCFG_CTRL_PCAP_RATE_EN_MASK);
XDCFG_CTRL_PCAP_RATE_EN_MASK);
}
XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
(u32)DestPtr, SrcWordLength, DestWordLength);
(u32)DestPtr, SrcWordLength, DestWordLength);
}
@ -847,8 +850,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
/*
* For PCAP readback of FPGA configuration register or memory,
@ -860,26 +863,26 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* transfer to support this mode of operation.
*/
return XDcfg_PcapReadback(InstancePtr,
(u32)SourcePtr, SrcWordLength,
(u32)DestPtr, DestWordLength);
(u32)SourcePtr, SrcWordLength,
(u32)DestPtr, DestWordLength);
}
if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
(TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
(TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
if ((!SourcePtr) || (SrcWordLength == 0) ||
(!DestPtr) || (DestWordLength == 0)) {
(!DestPtr) || (DestWordLength == 0)) {
return XST_INVALID_PARAM;
}
if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
/* Enable internal PCAP loopback */
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg |
XDCFG_MCTRL_PCAP_LPBK_MASK));
XDCFG_MCTRL_OFFSET, (CtrlReg |
XDCFG_MCTRL_PCAP_LPBK_MASK));
/*
* Clear QUARTER_PCAP_RATE_EN bit
@ -889,8 +892,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
}
if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
@ -898,8 +901,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
/*
* Set the QUARTER_PCAP_RATE_EN bit
@ -907,11 +910,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* cycles, this is required for encrypted data.
*/
XDcfg_SetControlRegister(InstancePtr,
XDCFG_CTRL_PCAP_RATE_EN_MASK);
XDCFG_CTRL_PCAP_RATE_EN_MASK);
}
XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
(u32)DestPtr, SrcWordLength, DestWordLength);
(u32)DestPtr, SrcWordLength, DestWordLength);
}
return XST_SUCCESS;

48
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
* @details
*
@ -133,6 +134,7 @@
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of devcfg in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -178,8 +180,18 @@ typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDcfg_Config;
/**
@ -210,7 +222,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_Unlock(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
@ -230,8 +242,8 @@ typedef struct {
#define XDcfg_GetPsVersion(InstancePtr) \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_OFFSET)) & \
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
@ -250,7 +262,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_ReadMultiBootConfig(InstancePtr) \
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MULTIBOOT_ADDR_OFFSET)
XDCFG_MULTIBOOT_ADDR_OFFSET)
/****************************************************************************/
@ -269,8 +281,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectIcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
/****************************************************************************/
/**
@ -288,8 +300,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectPcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
@ -298,7 +310,11 @@ typedef struct {
/*
* Lookup configuration in xdevcfg_sinit.c.
*/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xdevcfg_selftest.c
@ -309,7 +325,7 @@ int XDcfg_SelfTest(XDcfg *InstancePtr);
* Interface functions in xdevcfg.c
*/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
void XDcfg_EnablePCAP(XDcfg *InstancePtr);
@ -344,12 +360,12 @@ u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength);
u32 SrcWordLength, u32 DestWordLength);
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
/*
* Interrupt related function prototypes implemented in xdevcfg_intr.c
@ -367,7 +383,7 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
void XDcfg_InterruptHandler(XDcfg *InstancePtr);
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef);
void *CallBackRef);
#ifdef __cplusplus
}

5
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_g.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains a table that specifies the configuration of the Device

10
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_hw.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the implementation of the interface reset functionality
@ -17,6 +18,7 @@
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 2.04a kpc 10/07/13 First release
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -59,7 +61,7 @@ void XDcfg_ResetHw(u32 BaseAddr)
/* Mask the interrupts */
XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
XDCFG_IXR_ALL_MASK);
XDCFG_IXR_ALL_MASK);
/* Clear the interuupt status */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
@ -77,7 +79,7 @@ void XDcfg_ResetHw(u32 BaseAddr)
XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
/*Reset the configuration register to reset value */
XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
XDCFG_CONFIG_RESET_VALUE);
XDCFG_CONFIG_RESET_VALUE);
/*Disable the PCAP rate enable bit */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;

28
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_hw.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the hardware interface to the Device Config Interface.
@ -26,6 +27,7 @@
* version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -210,14 +212,14 @@ extern "C" {
* of Init Signal
*/
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
@ -266,9 +268,9 @@ extern "C" {
* Status
*/
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
/**< BBRAM key
* disable
*/
/**< BBRAM key
* disable
*/
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
* Enable Status
*/

32
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_intr.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* Contains the implementation of interrupt related functions of the XDcfg
@ -22,6 +23,7 @@
* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
* set the mask instead of oring it with the
* value read from the interrupt status register
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -70,11 +72,11 @@ void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
* Enable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
XDCFG_INT_MASK_OFFSET);
RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
XDCFG_INT_MASK_OFFSET,
RegValue);
}
@ -108,11 +110,11 @@ void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
* Disable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
XDCFG_INT_MASK_OFFSET);
RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
XDCFG_INT_MASK_OFFSET,
RegValue);
}
/****************************************************************************/
/**
@ -170,7 +172,7 @@ u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
* Return the value read from the Interrupt Status register.
*/
return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
XDCFG_INT_STS_OFFSET);
}
/****************************************************************************/
@ -199,8 +201,8 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET,
Mask);
XDCFG_INT_STS_OFFSET,
Mask);
}
@ -232,7 +234,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
* Read the Interrupt status register.
*/
IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
XDCFG_INT_STS_OFFSET);
/*
* Write the status back to clear the interrupts so that no
@ -240,13 +242,13 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
* This also does the DMA acknowledgment automatically.
*/
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET, IntrStatusReg);
XDCFG_INT_STS_OFFSET, IntrStatusReg);
/*
* Signal application that there are events to handle.
*/
InstancePtr->StatusHandler(InstancePtr->CallBackRef,
IntrStatusReg);
IntrStatusReg);
}
@ -268,7 +270,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
*
*****************************************************************************/
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef)
void *CallBackRef)
{
/*
* Asserts validate the input arguments

5
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_selftest.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* Contains diagnostic self-test functions for the XDcfg driver.

27
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_sinit.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains method for static initialization (compile-time) of the
@ -20,6 +21,7 @@
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 3.5 ms 08/07/17 Fixed compilation warnings.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -27,7 +29,9 @@
/***************************** Include Files *********************************/
#include "xdevcfg.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -50,6 +54,7 @@
* @note None.
*
******************************************************************************/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
{
extern XDcfg_Config XDcfg_ConfigTable[];
@ -65,4 +70,22 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
return (CfgPtr);
}
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress)
{
extern XDcfg_Config XDcfg_ConfigTable[];
XDcfg_Config *CfgPtr = NULL;
u32 Index;
for (Index = (u32)0x0; XDcfg_ConfigTable[Index].Name != NULL; Index++) {
if ((XDcfg_ConfigTable[Index].BaseAddr == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XDcfg_ConfigTable[Index];
break;
}
}
return (CfgPtr);
}
#endif
/** @} */

326
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the implementation of the interface functions for XDmaPs
@ -46,6 +47,7 @@
* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
* 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification.
* 2.6 hk 02/14/20 Correct boundary check for Channel.
* 2.7 aj 12/07/23 Fixed changes to support system device tree flow
*
* </pre>
*
@ -78,8 +80,8 @@
/************************** Function Prototypes *****************************/
static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
unsigned int Channel,
unsigned int Thread);
unsigned int Channel,
unsigned int Thread);
static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
@ -88,7 +90,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
unsigned CacheLength);
unsigned CacheLength);
static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
@ -125,8 +127,8 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
*
*****************************************************************************/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr)
XDmaPs_Config *Config,
u32 EffectiveAddr)
{
int Status = XST_SUCCESS;
unsigned int CacheLength = 0;
@ -143,15 +145,26 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
/*
* Setup the driver instance using passed in parameters
*/
#ifndef SDT
InstPtr->Config.DeviceId = Config->DeviceId;
#endif
InstPtr->Config.BaseAddress = EffectiveAddr;
#ifdef SDT
InstPtr->Config.IntrParent = Config->IntrParent;
/* Added one fault Inerrupt and eight per-channel Interrupt */
for (Channel = 0; Channel < (XDMAPS_CHANNELS_PER_DEV + 1); Channel++) {
InstPtr->Config.IntrId[Channel] = Config->IntrId[Channel];
}
#endif
CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
if (CacheLength < 2 || CacheLength > 5)
if (CacheLength < 2 || CacheLength > 5) {
CacheLength = 0;
else
} else {
CacheLength = 1 << CacheLength;
}
InstPtr->CacheLength = CacheLength;
@ -161,7 +174,11 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
ChanData = InstPtr->Chans + Channel;
ChanData->ChanId = Channel;
#ifndef SDT
ChanData->DevId = Config->DeviceId;
#else
ChanData->DevId = XDmaPs_GetDrvIndex(InstPtr, EffectiveAddr);
#endif
}
InstPtr->IsReady = 1;
@ -185,7 +202,7 @@ int XDmaPs_ResetManager(XDmaPs *InstPtr)
{
int Status;
Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
0, 0);
0, 0);
return Status;
}
@ -207,7 +224,7 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
{
int Status;
Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
Channel, 1);
Channel, 1);
return Status;
@ -247,8 +264,11 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
#ifndef SDT
DevId = InstPtr->Config.DeviceId;
#else
DevId = XDmaPs_GetDrvIndex(InstPtr, BaseAddr);
#endif
if (Fsm) {
/*
@ -275,9 +295,9 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
if (Fsc & (0x01 << Chan)) {
FaultType =
XDmaPs_ReadReg(BaseAddr,
XDmaPs_FTCn_OFFSET(Chan));
XDmaPs_FTCn_OFFSET(Chan));
Pc = XDmaPs_ReadReg(BaseAddr,
XDmaPs_CPCn_OFFSET(Chan));
XDmaPs_CPCn_OFFSET(Chan));
/* kill the channel thread */
/* Should we disable interrupt? */
@ -302,7 +322,7 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
if (DmaProgBuf)
XDmaPs_BufPool_Free(ChanData->ProgBufPool,
DmaProgBuf);
DmaProgBuf);
DmaCmd->GeneratedDmaProg = NULL;
}
@ -332,16 +352,17 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
*
******************************************************************************/
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef)
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef)
{
XDmaPs_ChannelData *ChanData;
Xil_AssertNonvoid(InstPtr != NULL);
if (Channel >= XDMAPS_CHANNELS_PER_DEV)
if (Channel >= XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
ChanData = InstPtr->Chans + Channel;
@ -367,8 +388,8 @@ int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
*
******************************************************************************/
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef)
XDmaPsFaultHandler FaultHandler,
void *CallbackRef)
{
Xil_AssertNonvoid(InstPtr != NULL);
@ -437,7 +458,7 @@ static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
*
*****************************************************************************/
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns)
u32 Imm, unsigned int Ns)
{
/*
* DMAGO encoding:
@ -504,7 +525,7 @@ static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
*
*****************************************************************************/
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations)
unsigned LoopIterations)
{
/*
* DMALP encoding
@ -742,19 +763,19 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg)
static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
{
switch (EndianSwapSize) {
case 0:
case 8:
return 0;
case 16:
return 1;
case 32:
return 2;
case 64:
return 3;
case 128:
return 4;
default:
return 0;
case 0:
case 8:
return 0;
case 16:
return 1;
case 32:
return 2;
case 64:
return 3;
case 128:
return 4;
default:
return 0;
}
}
@ -775,24 +796,24 @@ static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
{
switch (BurstSize) {
case 1:
return 0;
case 2:
return 1;
case 4:
return 2;
case 8:
return 3;
case 16:
return 4;
case 32:
return 5;
case 64:
return 6;
case 128:
return 7;
default:
return 0;
case 1:
return 0;
case 2:
return 1;
case 4:
return 2;
case 8:
return 3;
case 16:
return 4;
case 32:
return 5;
case 64:
return 6;
case 128:
return 7;
default:
return 0;
}
}
@ -835,7 +856,7 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
| ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
| ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
@ -843,21 +864,21 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
| ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
| ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
u32 ccr_value = (es << 28)
| (dst_cache_ctrl << 25)
| (dst_prot_ctrl << 22)
| (dst_burst_len << 18)
| (dst_burst_size << 15)
| (dst_inc_bit << 14)
| (src_cache_ctrl << 11)
| (src_prot_ctrl << 8)
| (src_burst_len << 4)
| (src_burst_size << 1)
| (src_inc_bit);
| (dst_cache_ctrl << 25)
| (dst_prot_ctrl << 22)
| (dst_burst_len << 18)
| (dst_burst_size << 15)
| (dst_inc_bit << 14)
| (src_cache_ctrl << 11)
| (src_prot_ctrl << 8)
| (src_burst_len << 4)
| (src_burst_size << 1)
| (src_inc_bit);
return ccr_value;
}
@ -883,9 +904,9 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
*
*****************************************************************************/
int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
int CacheLength,
char *DmaProgLoopStart,
int LoopCount)
int CacheLength,
char *DmaProgLoopStart,
int LoopCount)
{
int CacheStartOffset;
int CacheEndOffset;
@ -909,7 +930,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
!= CacheEndOffset / CacheLength) {
/* insert the nops */
NumNops = CacheLength
- CacheStartOffset % CacheLength;
- CacheStartOffset % CacheLength;
while (NumNops--) {
DmaProgBuf +=
XDmaPs_Instr_DMANOP(DmaProgBuf);
@ -920,7 +941,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
DmaProgBuf - 2, 0);
DmaProgBuf - 2, 0);
return DmaProgBuf - DmaProgLoopStart;
}
@ -948,10 +969,10 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
*
*****************************************************************************/
int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
int CacheLength,
char *DmaProgLoopStart,
unsigned int LoopCountOuter,
unsigned int LoopCountInner)
int CacheLength,
char *DmaProgLoopStart,
unsigned int LoopCountOuter,
unsigned int LoopCountInner)
{
int CacheStartOffset;
int CacheEndOffset;
@ -974,14 +995,14 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
*/
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCountInner);
CacheLength,
DmaProgBuf,
LoopCountInner);
/* outer loop end */
DmaProgBuf +=
XDmaPs_Instr_DMALPEND(DmaProgBuf,
InnerLoopStart,
1);
InnerLoopStart,
1);
/*
* the nested loop is constructed for
@ -1004,7 +1025,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
!= CacheEndOffset / CacheLength) {
/* insert the nops */
NumNops = CacheLength
- CacheStartOffset % CacheLength;
- CacheStartOffset % CacheLength;
while (NumNops--) {
DmaProgBuf +=
XDmaPs_Instr_DMANOP(DmaProgBuf);
@ -1021,10 +1042,10 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
/* inner DMALPEND */
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
DmaProgBuf - 2, 0);
DmaProgBuf - 2, 0);
/* outer DMALPEND */
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
InnerLoopStart, 1);
InnerLoopStart, 1);
/* return the number of bytes */
return DmaProgBuf - DmaProgLoopStart;
@ -1066,7 +1087,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
*
*****************************************************************************/
static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
unsigned CacheLength)
unsigned CacheLength)
{
/*
* unpack arguments
@ -1118,18 +1139,20 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* insert DMAMOV for SAR and DAR */
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_SAR,
SrcAddr);
XDMAPS_MOV_SAR,
SrcAddr);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_DAR,
DstAddr);
XDMAPS_MOV_DAR,
DstAddr);
if (ChanCtrl->SrcInc)
if (ChanCtrl->SrcInc) {
SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
}
if (ChanCtrl->DstInc)
if (ChanCtrl->DstInc) {
DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
}
if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
ChanCtrl = &Mem2MemByteCC;
@ -1151,12 +1174,12 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* if head is unaligned, transfer head in bytes */
UnalignedCount = MemBurstSize - Unaligned;
CCRValue = XDMAPS_CCR_SINGLE_BYTE
| (SrcInc & 1)
| ((DstInc & 1) << 14);
| (SrcInc & 1)
| ((DstInc & 1) << 14);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
for (Index = 0; Index < UnalignedCount; Index++) {
DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
@ -1169,8 +1192,8 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* now the burst transfer part */
CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
@ -1196,16 +1219,16 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
if (LoopCount1 > 1)
DmaProgBuf +=
XDmaPs_ConstructNestedLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCount1,
256);
CacheLength,
DmaProgBuf,
LoopCount1,
256);
else
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
256);
CacheLength,
DmaProgBuf,
256);
/* there will be some that cannot be covered by
* nested loops
@ -1215,9 +1238,9 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
if (LoopCount > 0) {
DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCount);
CacheLength,
DmaProgBuf,
LoopCount);
}
if (TailBytes) {
@ -1244,13 +1267,13 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
DmaProgBuf +=
XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
TailWords);
CacheLength,
DmaProgBuf,
TailWords);
}
@ -1264,19 +1287,19 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
* to perform a burst.
*/
CCRValue = XDMAPS_CCR_SINGLE_BYTE
| (SrcInc & 1)
| ((DstInc & 1) << 14);
| (SrcInc & 1)
| ((DstInc & 1) << 14);
DmaProgBuf +=
XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
TailBytes);
CacheLength,
DmaProgBuf,
TailBytes);
}
}
@ -1322,8 +1345,9 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Xil_AssertNonvoid(Cmd != NULL);
if (Channel > XDMAPS_CHANNELS_PER_DEV)
if (Channel > XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
ChanData = InstPtr->Chans + Channel;
ChanCtrl = &Cmd->ChanCtrl;
@ -1352,7 +1376,7 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Cmd->GeneratedDmaProg = Buf;
ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
InstPtr->CacheLength);
InstPtr->CacheLength);
Cmd->GeneratedDmaProgLength = ProgLen;
@ -1396,8 +1420,9 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Xil_AssertNonvoid(InstPtr != NULL);
Xil_AssertNonvoid(Cmd != NULL);
if (Channel > XDMAPS_CHANNELS_PER_DEV)
if (Channel > XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
Buf = (void *)Cmd->GeneratedDmaProg;
ChanData = InstPtr->Chans + Channel;
@ -1437,8 +1462,8 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
*
****************************************************************************/
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg)
XDmaPs_Cmd *Cmd,
int HoldDmaProg)
{
int Status;
u32 DmaProg = 0;
@ -1450,32 +1475,35 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
Cmd->DmaStatus = XST_FAILURE;
if (XDmaPs_IsActive(InstPtr, Channel))
if (XDmaPs_IsActive(InstPtr, Channel)) {
return XST_DEVICE_BUSY;
}
if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
if (Status)
if (Status) {
return XST_FAILURE;
}
}
InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
if (Cmd->UserDmaProg)
if (Cmd->UserDmaProg) {
DmaProg = (u32)Cmd->UserDmaProg;
else if (Cmd->GeneratedDmaProg)
} else if (Cmd->GeneratedDmaProg) {
DmaProg = (u32)Cmd->GeneratedDmaProg;
}
if (DmaProg) {
/* enable the interrupt */
Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET);
XDMAPS_INTEN_OFFSET);
Inten |= 0x01 << Channel; /* set the correpsonding bit */
XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET,
Inten);
XDMAPS_INTEN_OFFSET,
Inten);
Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET);
XDMAPS_INTEN_OFFSET);
InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
@ -1484,13 +1512,12 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
}
if (Cmd->ChanCtrl.DstInc) {
Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
Cmd->BD.Length);
Cmd->BD.Length);
}
Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
Channel, DmaProg);
}
else {
Channel, DmaProg);
} else {
InstPtr->Chans[Channel].DmaCmdToHw = NULL;
Status = XST_FAILURE;
}
@ -1517,8 +1544,9 @@ int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
Xil_AssertNonvoid(InstPtr != NULL);
/* Need to assert Channel is in range */
if (Channel >= XDMAPS_CHANNELS_PER_DEV)
if (Channel >= XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
}
@ -1725,8 +1753,8 @@ void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
*
*****************************************************************************/
static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
unsigned int Channel,
unsigned int Thread)
unsigned int Channel,
unsigned int Thread)
{
u32 DbgInst0;
int WaitCount;
@ -1736,14 +1764,15 @@ static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
/* wait while debug status is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT))
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
}
if (WaitCount >= XDMAPS_MAX_WAIT) {
/* wait time out */
xil_printf("PL330 device at %x debug status busy time out\n",
BaseAddr);
BaseAddr);
return -1;
}
@ -1816,7 +1845,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
/* wait while debug status is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
@ -1837,7 +1866,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
/* wait while the DMA Manager is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr,
XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
!= XDMAPS_DS_DMA_STATUS_STOPPED
&& WaitCount <= XDMAPS_MAX_WAIT) {
WaitCount++;
@ -1896,7 +1925,7 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
if (DmaProgBuf)
XDmaPs_BufPool_Free(ChanData->ProgBufPool,
DmaProgBuf);
DmaProgBuf);
DmaCmd->GeneratedDmaProg = NULL;
}
@ -1925,8 +1954,9 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
{
int Index;
for (Index = 0; Index < Length; Index++)
for (Index = 0; Index < Length; Index++) {
xil_printf("[%x] %x\r\n", Index, Buf[Index]);
}
}
/****************************************************************************/
@ -1940,20 +1970,20 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
* @note None.
*
*****************************************************************************/
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
{
if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
xil_printf("Generated DMA program (%d):\r\n",
Cmd->GeneratedDmaProgLength);
XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
Cmd->GeneratedDmaProgLength);
Cmd->GeneratedDmaProgLength);
}
if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
xil_printf("User defined DMA program (%d):\r\n",
Cmd->UserDmaProgLength);
XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
Cmd->UserDmaProgLength);
Cmd->UserDmaProgLength);
}
}

56
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
* @details
*
@ -60,6 +61,7 @@
* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
* to static inline to avoid the linkage conflict for IAR compiler.
* 2.9 aj 11/07/23 Added support for system device tree
* </pre>
*
*****************************************************************************/
@ -88,8 +90,19 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of device (IPIF) */
#ifdef SDT
u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDmaPs_Config;
@ -169,15 +182,15 @@ typedef struct {
* It's the done handler a user can set for a channel
*/
typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
/**
* It's the fault handler a user can set for a channel
*/
typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
#define XDMAPS_MAX_CHAN_BUFS 2
#define XDMAPS_CHAN_BUF_LEN 128
@ -236,18 +249,18 @@ typedef struct {
* Functions implemented in xdmaps.c
*/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr);
XDmaPs_Config *Config,
u32 EffectiveAddr);
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
@ -256,13 +269,13 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
int XDmaPs_Instr_DMARMB(char *DmaProg);
@ -276,10 +289,10 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg);
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns);
u32 Imm, unsigned int Ns);
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations);
unsigned LoopIterations);
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
@ -312,7 +325,12 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr);
/*
* Static loopup function implemented in xdmaps_sinit.c
*/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress);
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress);
#endif
/*

5
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_g.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains a configuration table where each entry is a configuration

36
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,10 +8,10 @@
/**
*
* @file xdmaps_hw.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the implementation of the interface reset functionality
* This file contains the implementation of the interface reset functionality
* for XDmaPs driver.
*
* <pre>
@ -40,10 +41,10 @@
/*****************************************************************************/
/**
* This function perform the reset sequence to the given dmaps interface by
* This function perform the reset sequence to the given dmaps interface by
* configuring the appropriate control bits in the dmaps specifc registers
* the dmaps reset squence involves the following steps
* Disable all the interuupts
* Disable all the interuupts
* Clear the pending interrupts
* Kill all the active channel threads
* Kill the manager thread
@ -52,8 +53,8 @@
*
* @return N/A
*
* @note
* This function will not modify the slcr registers that are relavant for
* @note
* This function will not modify the slcr registers that are relavant for
* dmaps controller
******************************************************************************/
void XDmaPs_ResetHw(u32 BaseAddress)
@ -67,22 +68,23 @@ void XDmaPs_ResetHw(u32 BaseAddress)
/* Clear the interrupts */
XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
/* Kill the dma channel threads */
for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
for (ChanIndex = 0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT))
WaitCount++;
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
}
DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
}
}
/* Kill the manager thread */
DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
}

9
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_hw.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
@ -233,7 +234,7 @@ extern "C" {
#define XDMAPS_INTCLR_ALL_MASK 0xFF
#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
Xil_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
@ -251,7 +252,7 @@ extern "C" {
* u32 RegisterValue)
******************************************************************************/
#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes *****************************/

11
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_selftest.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the self-test functions for the XDmaPs driver.
@ -71,13 +72,15 @@ int XDmaPs_SelfTest(XDmaPs *InstPtr)
int i;
if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
& XDMAPS_DBGSTATUS_BUSY) {
return XST_FAILURE;
}
for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
if (XDmaPs_ReadReg(BaseAddr,
XDmaPs_CSn_OFFSET(i)))
XDmaPs_CSn_OFFSET(i))) {
return XST_FAILURE;
}
}
return XST_SUCCESS;
}

40
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,10 +8,10 @@
/**
*
* @file xdmaps_sinit.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* The implementation of the XDmaPs driver's static initialzation
* The implementation of the XDmaPs driver's static initialization
* functionality.
*
* <pre>
@ -26,7 +27,9 @@
/***************************** Include Files ********************************/
#include "xstatus.h"
#ifndef SDT
#include "xparameters.h"
#endif
#include "xdmaps.h"
/************************** Constant Definitions ****************************/
@ -60,6 +63,7 @@ extern XDmaPs_Config XDmaPs_ConfigTable[];
* None.
*
******************************************************************************/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
{
XDmaPs_Config *CfgPtr = NULL;
@ -75,4 +79,34 @@ XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
return CfgPtr;
}
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress)
{
XDmaPs_Config *CfgPtr = NULL;
int i;
for (i = (u32)0x0; XDmaPs_ConfigTable[i].Name != NULL; i++) {
if ((XDmaPs_ConfigTable[i].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XDmaPs_ConfigTable[i];
break;
}
}
return CfgPtr;
}
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress)
{
u32 Index = 0;
for (Index = (u32)0x0; XDmaPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XDmaPs_ConfigTable[Index].BaseAddress == BaseAddress)) {
break;
}
}
return Index;
}
#endif
/** @} */

14
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* The XEmacPs driver. Functions in this file are the minimum required functions
@ -85,12 +86,21 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
Xil_AssertNonvoid(CfgPtr != NULL);
/* Set device base address and ID */
#ifndef SDT
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
#endif
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
#ifdef SDT
InstancePtr->Config.IntrId = CfgPtr->IntrId;
InstancePtr->Config.IntrParent = CfgPtr->IntrParent;
#endif
#if defined (XCLOCKING)
InstancePtr->Config.RefClk = CfgPtr->RefClk;
#endif
#ifdef SDT
InstancePtr->Config.PhyType = CfgPtr->PhyType;
#endif
InstancePtr->Config.S1GDiv0 = CfgPtr->S1GDiv0;
InstancePtr->Config.S1GDiv1 = CfgPtr->S1GDiv1;

101
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
* @details
*
@ -417,15 +418,15 @@ extern "C" {
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
@ -456,11 +457,11 @@ extern "C" {
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
@ -500,7 +501,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
u32 ErrorWord);
/*@}*/
@ -508,12 +509,25 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifdef SDT
char *Name; /**< Unique name of the device */
#else
u16 DeviceId; /**< Unique ID of device */
#endif
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#if defined (XCLOCKING)
#ifdef SDT
u16 IntrId;
UINTPTR IntrParent;
#endif
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clock */
#endif
#ifdef SDT
char *PhyType; /**< PhyType indicates which type of PHY interface is
* used (MII, GMII, RGMII, etc.
*/
#endif
u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
@ -606,8 +620,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -627,8 +641,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -648,8 +662,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -669,8 +683,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -687,10 +701,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
@ -711,9 +725,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
@ -734,9 +748,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
@ -761,10 +775,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
/****************************************************************************/
/**
@ -781,8 +795,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_GetRXWatermark(InstancePtr) \
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
/*
* Initialization functions in xemacps.c
*/
@ -797,7 +811,12 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
/*
* Lookup configuration in xemacps_sinit.c
*/
#ifndef SDT
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
#else
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Interrupt-related functions in xemacps_intr.c
@ -823,7 +842,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,

10
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bd.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header provides operations to manage buffer descriptors in support
@ -45,6 +46,7 @@
* 3.2 hk 11/18/15 Change BD typedef and number of words.
* 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
* 3.9 aj 22/03/24 Add mask for XEmaPs_BdGetBufAddr
*
* </pre>
*
@ -239,11 +241,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
#endif
/*****************************************************************************/

16
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bdring.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file implements buffer descriptor ring related functions.
@ -676,12 +677,13 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
BdPartialCount = 0U;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
/* Reached the end of the work group */
if (CurBdPtr == RingPtr->HwTail) {
break;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
}
/* Subtract off any partial packet BDs found */
@ -822,13 +824,13 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
BdPartialCount++;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
/* Reached the end of the work group */
if (CurBdPtr == RingPtr->HwTail) {
break;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
}
/* Subtract off any partial packet BDs found */

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_control.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* Functions in this file implement general purpose command and control related

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_g.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains a configuration table that specifies the configuration of

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_hw.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains the implementation of the ethernet interface reset sequence

2
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h
View File

@ -8,7 +8,7 @@
/**
*
* @file xemacps_hw.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or

7
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_intr.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* Functions in this file implement general purpose interrupt processing related
@ -228,7 +229,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
/* Transmit error conditions interrupt */
if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
(!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
((!(RegISR & XEMACPS_IXR_TXCOMPL_MASK)) != 0x00000000U)) {
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);

28
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_sinit.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains lookup method by device ID when success, it returns
@ -27,7 +28,9 @@
/***************************** Include Files *********************************/
#include "xemacps.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -35,7 +38,11 @@
/**************************** Type Definitions *******************************/
/*************************** Variable Definitions *****************************/
#ifdef SDT
extern XEmacPs_Config XEmacPs_ConfigTable[];
#else
extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
#endif
/***************** Macros (Inline Functions) Definitions *********************/
@ -54,6 +61,22 @@ extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
* device ID, or NULL if no match is found.
*
******************************************************************************/
#ifdef SDT
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress)
{
XEmacPs_Config *CfgPtr = NULL;
u32 Index;
/* Checks all the instances */
for (Index = (u32)0x0; XEmacPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XEmacPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XEmacPs_ConfigTable[Index];
break;
}
}
return (XEmacPs_Config *)(CfgPtr);
}
#else
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
{
XEmacPs_Config *CfgPtr = NULL;
@ -68,4 +91,5 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
return (XEmacPs_Config *)(CfgPtr);
}
#endif
/** @} */

8
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -35,6 +35,9 @@
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/13/19 Added Versal support.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Added multi-core interrupt support.
*
* </pre>
*
******************************************************************************/
@ -89,7 +92,9 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
*/
InstancePtr->IsReady = 0U;
InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
#ifndef SDT
InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
#endif
InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
InstancePtr->Platform = XGetPlatform_Info();
@ -176,6 +181,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
}
InstancePtr->CoreIntrMask[i] = 0;
}
/* Indicate the component is now ready to use. */

33
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -124,6 +124,11 @@
* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
* 3.9 sne 03/15/21 Fixed MISRA-C violations.
* 3.11 sg 02/23/23 Update bank and pin mapping information.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto
* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable,
* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin
* to add multi-core interrupt support.
*
* </pre>
*
@ -167,6 +172,7 @@ extern "C" {
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
@ -209,8 +215,18 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XGpioPs_Config;
/**
@ -227,6 +243,7 @@ typedef struct {
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */
} XGpioPs;
/************************** Variable Definitions *****************************/
@ -262,12 +279,12 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
@ -283,14 +300,18 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

36
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -35,6 +35,7 @@
* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
* 3.13 gm 03/15/24 Added multi-core interrupt support.
*
* </pre>
*
@ -71,7 +72,7 @@
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -87,6 +88,9 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, Mask);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] |= Mask;
}
/****************************************************************************/
@ -102,7 +106,7 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
@ -123,6 +127,9 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, IntrReg);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] |= IntrReg;
}
/****************************************************************************/
@ -142,7 +149,7 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -158,6 +165,9 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, Mask);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] &= ~Mask;
}
/****************************************************************************/
@ -173,7 +183,7 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
@ -194,6 +204,9 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, IntrReg);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] &= ~IntrReg;
}
/****************************************************************************/
@ -735,6 +748,7 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
{
u8 Bank;
u32 Mask;
u32 IntrStatus;
u32 IntrEnabled;
@ -755,12 +769,12 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
#endif
IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
if ((IntrStatus & IntrEnabled) != (u32)0) {
XGpioPs_IntrClear(InstancePtr, Bank,
(IntrStatus & IntrEnabled));
InstancePtr->Handler(InstancePtr->
CallBackRef, Bank,
(IntrStatus & IntrEnabled));
Mask = IntrStatus & IntrEnabled & InstancePtr->CoreIntrMask[Bank];
if (Mask != (u32)0)
{
XGpioPs_IntrClear(InstancePtr, Bank, Mask);
InstancePtr->Handler(InstancePtr->CallBackRef, Bank, Mask);
}
}
}

4
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -61,7 +61,7 @@
*
*
******************************************************************************/
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
{
s32 Status = (s32)0;
u32 IntrEnabled;

22
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -24,6 +24,8 @@
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.12 gm 07/11/23 Added SDT support.
*
* </pre>
*
******************************************************************************/
@ -57,6 +59,7 @@
* @note None.
*
******************************************************************************/
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
{
XGpioPs_Config *CfgPtr = NULL;
@ -71,4 +74,21 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
return (XGpioPs_Config *)CfgPtr;
}
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress)
{
XGpioPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = (u32)0x0; XGpioPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XGpioPs_ConfigTable[Index].BaseAddr == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XGpioPs_ConfigTable[Index];
break;
}
}
return (XGpioPs_Config *)CfgPtr;
}
#endif
/** @} */

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