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xilinx ps7_cortexa9 code Version xilinx_v2024.1

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This commit is contained in:
Ulrich Mohr
2024-10-14 13:36:25 +02:00
parent dd9c39af30
commit fb4b12c8f9
219 changed files with 11733 additions and 7355 deletions
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3
bsp_z7/ps7_cortexa9_0/libsrc/cpu_cortexa9/src/xcpu_cortexa9.h
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@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xcpu_cortexa9.h
* @addtogroup cpu_cortexa9_v2_11
* @addtogroup cpu_cortexa9 Overview
* @{
* @details
*

123
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.c
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@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the implementation of the interface functions for XDcfg
@ -55,7 +56,7 @@
* XDCFG_INT_STS_OFFSET) &
* XDCFG_IXR_D_P_DONE_MASK) !=
* XDCFG_IXR_D_P_DONE_MASK);
*
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
*
* </pre>
*
@ -106,7 +107,7 @@
*
******************************************************************************/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
@ -124,7 +125,9 @@ int XDcfg_CfgInitialize(XDcfg *InstancePtr,
/*
* Copy configuration into instance.
*/
#ifndef SDT
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
#endif
/*
* Save the base address pointer such that the registers of the block
@ -172,10 +175,10 @@ void XDcfg_EnablePCAP(XDcfg *InstancePtr)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
(CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
}
@ -203,10 +206,10 @@ void XDcfg_DisablePCAP(XDcfg *InstancePtr)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
(CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
}
@ -235,10 +238,10 @@ void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg | Mask));
(CtrlReg | Mask));
}
@ -266,10 +269,10 @@ void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(CtrlReg & ~Mask));
(CtrlReg & ~Mask));
}
@ -488,7 +491,7 @@ void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
Data);
Data);
}
@ -545,10 +548,10 @@ void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
(RegData | Mask));
(RegData | Mask));
}
/****************************************************************************/
@ -601,10 +604,10 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
/* Read the PCAP status register for DMA status */
RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_STATUS_OFFSET);
XDCFG_STATUS_OFFSET);
if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
XDCFG_STATUS_DMA_CMD_Q_F_MASK){
XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
return XST_SUCCESS;
}
@ -637,24 +640,24 @@ u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
*
****************************************************************************/
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength)
u32 SrcWordLength, u32 DestWordLength)
{
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_SRC_ADDR_OFFSET,
SourcePtr);
XDCFG_DMA_SRC_ADDR_OFFSET,
SourcePtr);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_DEST_ADDR_OFFSET,
DestPtr);
XDCFG_DMA_DEST_ADDR_OFFSET,
DestPtr);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_SRC_LEN_OFFSET,
SrcWordLength);
XDCFG_DMA_SRC_LEN_OFFSET,
SrcWordLength);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_DMA_DEST_LEN_OFFSET,
DestWordLength);
XDCFG_DMA_DEST_LEN_OFFSET,
DestWordLength);
}
/******************************************************************************/
@ -680,8 +683,8 @@ void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
*
****************************************************************************/
static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
u32 SrcWordLength, u32 DestPtr,
u32 DestWordLength)
u32 SrcWordLength, u32 DestPtr,
u32 DestWordLength)
{
u32 IntrReg;
@ -689,7 +692,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
* Send READ Frame command to FPGA
*/
XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
SrcWordLength, 0);
SrcWordLength, 0);
/*
* Store the enabled interrupts to enable before the actual read
@ -701,10 +704,10 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
/*
* Wait till you get the DMA done for the read command sent
*/
while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET) &
XDCFG_IXR_D_P_DONE_MASK) !=
XDCFG_IXR_D_P_DONE_MASK);
while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET) &
XDCFG_IXR_D_P_DONE_MASK) !=
XDCFG_IXR_D_P_DONE_MASK);
/*
* Enable the previously stored Interrupts .
*/
@ -714,7 +717,7 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
* Initiate the DMA write command.
*/
XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
0, DestWordLength);
0, DestWordLength);
return XST_SUCCESS;
}
@ -762,9 +765,9 @@ static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
*
*****************************************************************************/
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType)
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType)
{
u32 CtrlReg;
@ -781,7 +784,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* Check whether the fabric is in initialized state
*/
if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
& XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
& XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
/*
* We don't need to check PCFG_INIT to be high for
* non-encrypted loopback transfers.
@ -792,7 +795,7 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
}
if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
(TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
(TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
/* Check for valid source pointer and length */
if ((!SourcePtr) || (SrcWordLength == 0)) {
@ -803,8 +806,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
/*
@ -815,8 +818,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
}
if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
@ -828,11 +831,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* operation.
*/
XDcfg_SetControlRegister(InstancePtr,
XDCFG_CTRL_PCAP_RATE_EN_MASK);
XDCFG_CTRL_PCAP_RATE_EN_MASK);
}
XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
(u32)DestPtr, SrcWordLength, DestWordLength);
(u32)DestPtr, SrcWordLength, DestWordLength);
}
@ -847,8 +850,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
/*
* For PCAP readback of FPGA configuration register or memory,
@ -860,26 +863,26 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* transfer to support this mode of operation.
*/
return XDcfg_PcapReadback(InstancePtr,
(u32)SourcePtr, SrcWordLength,
(u32)DestPtr, DestWordLength);
(u32)SourcePtr, SrcWordLength,
(u32)DestPtr, DestWordLength);
}
if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
(TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
(TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
if ((!SourcePtr) || (SrcWordLength == 0) ||
(!DestPtr) || (DestWordLength == 0)) {
(!DestPtr) || (DestWordLength == 0)) {
return XST_INVALID_PARAM;
}
if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
/* Enable internal PCAP loopback */
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg |
XDCFG_MCTRL_PCAP_LPBK_MASK));
XDCFG_MCTRL_OFFSET, (CtrlReg |
XDCFG_MCTRL_PCAP_LPBK_MASK));
/*
* Clear QUARTER_PCAP_RATE_EN bit
@ -889,8 +892,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
XDCFG_CTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
XDCFG_CTRL_OFFSET, (CtrlReg &
~XDCFG_CTRL_PCAP_RATE_EN_MASK));
}
if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
@ -898,8 +901,8 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
XDCFG_MCTRL_OFFSET, (CtrlReg &
~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
/*
* Set the QUARTER_PCAP_RATE_EN bit
@ -907,11 +910,11 @@ u32 XDcfg_Transfer(XDcfg *InstancePtr,
* cycles, this is required for encrypted data.
*/
XDcfg_SetControlRegister(InstancePtr,
XDCFG_CTRL_PCAP_RATE_EN_MASK);
XDCFG_CTRL_PCAP_RATE_EN_MASK);
}
XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
(u32)DestPtr, SrcWordLength, DestWordLength);
(u32)DestPtr, SrcWordLength, DestWordLength);
}
return XST_SUCCESS;

48
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg.h
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@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
* @details
*
@ -133,6 +134,7 @@
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of devcfg in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -178,8 +180,18 @@ typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDcfg_Config;
/**
@ -210,7 +222,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_Unlock(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
@ -230,8 +242,8 @@ typedef struct {
#define XDcfg_GetPsVersion(InstancePtr) \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_OFFSET)) & \
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
@ -250,7 +262,7 @@ typedef struct {
*****************************************************************************/
#define XDcfg_ReadMultiBootConfig(InstancePtr) \
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MULTIBOOT_ADDR_OFFSET)
XDCFG_MULTIBOOT_ADDR_OFFSET)
/****************************************************************************/
@ -269,8 +281,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectIcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
/****************************************************************************/
/**
@ -288,8 +300,8 @@ typedef struct {
*****************************************************************************/
#define XDcfg_SelectPcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
@ -298,7 +310,11 @@ typedef struct {
/*
* Lookup configuration in xdevcfg_sinit.c.
*/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xdevcfg_selftest.c
@ -309,7 +325,7 @@ int XDcfg_SelfTest(XDcfg *InstancePtr);
* Interface functions in xdevcfg.c
*/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
void XDcfg_EnablePCAP(XDcfg *InstancePtr);
@ -344,12 +360,12 @@ u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength);
u32 SrcWordLength, u32 DestWordLength);
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
/*
* Interrupt related function prototypes implemented in xdevcfg_intr.c
@ -367,7 +383,7 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
void XDcfg_InterruptHandler(XDcfg *InstancePtr);
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef);
void *CallBackRef);
#ifdef __cplusplus
}

5
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_g.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains a table that specifies the configuration of the Device

10
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_hw.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the implementation of the interface reset functionality
@ -17,6 +18,7 @@
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 2.04a kpc 10/07/13 First release
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -59,7 +61,7 @@ void XDcfg_ResetHw(u32 BaseAddr)
/* Mask the interrupts */
XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
XDCFG_IXR_ALL_MASK);
XDCFG_IXR_ALL_MASK);
/* Clear the interuupt status */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
@ -77,7 +79,7 @@ void XDcfg_ResetHw(u32 BaseAddr)
XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
/*Reset the configuration register to reset value */
XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
XDCFG_CONFIG_RESET_VALUE);
XDCFG_CONFIG_RESET_VALUE);
/*Disable the PCAP rate enable bit */
Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;

28
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_hw.h
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains the hardware interface to the Device Config Interface.
@ -26,6 +27,7 @@
* version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -210,14 +212,14 @@ extern "C" {
* of Init Signal
*/
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
@ -266,9 +268,9 @@ extern "C" {
* Status
*/
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
/**< BBRAM key
* disable
*/
/**< BBRAM key
* disable
*/
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
* Enable Status
*/

32
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_intr.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_intr.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* Contains the implementation of interrupt related functions of the XDcfg
@ -22,6 +23,7 @@
* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
* set the mask instead of oring it with the
* value read from the interrupt status register
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -70,11 +72,11 @@ void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
* Enable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
XDCFG_INT_MASK_OFFSET);
RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
XDCFG_INT_MASK_OFFSET,
RegValue);
}
@ -108,11 +110,11 @@ void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
* Disable the specified interrupts in the Interrupt Mask Register.
*/
RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET);
XDCFG_INT_MASK_OFFSET);
RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_MASK_OFFSET,
RegValue);
XDCFG_INT_MASK_OFFSET,
RegValue);
}
/****************************************************************************/
/**
@ -170,7 +172,7 @@ u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
* Return the value read from the Interrupt Status register.
*/
return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
XDCFG_INT_STS_OFFSET);
}
/****************************************************************************/
@ -199,8 +201,8 @@ void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET,
Mask);
XDCFG_INT_STS_OFFSET,
Mask);
}
@ -232,7 +234,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
* Read the Interrupt status register.
*/
IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET);
XDCFG_INT_STS_OFFSET);
/*
* Write the status back to clear the interrupts so that no
@ -240,13 +242,13 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
* This also does the DMA acknowledgment automatically.
*/
XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
XDCFG_INT_STS_OFFSET, IntrStatusReg);
XDCFG_INT_STS_OFFSET, IntrStatusReg);
/*
* Signal application that there are events to handle.
*/
InstancePtr->StatusHandler(InstancePtr->CallBackRef,
IntrStatusReg);
IntrStatusReg);
}
@ -268,7 +270,7 @@ void XDcfg_InterruptHandler(XDcfg *InstancePtr)
*
*****************************************************************************/
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef)
void *CallBackRef)
{
/*
* Asserts validate the input arguments

5
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_selftest.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* Contains diagnostic self-test functions for the XDcfg driver.

27
bsp_z7/ps7_cortexa9_0/libsrc/devcfg/src/xdevcfg_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdevcfg_sinit.c
* @addtogroup devcfg_v3_7
* @addtogroup devcfg Overview
* @{
*
* This file contains method for static initialization (compile-time) of the
@ -20,6 +21,7 @@
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 3.5 ms 08/07/17 Fixed compilation warnings.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -27,7 +29,9 @@
/***************************** Include Files *********************************/
#include "xdevcfg.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -50,6 +54,7 @@
* @note None.
*
******************************************************************************/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
{
extern XDcfg_Config XDcfg_ConfigTable[];
@ -65,4 +70,22 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
return (CfgPtr);
}
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress)
{
extern XDcfg_Config XDcfg_ConfigTable[];
XDcfg_Config *CfgPtr = NULL;
u32 Index;
for (Index = (u32)0x0; XDcfg_ConfigTable[Index].Name != NULL; Index++) {
if ((XDcfg_ConfigTable[Index].BaseAddr == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XDcfg_ConfigTable[Index];
break;
}
}
return (CfgPtr);
}
#endif
/** @} */

326
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the implementation of the interface functions for XDmaPs
@ -46,6 +47,7 @@
* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
* 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification.
* 2.6 hk 02/14/20 Correct boundary check for Channel.
* 2.7 aj 12/07/23 Fixed changes to support system device tree flow
*
* </pre>
*
@ -78,8 +80,8 @@
/************************** Function Prototypes *****************************/
static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
unsigned int Channel,
unsigned int Thread);
unsigned int Channel,
unsigned int Thread);
static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
@ -88,7 +90,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
unsigned CacheLength);
unsigned CacheLength);
static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
@ -125,8 +127,8 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
*
*****************************************************************************/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr)
XDmaPs_Config *Config,
u32 EffectiveAddr)
{
int Status = XST_SUCCESS;
unsigned int CacheLength = 0;
@ -143,15 +145,26 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
/*
* Setup the driver instance using passed in parameters
*/
#ifndef SDT
InstPtr->Config.DeviceId = Config->DeviceId;
#endif
InstPtr->Config.BaseAddress = EffectiveAddr;
#ifdef SDT
InstPtr->Config.IntrParent = Config->IntrParent;
/* Added one fault Inerrupt and eight per-channel Interrupt */
for (Channel = 0; Channel < (XDMAPS_CHANNELS_PER_DEV + 1); Channel++) {
InstPtr->Config.IntrId[Channel] = Config->IntrId[Channel];
}
#endif
CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
if (CacheLength < 2 || CacheLength > 5)
if (CacheLength < 2 || CacheLength > 5) {
CacheLength = 0;
else
} else {
CacheLength = 1 << CacheLength;
}
InstPtr->CacheLength = CacheLength;
@ -161,7 +174,11 @@ int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
ChanData = InstPtr->Chans + Channel;
ChanData->ChanId = Channel;
#ifndef SDT
ChanData->DevId = Config->DeviceId;
#else
ChanData->DevId = XDmaPs_GetDrvIndex(InstPtr, EffectiveAddr);
#endif
}
InstPtr->IsReady = 1;
@ -185,7 +202,7 @@ int XDmaPs_ResetManager(XDmaPs *InstPtr)
{
int Status;
Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
0, 0);
0, 0);
return Status;
}
@ -207,7 +224,7 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
{
int Status;
Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
Channel, 1);
Channel, 1);
return Status;
@ -247,8 +264,11 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
#ifndef SDT
DevId = InstPtr->Config.DeviceId;
#else
DevId = XDmaPs_GetDrvIndex(InstPtr, BaseAddr);
#endif
if (Fsm) {
/*
@ -275,9 +295,9 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
if (Fsc & (0x01 << Chan)) {
FaultType =
XDmaPs_ReadReg(BaseAddr,
XDmaPs_FTCn_OFFSET(Chan));
XDmaPs_FTCn_OFFSET(Chan));
Pc = XDmaPs_ReadReg(BaseAddr,
XDmaPs_CPCn_OFFSET(Chan));
XDmaPs_CPCn_OFFSET(Chan));
/* kill the channel thread */
/* Should we disable interrupt? */
@ -302,7 +322,7 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
if (DmaProgBuf)
XDmaPs_BufPool_Free(ChanData->ProgBufPool,
DmaProgBuf);
DmaProgBuf);
DmaCmd->GeneratedDmaProg = NULL;
}
@ -332,16 +352,17 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr)
*
******************************************************************************/
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef)
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef)
{
XDmaPs_ChannelData *ChanData;
Xil_AssertNonvoid(InstPtr != NULL);
if (Channel >= XDMAPS_CHANNELS_PER_DEV)
if (Channel >= XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
ChanData = InstPtr->Chans + Channel;
@ -367,8 +388,8 @@ int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
*
******************************************************************************/
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef)
XDmaPsFaultHandler FaultHandler,
void *CallbackRef)
{
Xil_AssertNonvoid(InstPtr != NULL);
@ -437,7 +458,7 @@ static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
*
*****************************************************************************/
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns)
u32 Imm, unsigned int Ns)
{
/*
* DMAGO encoding:
@ -504,7 +525,7 @@ static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
*
*****************************************************************************/
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations)
unsigned LoopIterations)
{
/*
* DMALP encoding
@ -742,19 +763,19 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg)
static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
{
switch (EndianSwapSize) {
case 0:
case 8:
return 0;
case 16:
return 1;
case 32:
return 2;
case 64:
return 3;
case 128:
return 4;
default:
return 0;
case 0:
case 8:
return 0;
case 16:
return 1;
case 32:
return 2;
case 64:
return 3;
case 128:
return 4;
default:
return 0;
}
}
@ -775,24 +796,24 @@ static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
{
switch (BurstSize) {
case 1:
return 0;
case 2:
return 1;
case 4:
return 2;
case 8:
return 3;
case 16:
return 4;
case 32:
return 5;
case 64:
return 6;
case 128:
return 7;
default:
return 0;
case 1:
return 0;
case 2:
return 1;
case 4:
return 2;
case 8:
return 3;
case 16:
return 4;
case 32:
return 5;
case 64:
return 6;
case 128:
return 7;
default:
return 0;
}
}
@ -835,7 +856,7 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
| ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
| ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
@ -843,21 +864,21 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
| ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
| ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
u32 ccr_value = (es << 28)
| (dst_cache_ctrl << 25)
| (dst_prot_ctrl << 22)
| (dst_burst_len << 18)
| (dst_burst_size << 15)
| (dst_inc_bit << 14)
| (src_cache_ctrl << 11)
| (src_prot_ctrl << 8)
| (src_burst_len << 4)
| (src_burst_size << 1)
| (src_inc_bit);
| (dst_cache_ctrl << 25)
| (dst_prot_ctrl << 22)
| (dst_burst_len << 18)
| (dst_burst_size << 15)
| (dst_inc_bit << 14)
| (src_cache_ctrl << 11)
| (src_prot_ctrl << 8)
| (src_burst_len << 4)
| (src_burst_size << 1)
| (src_inc_bit);
return ccr_value;
}
@ -883,9 +904,9 @@ u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
*
*****************************************************************************/
int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
int CacheLength,
char *DmaProgLoopStart,
int LoopCount)
int CacheLength,
char *DmaProgLoopStart,
int LoopCount)
{
int CacheStartOffset;
int CacheEndOffset;
@ -909,7 +930,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
!= CacheEndOffset / CacheLength) {
/* insert the nops */
NumNops = CacheLength
- CacheStartOffset % CacheLength;
- CacheStartOffset % CacheLength;
while (NumNops--) {
DmaProgBuf +=
XDmaPs_Instr_DMANOP(DmaProgBuf);
@ -920,7 +941,7 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
DmaProgBuf - 2, 0);
DmaProgBuf - 2, 0);
return DmaProgBuf - DmaProgLoopStart;
}
@ -948,10 +969,10 @@ int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
*
*****************************************************************************/
int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
int CacheLength,
char *DmaProgLoopStart,
unsigned int LoopCountOuter,
unsigned int LoopCountInner)
int CacheLength,
char *DmaProgLoopStart,
unsigned int LoopCountOuter,
unsigned int LoopCountInner)
{
int CacheStartOffset;
int CacheEndOffset;
@ -974,14 +995,14 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
*/
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCountInner);
CacheLength,
DmaProgBuf,
LoopCountInner);
/* outer loop end */
DmaProgBuf +=
XDmaPs_Instr_DMALPEND(DmaProgBuf,
InnerLoopStart,
1);
InnerLoopStart,
1);
/*
* the nested loop is constructed for
@ -1004,7 +1025,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
!= CacheEndOffset / CacheLength) {
/* insert the nops */
NumNops = CacheLength
- CacheStartOffset % CacheLength;
- CacheStartOffset % CacheLength;
while (NumNops--) {
DmaProgBuf +=
XDmaPs_Instr_DMANOP(DmaProgBuf);
@ -1021,10 +1042,10 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
/* inner DMALPEND */
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
DmaProgBuf - 2, 0);
DmaProgBuf - 2, 0);
/* outer DMALPEND */
DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
InnerLoopStart, 1);
InnerLoopStart, 1);
/* return the number of bytes */
return DmaProgBuf - DmaProgLoopStart;
@ -1066,7 +1087,7 @@ int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
*
*****************************************************************************/
static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
unsigned CacheLength)
unsigned CacheLength)
{
/*
* unpack arguments
@ -1118,18 +1139,20 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* insert DMAMOV for SAR and DAR */
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_SAR,
SrcAddr);
XDMAPS_MOV_SAR,
SrcAddr);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_DAR,
DstAddr);
XDMAPS_MOV_DAR,
DstAddr);
if (ChanCtrl->SrcInc)
if (ChanCtrl->SrcInc) {
SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
}
if (ChanCtrl->DstInc)
if (ChanCtrl->DstInc) {
DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
}
if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
ChanCtrl = &Mem2MemByteCC;
@ -1151,12 +1174,12 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* if head is unaligned, transfer head in bytes */
UnalignedCount = MemBurstSize - Unaligned;
CCRValue = XDMAPS_CCR_SINGLE_BYTE
| (SrcInc & 1)
| ((DstInc & 1) << 14);
| (SrcInc & 1)
| ((DstInc & 1) << 14);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
for (Index = 0; Index < UnalignedCount; Index++) {
DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
@ -1169,8 +1192,8 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
/* now the burst transfer part */
CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
@ -1196,16 +1219,16 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
if (LoopCount1 > 1)
DmaProgBuf +=
XDmaPs_ConstructNestedLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCount1,
256);
CacheLength,
DmaProgBuf,
LoopCount1,
256);
else
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
256);
CacheLength,
DmaProgBuf,
256);
/* there will be some that cannot be covered by
* nested loops
@ -1215,9 +1238,9 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
if (LoopCount > 0) {
DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
LoopCount);
CacheLength,
DmaProgBuf,
LoopCount);
}
if (TailBytes) {
@ -1244,13 +1267,13 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
DmaProgBuf +=
XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
TailWords);
CacheLength,
DmaProgBuf,
TailWords);
}
@ -1264,19 +1287,19 @@ static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
* to perform a burst.
*/
CCRValue = XDMAPS_CCR_SINGLE_BYTE
| (SrcInc & 1)
| ((DstInc & 1) << 14);
| (SrcInc & 1)
| ((DstInc & 1) << 14);
DmaProgBuf +=
XDmaPs_Instr_DMAMOV(DmaProgBuf,
XDMAPS_MOV_CCR,
CCRValue);
XDMAPS_MOV_CCR,
CCRValue);
DmaProgBuf +=
XDmaPs_ConstructSingleLoop(DmaProgStart,
CacheLength,
DmaProgBuf,
TailBytes);
CacheLength,
DmaProgBuf,
TailBytes);
}
}
@ -1322,8 +1345,9 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Xil_AssertNonvoid(Cmd != NULL);
if (Channel > XDMAPS_CHANNELS_PER_DEV)
if (Channel > XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
ChanData = InstPtr->Chans + Channel;
ChanCtrl = &Cmd->ChanCtrl;
@ -1352,7 +1376,7 @@ int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Cmd->GeneratedDmaProg = Buf;
ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
InstPtr->CacheLength);
InstPtr->CacheLength);
Cmd->GeneratedDmaProgLength = ProgLen;
@ -1396,8 +1420,9 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
Xil_AssertNonvoid(InstPtr != NULL);
Xil_AssertNonvoid(Cmd != NULL);
if (Channel > XDMAPS_CHANNELS_PER_DEV)
if (Channel > XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
Buf = (void *)Cmd->GeneratedDmaProg;
ChanData = InstPtr->Chans + Channel;
@ -1437,8 +1462,8 @@ int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
*
****************************************************************************/
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg)
XDmaPs_Cmd *Cmd,
int HoldDmaProg)
{
int Status;
u32 DmaProg = 0;
@ -1450,32 +1475,35 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
Cmd->DmaStatus = XST_FAILURE;
if (XDmaPs_IsActive(InstPtr, Channel))
if (XDmaPs_IsActive(InstPtr, Channel)) {
return XST_DEVICE_BUSY;
}
if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
if (Status)
if (Status) {
return XST_FAILURE;
}
}
InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
if (Cmd->UserDmaProg)
if (Cmd->UserDmaProg) {
DmaProg = (u32)Cmd->UserDmaProg;
else if (Cmd->GeneratedDmaProg)
} else if (Cmd->GeneratedDmaProg) {
DmaProg = (u32)Cmd->GeneratedDmaProg;
}
if (DmaProg) {
/* enable the interrupt */
Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET);
XDMAPS_INTEN_OFFSET);
Inten |= 0x01 << Channel; /* set the correpsonding bit */
XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET,
Inten);
XDMAPS_INTEN_OFFSET,
Inten);
Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
XDMAPS_INTEN_OFFSET);
XDMAPS_INTEN_OFFSET);
InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
@ -1484,13 +1512,12 @@ int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
}
if (Cmd->ChanCtrl.DstInc) {
Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
Cmd->BD.Length);
Cmd->BD.Length);
}
Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
Channel, DmaProg);
}
else {
Channel, DmaProg);
} else {
InstPtr->Chans[Channel].DmaCmdToHw = NULL;
Status = XST_FAILURE;
}
@ -1517,8 +1544,9 @@ int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
Xil_AssertNonvoid(InstPtr != NULL);
/* Need to assert Channel is in range */
if (Channel >= XDMAPS_CHANNELS_PER_DEV)
if (Channel >= XDMAPS_CHANNELS_PER_DEV) {
return XST_FAILURE;
}
return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
}
@ -1725,8 +1753,8 @@ void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
*
*****************************************************************************/
static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
unsigned int Channel,
unsigned int Thread)
unsigned int Channel,
unsigned int Thread)
{
u32 DbgInst0;
int WaitCount;
@ -1736,14 +1764,15 @@ static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
/* wait while debug status is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT))
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
}
if (WaitCount >= XDMAPS_MAX_WAIT) {
/* wait time out */
xil_printf("PL330 device at %x debug status busy time out\n",
BaseAddr);
BaseAddr);
return -1;
}
@ -1816,7 +1845,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
/* wait while debug status is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
@ -1837,7 +1866,7 @@ static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
/* wait while the DMA Manager is busy */
WaitCount = 0;
while ((XDmaPs_ReadReg(BaseAddr,
XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
!= XDMAPS_DS_DMA_STATUS_STOPPED
&& WaitCount <= XDMAPS_MAX_WAIT) {
WaitCount++;
@ -1896,7 +1925,7 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
if (DmaProgBuf)
XDmaPs_BufPool_Free(ChanData->ProgBufPool,
DmaProgBuf);
DmaProgBuf);
DmaCmd->GeneratedDmaProg = NULL;
}
@ -1925,8 +1954,9 @@ static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
{
int Index;
for (Index = 0; Index < Length; Index++)
for (Index = 0; Index < Length; Index++) {
xil_printf("[%x] %x\r\n", Index, Buf[Index]);
}
}
/****************************************************************************/
@ -1940,20 +1970,20 @@ static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
* @note None.
*
*****************************************************************************/
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
{
if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
xil_printf("Generated DMA program (%d):\r\n",
Cmd->GeneratedDmaProgLength);
XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
Cmd->GeneratedDmaProgLength);
Cmd->GeneratedDmaProgLength);
}
if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
xil_printf("User defined DMA program (%d):\r\n",
Cmd->UserDmaProgLength);
XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
Cmd->UserDmaProgLength);
Cmd->UserDmaProgLength);
}
}

56
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
* @details
*
@ -60,6 +61,7 @@
* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
* to static inline to avoid the linkage conflict for IAR compiler.
* 2.9 aj 11/07/23 Added support for system device tree
* </pre>
*
*****************************************************************************/
@ -88,8 +90,19 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of device (IPIF) */
#ifdef SDT
u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDmaPs_Config;
@ -169,15 +182,15 @@ typedef struct {
* It's the done handler a user can set for a channel
*/
typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
/**
* It's the fault handler a user can set for a channel
*/
typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
#define XDMAPS_MAX_CHAN_BUFS 2
#define XDMAPS_CHAN_BUF_LEN 128
@ -236,18 +249,18 @@ typedef struct {
* Functions implemented in xdmaps.c
*/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr);
XDmaPs_Config *Config,
u32 EffectiveAddr);
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
XDmaPs_Cmd *Cmd);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
@ -256,13 +269,13 @@ int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
int XDmaPs_Instr_DMARMB(char *DmaProg);
@ -276,10 +289,10 @@ int XDmaPs_Instr_DMAWMB(char *DmaProg);
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns);
u32 Imm, unsigned int Ns);
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations);
unsigned LoopIterations);
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
@ -312,7 +325,12 @@ void XDmaPs_FaultISR(XDmaPs *InstPtr);
/*
* Static loopup function implemented in xdmaps_sinit.c
*/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress);
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress);
#endif
/*

5
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_g.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains a configuration table where each entry is a configuration

36
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,10 +8,10 @@
/**
*
* @file xdmaps_hw.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the implementation of the interface reset functionality
* This file contains the implementation of the interface reset functionality
* for XDmaPs driver.
*
* <pre>
@ -40,10 +41,10 @@
/*****************************************************************************/
/**
* This function perform the reset sequence to the given dmaps interface by
* This function perform the reset sequence to the given dmaps interface by
* configuring the appropriate control bits in the dmaps specifc registers
* the dmaps reset squence involves the following steps
* Disable all the interuupts
* Disable all the interuupts
* Clear the pending interrupts
* Kill all the active channel threads
* Kill the manager thread
@ -52,8 +53,8 @@
*
* @return N/A
*
* @note
* This function will not modify the slcr registers that are relavant for
* @note
* This function will not modify the slcr registers that are relavant for
* dmaps controller
******************************************************************************/
void XDmaPs_ResetHw(u32 BaseAddress)
@ -67,22 +68,23 @@ void XDmaPs_ResetHw(u32 BaseAddress)
/* Clear the interrupts */
XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
/* Kill the dma channel threads */
for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
for (ChanIndex = 0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT))
WaitCount++;
& XDMAPS_DBGSTATUS_BUSY)
&& (WaitCount < XDMAPS_MAX_WAIT)) {
WaitCount++;
}
DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
}
}
/* Kill the manager thread */
DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
}

9
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_hw.h
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
@ -233,7 +234,7 @@ extern "C" {
#define XDMAPS_INTCLR_ALL_MASK 0xFF
#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
Xil_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
@ -251,7 +252,7 @@ extern "C" {
* u32 RegisterValue)
******************************************************************************/
#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes *****************************/

11
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xdmaps_selftest.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* This file contains the self-test functions for the XDmaPs driver.
@ -71,13 +72,15 @@ int XDmaPs_SelfTest(XDmaPs *InstPtr)
int i;
if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
& XDMAPS_DBGSTATUS_BUSY)
& XDMAPS_DBGSTATUS_BUSY) {
return XST_FAILURE;
}
for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
if (XDmaPs_ReadReg(BaseAddr,
XDmaPs_CSn_OFFSET(i)))
XDmaPs_CSn_OFFSET(i))) {
return XST_FAILURE;
}
}
return XST_SUCCESS;
}

40
bsp_z7/ps7_cortexa9_0/libsrc/dmaps/src/xdmaps_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,10 +8,10 @@
/**
*
* @file xdmaps_sinit.c
* @addtogroup dmaps_v2_8
* @addtogroup dmaps Overview
* @{
*
* The implementation of the XDmaPs driver's static initialzation
* The implementation of the XDmaPs driver's static initialization
* functionality.
*
* <pre>
@ -26,7 +27,9 @@
/***************************** Include Files ********************************/
#include "xstatus.h"
#ifndef SDT
#include "xparameters.h"
#endif
#include "xdmaps.h"
/************************** Constant Definitions ****************************/
@ -60,6 +63,7 @@ extern XDmaPs_Config XDmaPs_ConfigTable[];
* None.
*
******************************************************************************/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
{
XDmaPs_Config *CfgPtr = NULL;
@ -75,4 +79,34 @@ XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
return CfgPtr;
}
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress)
{
XDmaPs_Config *CfgPtr = NULL;
int i;
for (i = (u32)0x0; XDmaPs_ConfigTable[i].Name != NULL; i++) {
if ((XDmaPs_ConfigTable[i].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XDmaPs_ConfigTable[i];
break;
}
}
return CfgPtr;
}
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress)
{
u32 Index = 0;
for (Index = (u32)0x0; XDmaPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XDmaPs_ConfigTable[Index].BaseAddress == BaseAddress)) {
break;
}
}
return Index;
}
#endif
/** @} */

14
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* The XEmacPs driver. Functions in this file are the minimum required functions
@ -85,12 +86,21 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
Xil_AssertNonvoid(CfgPtr != NULL);
/* Set device base address and ID */
#ifndef SDT
InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
#endif
InstancePtr->Config.BaseAddress = EffectiveAddress;
InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
#ifdef SDT
InstancePtr->Config.IntrId = CfgPtr->IntrId;
InstancePtr->Config.IntrParent = CfgPtr->IntrParent;
#endif
#if defined (XCLOCKING)
InstancePtr->Config.RefClk = CfgPtr->RefClk;
#endif
#ifdef SDT
InstancePtr->Config.PhyType = CfgPtr->PhyType;
#endif
InstancePtr->Config.S1GDiv0 = CfgPtr->S1GDiv0;
InstancePtr->Config.S1GDiv1 = CfgPtr->S1GDiv1;

101
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
* @details
*
@ -417,15 +418,15 @@ extern "C" {
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
@ -456,11 +457,11 @@ extern "C" {
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
@ -500,7 +501,7 @@ typedef void (*XEmacPs_Handler) (void *CallBackRef);
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
u32 ErrorWord);
/*@}*/
@ -508,12 +509,25 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifdef SDT
char *Name; /**< Unique name of the device */
#else
u16 DeviceId; /**< Unique ID of device */
#endif
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#if defined (XCLOCKING)
#ifdef SDT
u16 IntrId;
UINTPTR IntrParent;
#endif
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clock */
#endif
#ifdef SDT
char *PhyType; /**< PhyType indicates which type of PHY interface is
* used (MII, GMII, RGMII, etc.
*/
#endif
u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
@ -606,8 +620,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -627,8 +641,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -648,8 +662,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -669,8 +683,8 @@ typedef struct XEmacPs_Instance {
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
@ -687,10 +701,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
@ -711,9 +725,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
@ -734,9 +748,9 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
@ -761,10 +775,10 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
/****************************************************************************/
/**
@ -781,8 +795,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_GetRXWatermark(InstancePtr) \
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
/*
* Initialization functions in xemacps.c
*/
@ -797,7 +811,12 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
/*
* Lookup configuration in xemacps_sinit.c
*/
#ifndef SDT
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
#else
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Interrupt-related functions in xemacps_intr.c
@ -823,7 +842,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,

10
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bd.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bd.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header provides operations to manage buffer descriptors in support
@ -45,6 +46,7 @@
* 3.2 hk 11/18/15 Change BD typedef and number of words.
* 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
* 3.9 aj 22/03/24 Add mask for XEmaPs_BdGetBufAddr
*
* </pre>
*
@ -239,11 +241,11 @@ typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & XEMACPS_RXBUF_ADD_MASK)
#endif
/*****************************************************************************/

16
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bdring.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file implements buffer descriptor ring related functions.
@ -676,12 +677,13 @@ u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
BdPartialCount = 0U;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
/* Reached the end of the work group */
if (CurBdPtr == RingPtr->HwTail) {
break;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
}
/* Subtract off any partial packet BDs found */
@ -822,13 +824,13 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
BdPartialCount++;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
/* Reached the end of the work group */
if (CurBdPtr == RingPtr->HwTail) {
break;
}
/* Move on to next BD in work group */
CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
}
/* Subtract off any partial packet BDs found */

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_bdring.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_control.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_control.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* Functions in this file implement general purpose command and control related

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_g.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains a configuration table that specifies the configuration of

5
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_hw.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains the implementation of the ethernet interface reset sequence

2
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_hw.h
View File

@ -8,7 +8,7 @@
/**
*
* @file xemacps_hw.h
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or

7
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_intr.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_intr.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* Functions in this file implement general purpose interrupt processing related
@ -228,7 +229,7 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
/* Transmit error conditions interrupt */
if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
(!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
((!(RegISR & XEMACPS_IXR_TXCOMPL_MASK)) != 0x00000000U)) {
/* Clear TX status register */
RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
XEMACPS_TXSR_OFFSET);

28
bsp_z7/ps7_cortexa9_0/libsrc/emacps/src/xemacps_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xemacps_sinit.c
* @addtogroup emacps_v3_16
* @addtogroup emacps Overview
* @{
*
* This file contains lookup method by device ID when success, it returns
@ -27,7 +28,9 @@
/***************************** Include Files *********************************/
#include "xemacps.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -35,7 +38,11 @@
/**************************** Type Definitions *******************************/
/*************************** Variable Definitions *****************************/
#ifdef SDT
extern XEmacPs_Config XEmacPs_ConfigTable[];
#else
extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
#endif
/***************** Macros (Inline Functions) Definitions *********************/
@ -54,6 +61,22 @@ extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
* device ID, or NULL if no match is found.
*
******************************************************************************/
#ifdef SDT
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress)
{
XEmacPs_Config *CfgPtr = NULL;
u32 Index;
/* Checks all the instances */
for (Index = (u32)0x0; XEmacPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XEmacPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XEmacPs_ConfigTable[Index];
break;
}
}
return (XEmacPs_Config *)(CfgPtr);
}
#else
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
{
XEmacPs_Config *CfgPtr = NULL;
@ -68,4 +91,5 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
return (XEmacPs_Config *)(CfgPtr);
}
#endif
/** @} */

8
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -35,6 +35,9 @@
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/13/19 Added Versal support.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Added multi-core interrupt support.
*
* </pre>
*
******************************************************************************/
@ -89,7 +92,9 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
*/
InstancePtr->IsReady = 0U;
InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
#ifndef SDT
InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
#endif
InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
InstancePtr->Platform = XGetPlatform_Info();
@ -176,6 +181,7 @@ s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
}
InstancePtr->CoreIntrMask[i] = 0;
}
/* Indicate the component is now ready to use. */

33
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -124,6 +124,11 @@
* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
* 3.9 sne 03/15/21 Fixed MISRA-C violations.
* 3.11 sg 02/23/23 Update bank and pin mapping information.
* 3.12 gm 07/11/23 Added SDT support.
* 3.13 gm 03/15/24 Remove const of XGpioPs InstancePtr from function proto
* type of XGpioPs_IntrEnable, XGpioPs_IntrDisable,
* XGpioPs_IntrEnablePin and XGpioPs_IntrDisablePin
* to add multi-core interrupt support.
*
* </pre>
*
@ -167,6 +172,7 @@ extern "C" {
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS_CNT 0x06U /**< Max banks number of all platforms */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
@ -209,8 +215,18 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XGpioPs_Config;
/**
@ -227,6 +243,7 @@ typedef struct {
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
u32 CoreIntrMask[XGPIOPS_MAX_BANKS_CNT]; /**< Interrupt mask per core */
} XGpioPs;
/************************** Variable Definitions *****************************/
@ -262,12 +279,12 @@ void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnabl
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
@ -283,14 +300,18 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_g.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

2
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

36
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_intr.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -35,6 +35,7 @@
* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
* 3.13 gm 03/15/24 Added multi-core interrupt support.
*
* </pre>
*
@ -71,7 +72,7 @@
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -87,6 +88,9 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, Mask);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] |= Mask;
}
/****************************************************************************/
@ -102,7 +106,7 @@ void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
@ -123,6 +127,9 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTEN_OFFSET, IntrReg);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] |= IntrReg;
}
/****************************************************************************/
@ -142,7 +149,7 @@ void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -158,6 +165,9 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, Mask);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] &= ~Mask;
}
/****************************************************************************/
@ -173,7 +183,7 @@ void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
{
u8 Bank;
u8 PinNumber;
@ -194,6 +204,9 @@ void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTDIS_OFFSET, IntrReg);
/* Setup mask for CPU */
InstancePtr->CoreIntrMask[Bank] &= ~IntrReg;
}
/****************************************************************************/
@ -735,6 +748,7 @@ void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
{
u8 Bank;
u32 Mask;
u32 IntrStatus;
u32 IntrEnabled;
@ -755,12 +769,12 @@ void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
#endif
IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
if ((IntrStatus & IntrEnabled) != (u32)0) {
XGpioPs_IntrClear(InstancePtr, Bank,
(IntrStatus & IntrEnabled));
InstancePtr->Handler(InstancePtr->
CallBackRef, Bank,
(IntrStatus & IntrEnabled));
Mask = IntrStatus & IntrEnabled & InstancePtr->CoreIntrMask[Bank];
if (Mask != (u32)0)
{
XGpioPs_IntrClear(InstancePtr, Bank, Mask);
InstancePtr->Handler(InstancePtr->CallBackRef, Bank, Mask);
}
}
}

4
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_selftest.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -61,7 +61,7 @@
*
*
******************************************************************************/
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
{
s32 Status = (s32)0;
u32 IntrEnabled;

22
bsp_z7/ps7_cortexa9_0/libsrc/gpiops/src/xgpiops_sinit.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -24,6 +24,8 @@
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.12 gm 07/11/23 Added SDT support.
*
* </pre>
*
******************************************************************************/
@ -57,6 +59,7 @@
* @note None.
*
******************************************************************************/
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
{
XGpioPs_Config *CfgPtr = NULL;
@ -71,4 +74,21 @@ XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
return (XGpioPs_Config *)CfgPtr;
}
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress)
{
XGpioPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = (u32)0x0; XGpioPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XGpioPs_ConfigTable[Index].BaseAddr == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XGpioPs_ConfigTable[Index];
break;
}
}
return (XGpioPs_Config *)CfgPtr;
}
#endif
/** @} */

417
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* Contains implements the interface functions of the XQspiPs driver.
@ -117,7 +118,7 @@ typedef struct {
/************************** Function Prototypes ******************************/
static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
unsigned ByteCount);
/************************** Variable Definitions *****************************/
@ -191,7 +192,7 @@ static XQspiPsInstFormat FlashInst[] = {
*
******************************************************************************/
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
u32 EffectiveAddr)
u32 EffectiveAddr)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
@ -265,11 +266,11 @@ void XQspiPs_Reset(XQspiPs *InstancePtr)
* Do not modify reserved bits.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
ConfigReg);
ConfigReg);
}
/*****************************************************************************/
@ -299,7 +300,7 @@ void XQspiPs_Abort(XQspiPs *InstancePtr)
* De-assert slave select lines.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
@ -310,24 +311,24 @@ void XQspiPs_Abort(XQspiPs *InstancePtr)
IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
if (IsLock) {
XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
SLCR_UNLOCK_MASK);
SLCR_UNLOCK_MASK);
}
XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
LQSPI_RST_CTRL_MASK);
LQSPI_RST_CTRL_MASK);
XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
if (IsLock) {
XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
SLCR_LOCK_MASK);
SLCR_LOCK_MASK);
}
/*
* Set the RX and TX FIFO threshold to reset value (one)
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
InstancePtr->RemainingBytes = 0;
InstancePtr->RequestedBytes = 0;
@ -400,7 +401,7 @@ void XQspiPs_Abort(XQspiPs *InstancePtr)
*
******************************************************************************/
s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount)
u32 ByteCount)
{
u32 StatusReg;
u32 ConfigReg;
@ -460,7 +461,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* Set the RX FIFO threshold
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
/*
* If the slave select is "Forced" or under manual control,
@ -468,11 +469,11 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET,
ConfigReg);
XQSPIPS_CR_OFFSET,
ConfigReg);
}
/*
@ -484,7 +485,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* Clear all the interrupts.
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
XQSPIPS_IXR_WR_TO_CLR_MASK);
XQSPIPS_IXR_WR_TO_CLR_MASK);
if (Index < ARRAY_SIZE(FlashInst)) {
CurrInst = &FlashInst[Index];
@ -493,7 +494,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* Spansion (3 bytes) and Micron (2 bytes)
*/
if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
(ByteCount == 3)) {
(ByteCount == 3)) {
CurrInst->InstSize = 3;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
}
@ -511,36 +512,36 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* The remaining bytes of the instruction will be transmitted
* through TXD0 below.
*/
switch (ByteCount%4) {
case XQSPIPS_SIZE_ONE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_ONE;
CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_TWO:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_TWO;
CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_THREE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_THREE;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
default:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
break;
switch (ByteCount % 4) {
case XQSPIPS_SIZE_ONE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_ONE;
CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_TWO:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_TWO;
CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_THREE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_THREE;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
default:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
break;
}
}
@ -577,8 +578,8 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
*/
if (XQspiPs_IsManualStart(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
@ -588,8 +589,8 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
*/
do {
StatusReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
}
@ -599,15 +600,15 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* we have to send).
*/
while ((InstancePtr->RemainingBytes > 0) &&
(TransCount < XQSPIPS_FIFO_DEPTH)) {
(TransCount < XQSPIPS_FIFO_DEPTH)) {
/*
* In case of Write fill the Tx FIFO with data to be transmitted.
* In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
* of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
* with DUMMY.
*/
if(InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
if (InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
} else {
@ -629,19 +630,19 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
* enabling interrupts should have been done by the caller).
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
XQSPIPS_IXR_TXUF_MASK);
XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
XQSPIPS_IXR_TXUF_MASK);
/*
* If, in Manual Start mode, Start the transfer.
*/
if (XQspiPs_IsManualStart(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
}
return XST_SUCCESS;
@ -701,7 +702,7 @@ s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
*
******************************************************************************/
s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount)
u8 *RecvBufPtr, u32 ByteCount)
{
u32 StatusReg;
u32 ConfigReg;
@ -762,7 +763,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* Set the RX FIFO threshold
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
/*
* If the slave select is "Forced" or under manual control,
@ -770,11 +771,11 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET,
ConfigReg);
XQSPIPS_CR_OFFSET,
ConfigReg);
}
/*
@ -790,7 +791,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* Spansion (3 bytes) and Micron (2 bytes)
*/
if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
(ByteCount == 3)) {
(ByteCount == 3)) {
CurrInst->InstSize = 3;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
}
@ -808,35 +809,35 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* through TXD0 below.
*/
switch (ByteCount % 4) {
case XQSPIPS_SIZE_ONE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_ONE;
CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_TWO:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_TWO;
CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_THREE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_THREE;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
default:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
break;
case XQSPIPS_SIZE_ONE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_ONE;
CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_TWO:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_TWO;
CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
case XQSPIPS_SIZE_THREE:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_THREE;
CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
if (ByteCount > 4) {
SwitchFlag = 1;
}
break;
default:
CurrInst->OpCode = Instruction;
CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
break;
}
}
@ -860,7 +861,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
/* Write the command to the FIFO */
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
CurrInst->TxOffset, Data);
CurrInst->TxOffset, Data);
++TransCount;
/*
@ -873,8 +874,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*/
if (XQspiPs_IsManualStart(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
@ -884,8 +885,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*/
do {
StatusReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
}
@ -901,15 +902,15 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* many as we have to send).
*/
while ((InstancePtr->RemainingBytes > 0) &&
(TransCount < XQSPIPS_FIFO_DEPTH)) {
(TransCount < XQSPIPS_FIFO_DEPTH)) {
/*
* In case of Write fill the Tx FIFO with data to be transmitted.
* In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
* of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
* with DUMMY.
*/
if(InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
if (InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
} else {
@ -927,22 +928,22 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
}
while ((InstancePtr->RemainingBytes > 0) ||
(InstancePtr->RequestedBytes > 0)) {
(InstancePtr->RequestedBytes > 0)) {
/*
* Fill the TX FIFO with RX threshold no. of entries (or as
* many as we have to send, in case that's less).
*/
while ((InstancePtr->RemainingBytes > 0) &&
(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
/*
* In case of Write fill the Tx FIFO with data to be transmitted.
* In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
* of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
* with DUMMY.
*/
if(InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
if (InstancePtr->RecvBufferPtr &&
((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
} else {
@ -964,8 +965,8 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*/
if (IsManualStart == TRUE) {
ConfigReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
@ -988,10 +989,10 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
do {
StatusReg = XQspiPs_ReadReg(
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
InstancePtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
} while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
/*
* A transmit has just completed. Process received data
@ -1004,7 +1005,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* software may not care to receive data).
*/
while ((InstancePtr->RequestedBytes > 0) &&
(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
u32 Data;
RxCount++;
@ -1012,13 +1013,13 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
if (InstancePtr->RecvBufferPtr != NULL) {
if (InstancePtr->RequestedBytes < 4) {
Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXD_OFFSET);
XQSPIPS_RXD_OFFSET);
XQspiPs_GetReadData(InstancePtr, Data,
InstancePtr->RequestedBytes);
InstancePtr->RequestedBytes);
} else {
(*(u32 *)InstancePtr->RecvBufferPtr) =
XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXD_OFFSET);
XQSPIPS_RXD_OFFSET);
InstancePtr->RecvBufferPtr += 4;
InstancePtr->RequestedBytes -= 4;
if (InstancePtr->RequestedBytes < 0) {
@ -1027,7 +1028,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
}
} else {
Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXD_OFFSET);
XQSPIPS_RXD_OFFSET);
InstancePtr->RequestedBytes -= 4;
}
}
@ -1040,10 +1041,10 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
}
/*
@ -1060,7 +1061,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
* Reset the RX FIFO threshold to one
*/
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
return XST_SUCCESS;
}
@ -1085,7 +1086,7 @@ s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
*
******************************************************************************/
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
u32 Address, unsigned ByteCount)
u32 Address, unsigned ByteCount)
{
int Status = (int)XST_SUCCESS;
Xil_AssertNonvoid(InstancePtr != NULL);
@ -1102,11 +1103,11 @@ int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
XQspiPs_Enable(InstancePtr);
if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
XQSPIPS_LQSPI_CR_LINEAR_MASK) {
XQSPIPS_LQSPI_CR_LINEAR_MASK) {
memcpy((void *)RecvBufPtr,
(const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
Address),
(size_t)ByteCount);
(const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
Address),
(size_t)ByteCount);
Status = (int)XST_SUCCESS;
} else {
Status = (int)XST_FAILURE;
@ -1160,10 +1161,10 @@ int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
* Select the slave
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
return XST_SUCCESS;
}
@ -1206,7 +1207,7 @@ int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
*
******************************************************************************/
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
XQspiPs_StatusHandler FuncPtr)
XQspiPs_StatusHandler FuncPtr)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(FuncPtr != NULL);
@ -1233,7 +1234,7 @@ void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
*
******************************************************************************/
static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
unsigned ByteCount)
unsigned ByteCount)
{
(void) CallBackRef;
(void) StatusEvent;
@ -1298,15 +1299,15 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* TX_EMPTY interrupt.
*/
IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
XQSPIPS_SR_OFFSET);
XQSPIPS_SR_OFFSET);
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
(IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
(IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
/*
* Rx FIFO has just reached threshold no. of entries.
@ -1320,24 +1321,24 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
*/
TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
if (TransCount % 4) {
TransCount = TransCount/4 + 1;
TransCount = TransCount / 4 + 1;
} else {
TransCount = TransCount/4;
TransCount = TransCount / 4;
}
while ((Count < TransCount) &&
(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
if (QspiPtr->RecvBufferPtr != NULL) {
if (QspiPtr->RequestedBytes < 4) {
Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
XQSPIPS_RXD_OFFSET);
XQSPIPS_RXD_OFFSET);
XQspiPs_GetReadData(QspiPtr, Data,
QspiPtr->RequestedBytes);
QspiPtr->RequestedBytes);
} else {
(*(u32 *)QspiPtr->RecvBufferPtr) =
XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
XQSPIPS_RXD_OFFSET);
XQSPIPS_RXD_OFFSET);
QspiPtr->RecvBufferPtr += 4;
QspiPtr->RequestedBytes -= 4;
if (QspiPtr->RequestedBytes < 0) {
@ -1363,7 +1364,7 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* remaining entries (in case that is less than threshold)
*/
while ((QspiPtr->RemainingBytes > 0) &&
(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
/*
* Send more data.
* In case of Write fill the Tx FIFO with data to be transmitted.
@ -1371,8 +1372,8 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
* with DUMMY.
*/
if(QspiPtr->RecvBufferPtr &&
((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) {
if (QspiPtr->RecvBufferPtr &&
((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) {
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
} else {
@ -1391,7 +1392,7 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
}
if ((QspiPtr->RemainingBytes == 0) &&
(QspiPtr->RequestedBytes == 0)) {
(QspiPtr->RequestedBytes == 0)) {
/*
* No more data to send. Disable the interrupt
* and inform the upper layer software that the
@ -1399,11 +1400,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* when another transfer is initiated.
*/
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_IDR_OFFSET,
XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_TXOW_MASK |
XQSPIPS_IXR_RXOVR_MASK |
XQSPIPS_IXR_TXUF_MASK);
XQSPIPS_IDR_OFFSET,
XQSPIPS_IXR_RXNEMPTY_MASK |
XQSPIPS_IXR_TXOW_MASK |
XQSPIPS_IXR_RXOVR_MASK |
XQSPIPS_IXR_TXUF_MASK);
/*
* If the Slave select is being manually controlled,
@ -1411,12 +1412,12 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET,
ConfigReg);
XQSPIPS_CR_OFFSET,
ConfigReg);
}
/*
@ -1433,11 +1434,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* Reset the RX FIFO threshold to one
*/
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
QspiPtr->StatusHandler(QspiPtr->StatusRef,
XST_SPI_TRANSFER_DONE,
QspiPtr->RequestedBytes);
XST_SPI_TRANSFER_DONE,
QspiPtr->RequestedBytes);
} else {
/*
* Enable the TXOW interrupt.
@ -1453,12 +1454,12 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
*/
if (XQspiPs_IsManualStart(QspiPtr)) {
ConfigReg = XQspiPs_ReadReg(
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
XQspiPs_WriteReg(
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
}
}
}
@ -1476,11 +1477,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
}
/*
@ -1492,10 +1493,10 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* Reset the RX FIFO threshold to one
*/
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
QspiPtr->StatusHandler(QspiPtr->StatusRef,
XST_SPI_RECEIVE_OVERRUN, BytesDone);
XST_SPI_RECEIVE_OVERRUN, BytesDone);
}
if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
@ -1508,11 +1509,11 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
*/
if (XQspiPs_IsManualChipSelect(InstancePtr)) {
ConfigReg = XQspiPs_ReadReg(
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET, ConfigReg);
XQSPIPS_CR_OFFSET, ConfigReg);
}
/*
@ -1524,10 +1525,10 @@ void XQspiPs_InterruptHandler(void *InstancePtr)
* Reset the RX FIFO threshold to one
*/
XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
QspiPtr->StatusHandler(QspiPtr->StatusRef,
XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
}
}
@ -1552,46 +1553,46 @@ static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
if (InstancePtr->RecvBufferPtr) {
switch (Size) {
case 1:
if (InstancePtr->ShiftReadData == 1) {
*((u8 *)InstancePtr->RecvBufferPtr) =
((Data & 0xFF000000) >> 24);
} else {
*((u8 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFF);
}
InstancePtr->RecvBufferPtr += 1;
break;
case 2:
if (InstancePtr->ShiftReadData == 1) {
*((u16 *)InstancePtr->RecvBufferPtr) =
((Data >> 16) & 0xFF00) |
((Data >> 8) & 0xFF);
} else {
*((u16 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFFFF);
}
InstancePtr->RecvBufferPtr += 2;
break;
case 3:
if (InstancePtr->ShiftReadData == 1) {
*((u16 *)InstancePtr->RecvBufferPtr) =
((Data & 0x00FFFF00) >> 8);
case 1:
if (InstancePtr->ShiftReadData == 1) {
*((u8 *)InstancePtr->RecvBufferPtr) =
((Data & 0xFF000000) >> 24);
} else {
*((u8 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFF);
}
InstancePtr->RecvBufferPtr += 1;
break;
case 2:
if (InstancePtr->ShiftReadData == 1) {
*((u16 *)InstancePtr->RecvBufferPtr) =
((Data >> 16) & 0xFF00) |
((Data >> 8) & 0xFF);
} else {
*((u16 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFFFF);
}
InstancePtr->RecvBufferPtr += 2;
DataByte3 = ((Data & 0xFF000000) >> 24);
*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
} else {
*((u16 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFFFF);
InstancePtr->RecvBufferPtr += 2;
DataByte3 = ((Data & 0x00FF0000) >> 16);
*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
}
InstancePtr->RecvBufferPtr += 1;
break;
default:
/* This will never execute */
break;
break;
case 3:
if (InstancePtr->ShiftReadData == 1) {
*((u16 *)InstancePtr->RecvBufferPtr) =
((Data & 0x00FFFF00) >> 8);
InstancePtr->RecvBufferPtr += 2;
DataByte3 = ((Data & 0xFF000000) >> 24);
*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
} else {
*((u16 *)InstancePtr->RecvBufferPtr) =
(Data & 0xFFFF);
InstancePtr->RecvBufferPtr += 2;
DataByte3 = ((Data & 0x00FF0000) >> 16);
*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
}
InstancePtr->RecvBufferPtr += 1;
break;
default:
/* This will never execute */
break;
}
}
InstancePtr->ShiftReadData = 0;

59
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips.h
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
* @details
*
@ -270,6 +271,8 @@
* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
* data when RX buffer is not NULL.
* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow.
* 3.12 sb 02/20/24 Add missing parenthesis for macro expansions.
*
* </pre>
*
@ -478,16 +481,26 @@ extern "C" {
* requested if the status event indicates an error.
*/
typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
unsigned ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
#ifdef SDT
u32 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XQspiPs_Config;
/**
@ -571,7 +584,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET, (RegisterValue))
XQSPIPS_SICR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -589,7 +602,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_GetSlaveIdle(InstancePtr) \
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET)
XQSPIPS_SICR_OFFSET)
/****************************************************************************/
/**
@ -608,7 +621,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_TXWR_OFFSET, (RegisterValue))
XQSPIPS_TXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -625,7 +638,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetTXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
@ -644,7 +657,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_RXWR_OFFSET, (RegisterValue))
XQSPIPS_RXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -661,7 +674,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetRXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
@ -677,8 +690,8 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_Enable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
/**
@ -694,7 +707,7 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_Disable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
/****************************************************************************/
/**
@ -714,7 +727,7 @@ typedef struct {
*****************************************************************************/
#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
@ -731,35 +744,39 @@ typedef struct {
*
*****************************************************************************/
#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
/************************** Function Prototypes ******************************/
/*
* Initialization function, implemented in xqspips_sinit.c
*/
#ifndef SDT
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
#else
XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Functions implemented in xqspips.c
*/
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
u32 EffectiveAddr);
u32 EffectiveAddr);
void XQspiPs_Reset(XQspiPs *InstancePtr);
void XQspiPs_Abort(XQspiPs *InstancePtr);
s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount);
u32 ByteCount);
s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount);
u8 *RecvBufPtr, u32 ByteCount);
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
u32 Address, unsigned ByteCount);
u32 Address, unsigned ByteCount);
int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
XQspiPs_StatusHandler FuncPtr);
XQspiPs_StatusHandler FuncPtr);
void XQspiPs_InterruptHandler(void *InstancePtr);
/*
@ -777,9 +794,9 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
u8 DelayAfter, u8 DelayInit);
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
u8 *DelayAfter, u8 *DelayInit);
#ifdef __cplusplus
}
#endif

3
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_g.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* This file contains a configuration table that specifies the configuration of

37
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_hw.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* Contains low level functions, primarily reset related.
@ -71,13 +72,13 @@ void XQspiPs_ResetHw(u32 BaseAddress)
* Disable interrupts
*/
XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
XQSPIPS_IXR_DISABLE_ALL);
XQSPIPS_IXR_DISABLE_ALL);
/*
* Disable device
*/
XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
0);
0);
/*
* De-assert slave select lines.
@ -92,14 +93,14 @@ void XQspiPs_ResetHw(u32 BaseAddress)
* status bit is used next to clear the RXFIFO
*/
XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
/*
* Clear RXFIFO
*/
while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
while ((XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET) &
XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
}
@ -110,7 +111,7 @@ void XQspiPs_ResetHw(u32 BaseAddress)
*/
XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
XQSPIPS_IXR_WR_TO_CLR_MASK);
XQSPIPS_IXR_WR_TO_CLR_MASK);
/*
* Write default value to configuration register
@ -124,7 +125,7 @@ void XQspiPs_ResetHw(u32 BaseAddress)
* De-select linear mode
*/
XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
0x0);
0x0);
}
@ -166,33 +167,33 @@ void XQspiPs_LinearInit(u32 BaseAddress)
* enable linear mode and use fast read.
*/
if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
if (XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE) {
LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
XQSPIPS_CONNECTION_MODE_STACKED){
} else if (XPAR_XQSPIPS_0_QSPI_MODE ==
XQSPIPS_CONNECTION_MODE_STACKED) {
LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
XQSPIPS_CONNECTION_MODE_PARALLEL){
} else if (XPAR_XQSPIPS_0_QSPI_MODE ==
XQSPIPS_CONNECTION_MODE_PARALLEL) {
LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
}
XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
LinearCfg);
LinearCfg);
/*
* Enable device
*/
XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
XQSPIPS_ER_ENABLE_MASK);
XQSPIPS_ER_ENABLE_MASK);
}
/** @} */

25
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_hw.h
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* This header file contains the identifiers and basic HW access driver
@ -117,18 +118,18 @@ extern "C" {
/* Deselect the Slave select line and set the transfer size to 32 at reset */
#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
XQSPIPS_CR_SSCTRL_MASK | \
XQSPIPS_CR_DATA_SZ_MASK | \
XQSPIPS_CR_MSTREN_MASK | \
XQSPIPS_CR_SSFORCE_MASK | \
XQSPIPS_CR_HOLD_B_MASK
XQSPIPS_CR_SSCTRL_MASK | \
XQSPIPS_CR_DATA_SZ_MASK | \
XQSPIPS_CR_MSTREN_MASK | \
XQSPIPS_CR_SSFORCE_MASK | \
XQSPIPS_CR_HOLD_B_MASK
#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
XQSPIPS_CR_CPHA_MASK | \
XQSPIPS_CR_PRESC_MASK | \
XQSPIPS_CR_MANSTRTEN_MASK | \
XQSPIPS_CR_MANSTRT_MASK | \
XQSPIPS_CR_ENDIAN_MASK | \
XQSPIPS_CR_REF_CLK_MASK
XQSPIPS_CR_CPHA_MASK | \
XQSPIPS_CR_PRESC_MASK | \
XQSPIPS_CR_MANSTRTEN_MASK | \
XQSPIPS_CR_MANSTRT_MASK | \
XQSPIPS_CR_ENDIAN_MASK | \
XQSPIPS_CR_REF_CLK_MASK
/* @} */

37
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_options.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_options.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* Contains functions for the configuration of the XQspiPs driver component.
@ -116,7 +117,7 @@ s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
/*
* Loop through the options table, turning the option on or off
@ -143,18 +144,18 @@ s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
* Check for the LQSPI configuration options.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_LQSPI_CR_OFFSET);
XQSPIPS_LQSPI_CR_OFFSET);
if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_LQSPI_CR_OFFSET,
XQSPIPS_LQSPI_CR_RST_STATE);
XQSPIPS_LQSPI_CR_OFFSET,
XQSPIPS_LQSPI_CR_RST_STATE);
XQspiPs_SetSlaveSelect(InstancePtr);
} else {
ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
}
return XST_SUCCESS;
@ -190,7 +191,7 @@ u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
* Get the current options from QSPI configuration register.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
/*
* Loop through the options table to grab options
@ -205,7 +206,7 @@ u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
* Check for the LQSPI configuration options.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_LQSPI_CR_OFFSET);
XQSPIPS_LQSPI_CR_OFFSET);
if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
@ -257,15 +258,15 @@ s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
* results back to the configuration register.
*/
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
XQSPIPS_CR_PRESC_SHIFT;
XQSPIPS_CR_PRESC_SHIFT;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET,
ConfigReg);
XQSPIPS_CR_OFFSET,
ConfigReg);
return XST_SUCCESS;
}
@ -291,7 +292,7 @@ u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_CR_OFFSET);
XQSPIPS_CR_OFFSET);
ConfigReg &= XQSPIPS_CR_PRESC_MASK;
@ -330,7 +331,7 @@ u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
*
******************************************************************************/
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit)
u8 DelayAfter, u8 DelayInit)
{
u32 DelayRegister;
@ -352,7 +353,7 @@ int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
DelayRegister |= (u32) DelayInit;
XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
XQSPIPS_DR_OFFSET, DelayRegister);
XQSPIPS_DR_OFFSET, DelayRegister);
return XST_SUCCESS;
}
@ -380,7 +381,7 @@ int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
*
******************************************************************************/
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit)
u8 *DelayAfter, u8 *DelayInit)
{
u32 DelayRegister;
@ -388,7 +389,7 @@ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
XQSPIPS_DR_OFFSET);
XQSPIPS_DR_OFFSET);
*DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
@ -399,6 +400,6 @@ void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
XQSPIPS_DR_BTWN_SHIFT);
*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
XQSPIPS_DR_NSS_SHIFT);
XQSPIPS_DR_NSS_SHIFT);
}
/** @} */

9
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_selftest.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* This file contains the implementation of selftest function for the QSPI
@ -86,15 +87,15 @@ int XQspiPs_SelfTest(XQspiPs *InstancePtr)
* hardware out there.
*/
Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
DelayTestAfter, DelayTestInit);
DelayTestAfter, DelayTestInit);
if (Status != XST_SUCCESS) {
return Status;
}
XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
&DelayTestAfter, &DelayTestInit);
&DelayTestAfter, &DelayTestInit);
if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
return XST_REGISTER_ERROR;
}

23
bsp_z7/ps7_cortexa9_0/libsrc/qspips/src/xqspips_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xqspips_sinit.c
* @addtogroup qspips_v3_10
* @addtogroup qspips Overview
* @{
*
* The implementation of the XQspiPs component's static initialization
@ -19,6 +20,7 @@
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00 sdm 11/25/10 First release
* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow.
* </pre>
*
******************************************************************************/
@ -27,7 +29,9 @@
#include "xstatus.h"
#include "xqspips.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -58,6 +62,7 @@ extern XQspiPs_Config XQspiPs_ConfigTable[];
* @note None.
*
******************************************************************************/
#ifndef SDT
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
{
XQspiPs_Config *CfgPtr = NULL;
@ -71,4 +76,20 @@ XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
}
return CfgPtr;
}
#else
XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress)
{
XQspiPs_Config *CfgPtr = NULL;
int Index;
for (Index = 0U; XQspiPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XQspiPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XQspiPs_ConfigTable[Index];
break;
}
}
return CfgPtr;
}
#endif
/** @} */

726
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.c
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File diff suppressed because it is too large Load Diff

239
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,56 +8,10 @@
/**
*
* @file xscugic.h
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
* @details
*
* The generic interrupt controller driver component.
*
* The interrupt controller driver uses the idea of priority for the various
* handlers. Priority is an integer within the range of 1 and 31 inclusive with
* default of 1 being the highest priority interrupt source. The priorities
* of the various sources can be dynamically altered as needed through
* hardware configuration.
*
* The generic interrupt controller supports the following
* features:
*
* - specific individual interrupt enabling/disabling
* - specific individual interrupt acknowledging
* - attaching specific callback function to handle interrupt source
* - assigning desired priority to interrupt source if default is not
* acceptable.
*
* Details about connecting the interrupt handler of the driver are contained
* in the source file specific to interrupt processing, xscugic_intr.c.
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads
* or thread mutual exclusion, virtual memory, or cache control must be
* satisfied by the layer above this driver.
*
* <b>Interrupt Vector Tables</b>
*
* The device ID of the interrupt controller device is used by the driver as a
* direct index into the configuration data table. The user should populate the
* vector table with handlers and callbacks at run-time using the
* XScuGic_Connect() and XScuGic_Disconnect() functions.
*
* Each vector table entry corresponds to a device that can generate an
* interrupt. Each entry contains an interrupt handler function and an
* argument to be passed to the handler when an interrupt occurs. The
* user must use XScuGic_Connect() when the interrupt handler takes an
* argument other than the base address.
*
* <b>Nested Interrupts Processing</b>
*
* Nested interrupts are not supported by this driver.
*
* NOTE:
* The generic interrupt controller is not a part of the snoop control unit
* as indicated by the prefix "scu" in the name of the driver.
* It is an independent module in APU.
*
* <pre>
* MODIFICATION HISTORY:
@ -190,12 +144,14 @@
* executed, redistributor address will be stored in newly
* added member of XScuGic data structure "RedistBaseAddr".
* It fixes CR#1150432.
* 5.2 ml 03/02/23 Add description to fix Doxygen warnings.
* 5.2 adk 04/14/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_H /* prevent circular inclusions */
#define XSCUGIC_H /* by using protection macros */
#ifndef XSCUGIC_H /**< prevent circular inclusions */
#define XSCUGIC_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -212,13 +168,23 @@ extern "C" {
/************************** Constant Definitions *****************************/
/**
* @name EFUSE status Register information
* EFUSE Status Register
* @{
*/
#define EFUSE_STATUS_OFFSET 0x10
#define EFUSE_STATUS_CPU_MASK 0x80
#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
#define ARMA9
#define ARMA9 /**< ARMA9 macro to identify cortexA9 */
#endif
/**
* @name GICD_CTLR Register information
* GICD_CTLR Status Register
* @{
*/
#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
@ -245,8 +211,12 @@ extern "C" {
*/
typedef struct
{
Xil_InterruptHandler Handler;
void *CallBackRef;
Xil_InterruptHandler Handler; /**< Interrupt Handler */
void *CallBackRef; /**< CallBackRef is the callback reference passed in
by the upper layer when setting the Interrupt
handler for specific interrupt ID, and it will
passed back to Interrupt handler when it is
invoked. */
} XScuGic_VectorTableEntry;
/**
@ -254,9 +224,15 @@ typedef struct
*/
typedef struct
{
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 CpuBaseAddress; /**< CPU Interface Register base address */
u32 DistBaseAddress; /**< Distributor Register base address */
#else
char *Name; /**< Compatible string */
u32 DistBaseAddress; /**< Distributor Register base address */
u32 CpuBaseAddress; /**< CPU Interface Register base address */
#endif
XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
Vector table of interrupt handlers */
} XScuGic_Config;
@ -285,17 +261,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given CPU Interface register
* Writes the given CPU Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
@ -305,16 +280,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given CPU Interface register
* Reads the given CPU Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Rregister offset to be read.
*
* @return The 32-bit value of the register
* @return 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
@ -323,17 +297,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given Distributor Interface register
* Writes the given Distributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
@ -343,16 +316,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given Distributor Interface register
* Reads the given Distributor Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
* @return The 32-bit value of the register.
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
@ -362,17 +334,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given ReDistributor Interface register
* Writes the given ReDistributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
@ -381,16 +352,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given ReDistributor Interface register
* Reads the given ReDistributor Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
* @return 32-bit value of the register.
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
@ -399,17 +369,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Write the given ReDistributor SGI PPI Interface register
* Writes the given ReDistributor SGI PPI Interface register.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be written.
* @param Data 32-bit value to write to the register.
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
@ -419,16 +388,15 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
*
* Read the given ReDistributor SGI PPI Interface register
* Reads the given ReDistributor SGI PPI Interface register
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param RegOffset is the register offset to be read
* @param InstancePtr Pointer to the instance to be worked on.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
@ -443,9 +411,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#define XREG_ICC_SGI1R_EL1 "p15, 0, %0, %1, c12"
#define XREG_ICC_PMR_EL1 "p15, 0, %0, c4, c6, 0"
#define XREG_ICC_IAR0_EL1 "p15, 0, %0, c12, c8, 0"
#define XREG_ICC_IAR1_EL1 "p15, 0, %0, c12, c12, 0"
#define XREG_ICC_EOIR0_EL1 "p15, 0, %0, c12, c8, 1"
#define XREG_ICC_EOIR1_EL1 "p15, 0, %0, c12, c12, 1"
#define XREG_IMP_CBAR "p15, 1, %0, c15, c3, 0"
#define XREG_ICC_BPR0_EL1 "p15, 0, %0, c12, c8, 3"
#define XREG_ICC_BPR1_EL1 "p15, 0, %0, c12, c12, 3"
#define XREG_ICC_RPR_EL1 "p15, 0, %0, c12, c11, 3"
#else
#define XREG_ICC_SRE_EL1 "S3_0_C12_C12_5"
@ -463,13 +434,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function enables system register interface for GIC CPU Interface
* Enables system register interface for GIC CPU Interface.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (__aarch64__)
@ -480,13 +450,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function enables Grou0 interrupts
* Enable Grou0 interrupts.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -502,7 +471,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -518,13 +486,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function writes to ICC_SGI0R_EL1
* Writes to ICC_SGI0R_EL1.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -535,13 +502,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
* This function writes to ICC_SGI1R_EL1
* Writes to ICC_SGI1R_EL1.
*
* @param value to be written
* @param value Value to be written.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
@ -552,13 +518,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
/****************************************************************************/
/**
* This function reads ICC_SGI1R_EL1 register
* Reads ICC_SGI1R_EL1 register.
*
* @param None
*
* @return Value of ICC_SGI1R_EL1 register
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -568,13 +533,12 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function sets interrupt priority filter
* Sets interrupt priority filter.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined (ARMR52)
@ -584,17 +548,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function returns interrupt id of highest priority pending interrupt
* Returns interrupt ID of highest priority pending interrupt.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR0_EL1)
#define XScuGic_get_IntID() mfcp(XREG_ICC_IAR1_EL1)
#elif EL3
#define XScuGic_get_IntID() mfcpnotoken(XREG_ICC_IAR0_EL1)
#else
@ -602,17 +565,16 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
#endif
/****************************************************************************/
/**
* This function acks the interrupt
* Acknowledges the interrupt.
*
* @param None.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#if defined(ARMR52)
#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR0_EL1,val)
#define XScuGic_ack_Int(val) mtcp(XREG_ICC_EOIR1_EL1,val)
#elif EL3
#define XScuGic_ack_Int(val) mtcpnotoken(XREG_ICC_EOIR0_EL1,val)
#else
@ -627,7 +589,6 @@ extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) ((Int_Id%16) * 2U)
@ -660,12 +621,23 @@ void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
void XScuGic_Stop(XScuGic *InstancePtr);
void XScuGic_SetCpuID(u32 CpuCoreId);
u32 XScuGic_GetCpuID(void);
#ifndef SDT
u8 XScuGic_IsInitialized(u32 DeviceId);
#else
u8 XScuGic_IsInitialized(u32 BaseAddress);
#endif
#ifndef SDT
/*
* Initialization functions in xscugic_sinit.c
* Lookup configuration by using DeviceId
*/
XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
/*
* Lookup configuration by using BaseAddress
*/
XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress);
#else
XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddr);
#endif
/*
* Interrupt functions in xscugic_intr.c
@ -685,5 +657,6 @@ void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
}
#endif
#endif /* end of protection macro */
#endif
/* end of protection macro */
/** @} */

6
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_g.c
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@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,10 +8,10 @@
/**
*
* @file xscugic_g.c
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* This file contains a configuration table that specifies the configuration of
* The xscugic_g.c file contains a configuration table that specifies the configuration of
* interrupt controller devices in the system.
*
* <pre>

547
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.c
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134
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_hw.h
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@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,11 +8,11 @@
/**
*
* @file xscugic_hw.h
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* This header file contains identifiers and HW access functions (or
* macros) that can be used to access the device. The user should refer to the
* The xscugic_hw.h header file contains identifiers and hardware access functions (or
* macros) that can be used to access the device. The user should refer to the
* hardware device specification for more details of the device operation.
* The driver functions/APIs are defined in xscugic.h.
*
@ -69,13 +69,14 @@
* based address for specific CPU core. Also, added new macro
* XScuGic_ReadReg64 to read 64 bit value from specific address.
* 5.1 mus 02/15/23 Added support for VERSAL_NET APU and RPU GIC.
*
* 5.2 ml 03/02/23 Add description to fix Doxygen warnings.
* 5.2 mus 03/26/23 Fixed calculation for XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC.
* </pre>
*
******************************************************************************/
#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
#define XSCUGIC_HW_H /* by using protection macros */
#ifndef XSCUGIC_HW_H /**< prevent circular inclusions */
#define XSCUGIC_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -110,24 +111,31 @@ extern "C" {
* The maximum number of interrupts supported by the hardware.
*/
#ifdef PLATFORM_ZYNQ
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /**< Maximum number of
interrupt defined by
Zynq */
#elif defined (VERSAL_NET)
#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /* Maximum number of interrupt sources in VERSAL NET */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 256U /**< Maximum number of
interrupt sources in
VERSAL NET */
#elif defined (versal)
#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U /**< Maximum number of
interrupt sources in
VERSAL */
#else
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /**< Maximum number of
interrupt defined by
Zynq Ultrascale Mp */
#endif
/*
* First Interrupt Id for SPI interrupts.
*/
#define XSCUGIC_SPI_INT_ID_START 0x20U
/*
* The maximum priority value that can be used in the GIC.
*/
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
#define XSCUGIC_SPI_INT_ID_START 0x20U /**< First Interrupt Id for
SPI interrupts. */
#define XSCUGIC_MAX_INTR_PRIO_VAL 248U /**< The maximum priority value
that can be used in
the GIC. */
#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U /**< The Interrupt
priority mask value */
/** @name Distributor Interface Register Map
*
@ -338,7 +346,7 @@ extern "C" {
* There are up to 255 of these registers staring at location 0xC08.
* @{
*/
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< Interrupt configuration Mask */
/* @} */
/** @name PPI Status Register
@ -523,6 +531,7 @@ extern "C" {
#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
#define XSCUGIC_RDIST_TYPER_OFFSET 0x8U
@ -535,7 +544,7 @@ extern "C" {
/*
* GICR_IGROUPR register definitions
*/
#if (defined(ARMR52) || EL3)
#if EL3
#define XSCUGIC_DEFAULT_SECURITY 0x0U
#else
#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
@ -551,13 +560,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Configuration Register offset for an interrupt id.
* Reads the Interrupt Configuration Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
@ -566,13 +574,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Priority Register offset for an interrupt id.
* Reads the Interrupt Priority Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
@ -581,13 +588,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Interrupt Routing Register offset for an interrupt id.
* Reads the Interrupt Routing Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
@ -596,13 +602,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the SPI Target Register offset for an interrupt id.
* Reads the SPI Target Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
* @return The 32-bit value of the offset.
*
* @note
*
*****************************************************************************/
#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
@ -610,13 +615,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the SPI Target Register offset for an interrupt id.
* Reads the SPI Target Register offset for an interrupt ID.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
@ -625,13 +629,12 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Re-distributor Interrupt configuration register offset
* Reads the Re-distributor Interrupt configuration register offset.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
@ -640,28 +643,26 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the Re-distributor Interrupt Priority register offset
* Reads the Re-distributor Interrupt Priority register offset.
*
* @param InterruptID is the interrupt number.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + ((InterruptID/4) * 4))
/****************************************************************************/
/**
*
* Read the Interrupt Clear-Enable Register offset for an interrupt ID
* Reads the Interrupt Clear-Enable Register offset for an interrupt ID.
*
* @param Register is the register offset for the clear/enable bank.
* @param InterruptID is the interrupt number.
* @param Register Register offset for the clear/enable bank.
* @param InterruptID Interrupt number.
*
* @return The 32-bit value of the offset
*
* @note
*
*****************************************************************************/
#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
@ -670,16 +671,15 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the given Intc register.
* Reads the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be read
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be read.
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg(BaseAddress, RegOffset) \
@ -688,16 +688,15 @@ extern "C" {
/****************************************************************************/
/**
*
* Read the given Intc register.
* Reads the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be read
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be read.
*
* @return The 64-bit value of the register
*
* @note
* C-style signature:
* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset)
* @note C-style signature:
* u32 XScuGic_ReadReg64(UINTPTR BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XScuGic_ReadReg64(BaseAddress, RegOffset) \
@ -706,17 +705,16 @@ extern "C" {
/****************************************************************************/
/**
*
* Write the given Intc register.
* Writes the given Intc register.
*
* @param BaseAddress is the base address of the device.
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
* @param BaseAddress Base address of the device.
* @param RegOffset Register offset to be written
* @param Data 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
* @note C-style signature:
* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \

25
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_intr.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,22 +8,22 @@
/**
*
* @file xscugic_intr.c
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* This file contains the interrupt processing for the driver for the Xilinx
* Interrupt Controller. The interrupt processing is partitioned separately such
* that users are not required to use the provided interrupt processing. This
* The xscugic_intr.c file contains the interrupt processing for the driver for the
* Interrupt Controller. The interrupt processing is partitioned separately such
* that users are not required to use the provided interrupt processing. This
* file requires other files of the driver to be linked in also.
*
* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
* The interrupt handler XScuGic_InterruptHandler uses an input argument which
* is an instance pointer to an interrupt controller driver such that multiple
* interrupt controllers can be supported. This handler requires the calling
* interrupt controllers can be supported. This handler requires the calling
* function to pass it the appropriate argument, so another level of indirection
* may be required.
* can be required.
*
* The interrupt processing may be used by connecting the interrupt handler to
* the interrupt system. The handler does not save and restore the processor
* The interrupt processing is used by connecting the interrupt handler to
* the interrupt system. The handler does not save and restore the processor
* context but only handles the processing of the Interrupt Controller. The user
* is encouraged to supply their own interrupt handler when performance tuning is
* deemed necessary.
@ -49,7 +49,7 @@
* This driver assumes that the context of the processor has been saved prior to
* the calling of the Interrupt Controller interrupt handler and then restored
* after the handler returns. This requires either the running RTOS to save the
* state of the machine or that a wrapper be used as the destination of the
* state of the machine or a wrapper be used as the destination of the
* interrupt vector to save the state of the processor and restore the state
* after the interrupt handler returns.
*
@ -85,11 +85,10 @@
* calling an interrupt handler.
*
*
* @param InstancePtr is a pointer to the XScuGic instance.
* @param InstancePtr Pointer to the XScuGic instance.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XScuGic_InterruptHandler(XScuGic *InstancePtr)

25
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_selftest.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,10 +8,12 @@
/**
*
* @file xscugic_selftest.c
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* Contains diagnostic self-test functions for the XScuGic driver.
* The xscugic_selftest.c file contains diagnostic self-test functions for the XScuGic driver.
*
*
* <pre>
* MODIFICATION HISTORY:
*
@ -21,7 +23,8 @@
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
* reported by checkpatch. It fixes CR#1006344.
*
* 5.2 ml 03/02/23 Add description to fix Doxygen warnings.
* 5.2 ml 09/07/23 Added comments to fix HIS COMF violations.
* </pre>
*
******************************************************************************/
@ -34,7 +37,7 @@
/************************** Constant Definitions *****************************/
#define XSCUGIC_PCELL_ID 0xB105F00DU
#define XSCUGIC_PCELL_ID 0xB105F00DU /**< PCELL ID value */
/**************************** Type Definitions *******************************/
@ -49,17 +52,16 @@
/*****************************************************************************/
/**
*
* Run a self-test on the driver/device. This test reads the ID registers and
* Runs a self-test on the driver/device. This test reads the ID registers and
* compares them.
*
* @param InstancePtr is a pointer to the XScuGic instance.
* @param InstancePtr Pointer to the XScuGic instance.
*
* @return
*
* -XST_SUCCESS if self-test is successful.
* -XST_FAILURE if the self-test is not successful.
*
* @note None.
*
******************************************************************************/
s32 XScuGic_SelfTest(XScuGic *InstancePtr)
@ -69,7 +71,7 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr)
s32 Status;
/*
* Assert the arguments
* Validate the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@ -79,8 +81,8 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr)
*/
for (Index = 0U; Index <= 3U; Index++) {
RegValue1 |= XScuGic_DistReadReg(InstancePtr,
((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
(Index * 8U);
((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
(Index * 8U);
}
if (XSCUGIC_PCELL_ID != RegValue1) {
@ -88,6 +90,7 @@ s32 XScuGic_SelfTest(XScuGic *InstancePtr)
} else {
Status = XST_SUCCESS;
}
/* Return statement */
return Status;
}
/** @} */

83
bsp_z7/ps7_cortexa9_0/libsrc/scugic/src/xscugic_sinit.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,11 +8,11 @@
/**
*
* @file xscugic_sinit.c
* @addtogroup scugic Overview
* @addtogroup scugic_api SCUGIC APIs
* @{
*
* Contains static init functions for the XScuGic driver for the Interrupt
* Controller. See xscugic.h for a detailed description of the driver.
* The xscugic_sinit.c contains static init functions for the XScuGic driver for the Interrupt
* Controller.
*
* <pre>
* MODIFICATION HISTORY:
@ -25,7 +25,8 @@
* reported by checkpatch. It fixes CR#1006344.
* 4.6 sk 08/05/21 Remove XScuGic_Config variable definition to fix
* misrac violation.
*
* 5.2 ml 03/03/23 Add description to fix Doxygen warnings.
* 5.2 ml 09/07/23 Added comments to fix HIS COMF violations.
* </pre>
*
******************************************************************************/
@ -34,8 +35,10 @@
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xscugic.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -56,40 +59,82 @@
* Looks up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId is the unique identifier for a device.
* @param DeviceId Unique identifier for a device.
*
* @return A pointer to the XScuGic configuration structure for the
* specified device, or NULL if the device was not found.
* specified device, or NULL if the device is not found.
*
* @note None.
*
******************************************************************************/
#ifndef SDT
XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
{
XScuGic_Config *CfgPtr = NULL;
u32 Index;
/*
* checks the device Id in configuration table
* whether it matches or not
*/
for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XScuGic_ConfigTable[Index];
break;
}
}
/* Return statement */
return (XScuGic_Config *)CfgPtr;
}
/*****************************************************************************/
/**
*
* Looks up the device configuration based on the BaseAddress. The return value
* will refer to an entry in the device configuration table defined in the
* xscugic_g.c file.
*
* @param BaseAddress Base address of the device.
*
* @return A pointer to the XScuGic configuration structure for the
* specified device, or NULL if the device is not found.
*
*
******************************************************************************/
XScuGic_Config *XScuGic_LookupConfigBaseAddr(UINTPTR BaseAddress)
{
XScuGic_Config *CfgPtr = NULL;
u32 Index;
XScuGic_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
if (XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) {
CfgPtr = &XScuGic_ConfigTable[Index];
break;
}
}
return (XScuGic_Config *)CfgPtr;
/*
* checks the BaseAddress in configuration table
* whether it matches or not
*/
for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
if (XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) {
CfgPtr = &XScuGic_ConfigTable[Index];
break;
}
}
/* Return statement */
return (XScuGic_Config *)CfgPtr;
}
#else
XScuGic_Config *XScuGic_LookupConfig(UINTPTR BaseAddress)
{
XScuGic_Config *CfgPtr = NULL;
u32 Index;
/* checks the BaseAddress in configuration table
* whether it matches or not
*/
for (Index = 0U; XScuGic_ConfigTable[Index].Name != NULL; Index++) {
if ((XScuGic_ConfigTable[Index].DistBaseAddress == BaseAddress) || !BaseAddress) {
CfgPtr = &XScuGic_ConfigTable[Index];
break;
}
}
/* Return statement */
return (XScuGic_Config *)CfgPtr;
}
#endif
/** @} */

27
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer.c
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* Contains the implementation of interface functions of the SCU Timer driver.
@ -20,6 +21,7 @@
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* 2.5 dp 07/11/23 Add Support for system device tree flow
* </pre>
*
******************************************************************************/
@ -58,7 +60,7 @@
*
******************************************************************************/
s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
{
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
@ -74,7 +76,9 @@ s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
/*
* Copy configuration into the instance structure.
*/
#ifndef SDT
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
#endif
/*
* Save the base address pointer such that the registers of the block
@ -93,9 +97,8 @@ s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
InstancePtr->Config.IntrParent = ConfigPtr->IntrParent;
#endif
Status =(s32)XST_SUCCESS;
}
else {
Status = (s32)XST_SUCCESS;
} else {
Status = (s32)XST_DEVICE_IS_STARTED;
}
return Status;
@ -124,7 +127,7 @@ void XScuTimer_Start(XScuTimer *InstancePtr)
* Read the contents of the Control register.
*/
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
XSCUTIMER_CONTROL_OFFSET);
/*
* Set the 'timer enable' bit in the register.
@ -135,7 +138,7 @@ void XScuTimer_Start(XScuTimer *InstancePtr)
* Update the Control register with the new value.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Indicate that the device is started.
@ -166,7 +169,7 @@ void XScuTimer_Stop(XScuTimer *InstancePtr)
* Read the contents of the Control register.
*/
Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
XSCUTIMER_CONTROL_OFFSET);
/*
* Clear the 'timer enable' bit in the register.
@ -177,7 +180,7 @@ void XScuTimer_Stop(XScuTimer *InstancePtr)
* Update the Control register with the new value.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Indicate that the device is stopped.
@ -211,7 +214,7 @@ void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
* Read the Timer control register.
*/
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
XSCUTIMER_CONTROL_OFFSET);
/*
* Clear all of the prescaler control bits in the register.
@ -227,7 +230,7 @@ void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
* Write the register with the new values.
*/
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, ControlReg);
XSCUTIMER_CONTROL_OFFSET, ControlReg);
}
/*****************************************************************************/
@ -256,7 +259,7 @@ u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
* Read the Timer control register.
*/
ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
XSCUTIMER_CONTROL_OFFSET);
ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);

62
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer.h
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
* @details
*
@ -82,6 +83,7 @@
* 2.3 mus 08/31/20 Updated makefile to support parallel make and
* incremental builds, it would help to reduce compilation
* time.
* 2.5 dp 07/11/23 Add support for system device tree flow
* </pre>
*
******************************************************************************/
@ -106,7 +108,11 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef XIL_INTERRUPT
u32 IntrId;
@ -145,9 +151,9 @@ typedef struct {
******************************************************************************/
#define XScuTimer_IsExpired(InstancePtr) \
((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET) & \
XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
XSCUTIMER_ISR_EVENT_FLAG_MASK)
XSCUTIMER_ISR_OFFSET) & \
XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
XSCUTIMER_ISR_EVENT_FLAG_MASK)
/****************************************************************************/
/**
@ -165,8 +171,8 @@ typedef struct {
******************************************************************************/
#define XScuTimer_RestartTimer(InstancePtr) \
XScuTimer_LoadTimer((InstancePtr), \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET))
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET))
/****************************************************************************/
/**
@ -186,7 +192,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_LoadTimer(InstancePtr, Value) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_LOAD_OFFSET, (Value))
XSCUTIMER_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
@ -204,7 +210,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_GetCounterValue(InstancePtr) \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_COUNTER_OFFSET)
XSCUTIMER_COUNTER_OFFSET)
/****************************************************************************/
/**
@ -221,10 +227,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_EnableAutoReload(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
/****************************************************************************/
/**
@ -241,10 +247,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_DisableAutoReload(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
/****************************************************************************/
/**
@ -261,10 +267,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_EnableInterrupt(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) | \
XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
/****************************************************************************/
/**
@ -281,10 +287,10 @@ typedef struct {
******************************************************************************/
#define XScuTimer_DisableInterrupt(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
XSCUTIMER_CONTROL_OFFSET, \
(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_CONTROL_OFFSET) & \
~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
/*****************************************************************************/
/**
@ -301,7 +307,7 @@ typedef struct {
******************************************************************************/
#define XScuTimer_GetInterruptStatus(InstancePtr) \
XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET)
XSCUTIMER_ISR_OFFSET)
/*****************************************************************************/
/**
@ -318,14 +324,18 @@ typedef struct {
******************************************************************************/
#define XScuTimer_ClearInterruptStatus(InstancePtr) \
XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
/************************** Function Prototypes ******************************/
/*
* Lookup configuration in xscutimer_sinit.c
*/
#ifndef SDT
XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
#else
XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr);
#endif
/*
* Selftest function in xscutimer_selftest.c

3
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer_g.c
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* This file contains a table that specifies the configuration of the SCU

3
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer_hw.h
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* This file contains the hardware interface to the Timer.

16
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer_selftest.c
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* Contains diagnostic self-test functions for the XScuTimer driver.
@ -74,10 +75,10 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
* Save the contents of the Control Register and stop the timer.
*/
CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET);
XSCUTIMER_CONTROL_OFFSET);
Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, Register);
XSCUTIMER_CONTROL_OFFSET, Register);
/*
* Save the contents of the Load Register.
@ -85,17 +86,17 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
* compare it with the written value.
*/
LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUTIMER_LOAD_OFFSET);
XSCUTIMER_LOAD_OFFSET);
XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
XSCUTIMER_LOAD_OFFSET);
XSCUTIMER_LOAD_OFFSET);
/*
* Restore the contents of the Load Register and Control Register.
*/
XScuTimer_LoadTimer(InstancePtr, LoadOrig);
XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
/*
* Return a Failure if the contents of the Load Register do not
@ -103,8 +104,7 @@ s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
*/
if (Register != XSCUTIMER_SELFTEST_VALUE) {
Status = (s32)XST_FAILURE;
}
else {
} else {
Status = (s32)XST_SUCCESS;
}

27
bsp_z7/ps7_cortexa9_0/libsrc/scutimer/src/xscutimer_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscutimer_sinit.c
* @addtogroup scutimer_v2_4
* @addtogroup scutimer Overview
* @{
*
* This file contains method for static initialization (compile-time) of the
@ -20,6 +21,7 @@
* ----- --- -------- ---------------------------------------------
* 1.00a nm 03/10/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* 2.5 dp 07/11/23 Add Support for system device tree flow
* </pre>
*
******************************************************************************/
@ -27,7 +29,9 @@
/***************************** Include Files *********************************/
#include "xscutimer.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -36,7 +40,11 @@
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions ****************************/
#ifndef SDT
extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
#else
extern XScuTimer_Config XScuTimer_ConfigTable[];
#endif
/************************** Function Prototypes ******************************/
@ -53,6 +61,7 @@ extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
* @note None.
*
******************************************************************************/
#ifndef SDT
XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
{
XScuTimer_Config *CfgPtr = NULL;
@ -67,4 +76,20 @@ XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
return (XScuTimer_Config *)CfgPtr;
}
#else
XScuTimer_Config *XScuTimer_LookupConfig(UINTPTR BaseAddr)
{
XScuTimer_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; XScuTimer_ConfigTable[Index].Name != NULL; Index++) {
if (XScuTimer_ConfigTable[Index].BaseAddr == BaseAddr) {
CfgPtr = &XScuTimer_ConfigTable[Index];
break;
}
}
return (XScuTimer_Config *)CfgPtr;
}
#endif
/** @} */

23
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt.c
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* Contains the implementation of interface functions of the XScuWdt driver.
@ -20,6 +21,7 @@
* ----- --- -------- ---------------------------------------------
* 1.00a sdm 01/15/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* 2.5 asa 07/18/23 Made updates for workflow decoupling flow.
* </pre>
*
******************************************************************************/
@ -58,7 +60,7 @@
*
******************************************************************************/
s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
{
s32 CfgStatus;
Xil_AssertNonvoid(InstancePtr != NULL);
@ -73,12 +75,13 @@ s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
*/
if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
CfgStatus = (s32)XST_DEVICE_IS_STARTED;
}
else {
} else {
/*
* Copy configuration into instance.
*/
#ifndef SDT
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
#endif
/*
* Save the base address pointer such that the registers of the block
@ -97,7 +100,7 @@ s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
*/
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
CfgStatus =(s32)XST_SUCCESS;
CfgStatus = (s32)XST_SUCCESS;
}
return CfgStatus;
}
@ -128,7 +131,7 @@ void XScuWdt_Start(XScuWdt *InstancePtr)
* Read the contents of the Control register.
*/
Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
XSCUWDT_CONTROL_OFFSET);
XSCUWDT_CONTROL_OFFSET);
/*
* Set the 'watchdog enable' bit in the register.
@ -139,7 +142,7 @@ void XScuWdt_Start(XScuWdt *InstancePtr)
* Update the Control register with the new value.
*/
XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
XSCUWDT_CONTROL_OFFSET, Register);
XSCUWDT_CONTROL_OFFSET, Register);
/*
* Indicate that the device is started.
@ -170,7 +173,7 @@ void XScuWdt_Stop(XScuWdt *InstancePtr)
* Read the contents of the Control register.
*/
Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
XSCUWDT_CONTROL_OFFSET);
XSCUWDT_CONTROL_OFFSET);
/*
* Clear the 'watchdog enable' bit in the register.
@ -181,7 +184,7 @@ void XScuWdt_Stop(XScuWdt *InstancePtr)
* Update the Control register with the new value.
*/
XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
XSCUWDT_CONTROL_OFFSET, Register);
XSCUWDT_CONTROL_OFFSET, Register);
/*
* Indicate that the device is stopped.

49
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt.h
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
* @details
*
@ -106,6 +107,8 @@
* time.
* 2.3 sne 09/16/20 Fixed MISRA-C violations.
* 2.4 sne 02/04/21 Fixed Doxygen warnings.
* 2.5 asa 07/18/23 Added support for system device tree based workflow
* decoupling flow.
* </pre>
*
******************************************************************************/
@ -129,8 +132,18 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddr; /**< Base address of the device */
#else
char *Name; /**< Unique name of the device */
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XScuWdt_Config;
/**
@ -168,7 +181,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_IsWdtExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_RST_STS_OFFSET) & \
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
/****************************************************************************/
/**
@ -189,7 +202,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_IsTimerExpired(InstancePtr) \
((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_ISR_OFFSET) & \
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
/****************************************************************************/
/**
@ -230,7 +243,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
******************************************************************************/
#define XScuWdt_LoadWdt(InstancePtr, Value) \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_LOAD_OFFSET, (Value))
XSCUWDT_LOAD_OFFSET, (Value))
/****************************************************************************/
/**
@ -250,7 +263,7 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET, \
(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_CONTROL_OFFSET) | \
XSCUWDT_CONTROL_OFFSET) | \
(XSCUWDT_CONTROL_WD_MODE_MASK)))
/****************************************************************************/
@ -271,14 +284,14 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
*
******************************************************************************/
#define XScuWdt_SetTimerMode(InstancePtr) \
{ \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE1); \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE2); \
}
{ \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE1); \
XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
XSCUWDT_DISABLE_OFFSET, \
XSCUWDT_DISABLE_VALUE2); \
}
/****************************************************************************/
/**
@ -332,14 +345,18 @@ extern XScuWdt_Config XScuWdt_ConfigTable[];
#define XScuWdt_EnableAutoReload(InstancePtr) \
XScuWdt_SetControlReg((InstancePtr), \
(XScuWdt_GetControlReg(InstancePtr) | \
XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
/************************** Function Prototypes ******************************/
/*
* Lookup configuration in xscuwdt_sinit.c.
*/
#ifndef SDT
XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
#else
XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xscuwdt_selftest.c

5
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_g.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt_g.c
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* This file contains a table that specifies the configuration of the SCU

5
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_hw.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt_hw.h
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* This file contains the hardware interface to the Xilinx SCU private Watch Dog

8
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_selftest.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt_selftest.c
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* Contains diagnostic self-test functions for the XScuWdt driver.
@ -95,8 +96,7 @@ s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
if (Register == 0xFFFFFFFFU) {
SelfTestStatus = (s32)XST_FAILURE;
}
else {
} else {
SelfTestStatus = (s32)XST_SUCCESS;
}

28
bsp_z7/ps7_cortexa9_0/libsrc/scuwdt/src/xscuwdt_sinit.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -7,7 +8,7 @@
/**
*
* @file xscuwdt_sinit.c
* @addtogroup scuwdt_v2_4
* @addtogroup Overview
* @{
*
* This file contains method for static initialization (compile-time) of the
@ -20,6 +21,8 @@
* ----- --- -------- ---------------------------------------------
* 1.00a sdm 01/15/10 First release
* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
* 2.5 asa 07/18/23 Made updates to support system device tree based
* workflow decoupling flow.
* </pre>
*
******************************************************************************/
@ -27,6 +30,9 @@
/***************************** Include Files *********************************/
#include "xscuwdt.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
@ -49,6 +55,7 @@
* @note None.
*
******************************************************************************/
#ifndef SDT
XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
{
XScuWdt_Config *CfgPtr = NULL;
@ -63,4 +70,21 @@ XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
return (XScuWdt_Config *)CfgPtr;
}
#else
XScuWdt_Config *XScuWdt_LookupConfig(UINTPTR BaseAddress)
{
XScuWdt_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; XScuWdt_ConfigTable[Index].Name != NULL; Index++) {
if ((XScuWdt_ConfigTable[Index].BaseAddr == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XScuWdt_ConfigTable[Index];
break;
}
}
return (XScuWdt_Config *)CfgPtr;
}
#endif
/** @} */

128
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +8,7 @@
/**
*
* @file xsdps.c
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* Contains the interface functions of the XSdPs driver.
@ -90,6 +90,8 @@
* 4.0 sk 02/25/22 Add support for eMMC5.1.
* sk 04/07/22 Add support to read custom tap delay values from design
* for SD/eMMC.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
* 4.3 ap 11/29/23 Add support for Sanitize feature.
*
* </pre>
*
@ -109,21 +111,21 @@
/**
*
* @brief
* Initializes a specific XSdPs instance such that the driver is ready to use.
* Initializes a specific XSdPs instance so that the driver is ready to use.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param ConfigPtr is a reference to a structure containing information
* @param InstancePtr Pointer to the XSdPs instance.
* @param ConfigPtr Reference to a structure containing information
* about a specific SD device. This function initializes an
* InstancePtr object for a specific device specified by the
* contents of Config.
* @param EffectiveAddr is the device base address in the virtual memory
* contents of Configuration.
* @param EffectiveAddr Device base address in the virtual memory
* address space. The caller is responsible for keeping the address
* mapping from EffectiveAddr to the device physical base address
* unchanged once this function is invoked. Unexpected errors may
* occur if the address mapping changes after this function is
* called. If address translation is not used, use
* ConfigPtr->Config.BaseAddress for this device.
* ConfigPtr->Config. BaseAddress for this device.
*
* @return
* - XST_SUCCESS if successful.
@ -131,15 +133,15 @@
* It must be stopped to re-initialize.
*
* @note This function initializes the host controller.
* Initial clock of 400KHz is set.
* Voltage of 3.3V is selected as that is supported by host.
* Initial clock of 400 KHz is set.
* Voltage of 3.3 V is selected as that is supported by host.
* Interrupts status is enabled and signal disabled by default.
* Default data direction is card to host and
* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
*
******************************************************************************/
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr)
UINTPTR EffectiveAddr)
{
s32 Status;
@ -157,7 +159,9 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
}
/* Set some default values. */
#ifndef SDT
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
#endif
InstancePtr->Config.BaseAddress = EffectiveAddr;
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
@ -173,6 +177,7 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
InstancePtr->Config.OTapDly_DDR_Clk50 = ConfigPtr->OTapDly_DDR_Clk50;
InstancePtr->Config.OTapDly_SDR_Clk100 = ConfigPtr->OTapDly_SDR_Clk100;
InstancePtr->Config.OTapDly_SDR_Clk200 = ConfigPtr->OTapDly_SDR_Clk200;
InstancePtr->Config.OTapDly_DDR_Clk200 = ConfigPtr->OTapDly_DDR_Clk200;
InstancePtr->SectorCount = 0U;
InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
InstancePtr->OTapDelay = 0U;
@ -185,15 +190,15 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
/* Host Controller version is read. */
InstancePtr->HC_Version =
(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
/*
* Read capabilities register and update it in Instance pointer.
* It is sufficient to read this once on power on.
*/
InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_CAPS_OFFSET);
XSDPS_CAPS_OFFSET);
/* Reset the SD bus lines */
Status = XSdPs_ResetConfig(InstancePtr);
@ -219,10 +224,10 @@ RETURN_PATH:
/**
*
* @brief
* Initialize Card with Identification mode sequence
* Initializes Card with Identification mode sequence
*
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param InstancePtr Pointer to the instance to be worked on.
*
* @return
* - XST_SUCCESS if initialization was successful
@ -272,7 +277,8 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
Status = XST_FAILURE;
goto RETURN_PATH;
}
} else {
}
else {
Status = XSdPs_MmcCardInitialize(InstancePtr);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
@ -290,13 +296,13 @@ RETURN_PATH:
/*****************************************************************************/
/**
* @brief
* This function performs SD read in polled mode.
* Performs SD read in polled mode.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* @param InstancePtr Pointer to the instance to be worked on.
* @param Arg Address passed by the user that is to be sent as
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
* @param BlkCnt Block count passed by the user.
* @param Buff Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if initialization was successful
@ -343,7 +349,7 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
if (InstancePtr->Config.IsCacheCoherent == 0U) {
Xil_DCacheInvalidateRange((INTPTR)Buff,
((INTPTR)BlkCnt * (INTPTR)InstancePtr->BlkSize));
((INTPTR)BlkCnt * (INTPTR)InstancePtr->BlkSize));
}
RETURN_PATH:
@ -356,13 +362,13 @@ RETURN_PATH:
/*****************************************************************************/
/**
* @brief
* This function performs SD write in polled mode.
* Performs SD write in polled mode.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* @param InstancePtr Pointer to the instance to be worked on.
* @param Arg Address passed by the user that is to be sent as
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
* @param BlkCnt Block count passed by the user.
* @param Buff Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if initialization was successful
@ -418,14 +424,13 @@ RETURN_PATH:
/**
*
* @brief
* API to idle the SDIO Interface
* API to idle the SDIO Interface.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param InstancePtr Pointer to the XSdPs instance.
*
* @return None
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Idle(XSdPs *InstancePtr)
@ -441,8 +446,8 @@ s32 XSdPs_Idle(XSdPs *InstancePtr)
/* Check if the bus is idle */
Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
| XSDPS_PSR_INHIBIT_DAT_MASK
| XSDPS_PSR_DAT_ACTIVE_MASK);
| XSDPS_PSR_INHIBIT_DAT_MASK
| XSDPS_PSR_DAT_ACTIVE_MASK);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH ;
@ -469,11 +474,11 @@ RETURN_PATH:
/*****************************************************************************/
/**
* @brief
* This function performs Erase operation on the given address range.
* Performs Erase operation on the given address range.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param StartAddr is the address of the first write block to be erased.
* @param EndAddr is the address of the last write block of the continuous
* @param InstancePtr Pointer to the instance to be worked on.
* @param StartAddr Address of the first write block to be erased.
* @param EndAddr Address of the last write block of the continuous
* range to be erased.
*
* @return
@ -501,12 +506,12 @@ s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr)
}
if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
!= XSDPS_CAPS_EMB_SLOT)) {
if(InstancePtr->Config.CardDetect != 0U) {
((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
!= XSDPS_CAPS_EMB_SLOT)) {
if (InstancePtr->Config.CardDetect != 0U) {
/* Check status to ensure card is present */
PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
XSDPS_PRES_STATE_OFFSET);
XSDPS_PRES_STATE_OFFSET);
if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
Status = XST_FAILURE;
goto RETURN_PATH;
@ -545,4 +550,45 @@ RETURN_PATH:
return Status;
}
/*****************************************************************************/
/**
* @brief
* Performs Sanitize operation on the unmapped user address range.
*
* @param InstancePtr Pointer to the instance to be worked on.
*
* @return
* - XST_SUCCESS if Sanitize is successful
* - XST_FAILURE if failure - could be because another transfer
* is in progress or card not present or Sanitize operation failure.
*
******************************************************************************/
s32 XSdPs_Sanitize(XSdPs *InstancePtr)
{
s32 Status;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
#if defined (XCLOCKING)
Xil_ClockEnable(InstancePtr->Config.RefClk);
#endif
if (InstancePtr->IsBusy == TRUE) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_START_SANITIZE_ARG);
if (Status != XST_SUCCESS) {
Status = XST_FAILURE;
goto RETURN_PATH;
}
RETURN_PATH:
#if defined (XCLOCKING)
Xil_ClockDisable(InstancePtr->Config.RefClk);
#endif
return Status;
}
/** @} */

111
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,75 +8,10 @@
/**
*
* @file xsdps.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
* @details
*
* This section explains the implementation of the XSdPs driver.
* See xsdps.h for a detailed description of the device and driver.
*
* This driver is used initialize read from and write to the SD card.
* Features such as switching bus width to 4-bit and switching to high speed,
* changing clock frequency, block size etc. are supported.
* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
* is done using 1-bit bus width and 400KHz clock frequency.
* SD commands are classified as broadcast and addressed. Commands can be
* those with response only (using only command line) or
* response + data (using command and data lines).
* Only one command can be sent at a time. During a data transfer however,
* when dsta lines are in use, certain commands (which use only the command
* line) can be sent, most often to obtain status.
* This driver does not support multi card slots at present.
*
* <b>Initialization & Configuration</b>
*
* This includes initialization on the host controller side to select
* clock frequency, bus power and default transfer related parameters.
* The default voltage is 3.3V.
* On the SD card side, the initialization and identification state diagram is
* implemented. This resets the card, gives it a unique address/ID and
* identifies key card related specifications.
*
* <b>Data transfer</b>
*
* The SD card is put in transfer state to read from or write to it.
* The default block size is 512 bytes and if supported,
* default bus width is 4-bit and bus speed is High speed.
* The read and write functions are implemented in polled mode using ADMA2.
*
* At any point, when key parameters such as block size or
* clock/speed or bus width are modified, this driver takes care of
* maintaining the same selection on host and card.
* All error bits in host controller are monitored by the driver and in the
* event one of them is set, driver will clear the interrupt status and
* communicate failure to the upper layer.
*
* <b>File system use</b>
*
* This driver can be used with xilffs library to read and write files to SD.
* (Please refer to procedure in diskio.c). The file system read/write example
* in polled mode can used for reference.
*
* There is no example for using SD driver without file system at present.
* However, the driver can be used without the file system. The glue layer
* in filesystem can be used as reference for the same. The block count
* passed to the read/write function in one call is limited by the ADMA2
* descriptor table and hence care will have to be taken to call read/write
* API's in a loop for large file sizes.
*
* Interrupt mode is not supported because it offers no improvement when used
* with file system.
*
* <b>eMMC support</b>
*
* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
* The features of eMMC supported by the driver will depend on those supported
* by the host controller. The current driver supports read/write on eMMC card
* using 4-bit and high speed mode currently.
*
* Features not supported include - card write protect, password setting,
* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
* 64-bit addressed ADMA2, erase/pre-erase commands.
*
* <pre>
* MODIFICATION HISTORY:
@ -161,6 +96,11 @@
* 4.1 sa 01/03/23 Report error if Transfer size is greater than 2MB.
* 4.1 sa 12/19/22 Enable eMMC HS400 mode for Versal Net.
* sa 01/25/23 Use instance structure to store DMA descriptor tables.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
* 4.2 ap 08/09/23 Reordered XSdPs_FrameCmd XSdPs_Identify_UhsMode functions
* 4.3 ap 10/11/23 Resolved compilation errors with Microblaze RISC-V
* 4.3 ap 11/29/23 Add support for Sanitize feature.
* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
*
* </pre>
*
@ -243,8 +183,12 @@ extern "C" {
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
u32 BaseAddress; /**< Base address of the device */
#else
char *Name;
#endif
UINTPTR BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u32 CardDetect; /**< Card Detect */
u32 WriteProtect; /**< Write Protect */
@ -253,7 +197,7 @@ typedef struct {
u32 HasEMIO; /**< If SD is connected to EMIO */
u8 SlotType; /**< Slot type */
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
#if defined (XCLOCKING)
#if defined (XCLOCKING) || defined (SDT)
u32 RefClk; /**< Input clocks */
#endif
u32 ITapDly_SDR_Clk50; /**< Input Tap delay for HSD/SDR25 modes */
@ -262,6 +206,7 @@ typedef struct {
u32 OTapDly_DDR_Clk50; /**< Output Tap delay for DDR50 modes */
u32 OTapDly_SDR_Clk100; /**< Input Tap delay for SDR50 modes */
u32 OTapDly_SDR_Clk200; /**< Input Tap delay for SDR104/HS200 modes */
u32 OTapDly_DDR_Clk200; /**< Input Tap delay for HS400 modes */
} XSdPs_Config;
/**
@ -275,7 +220,8 @@ typedef struct {
#pragma data_alignment = 32
} XSdPs_Adma2Descriptor32;
#else
} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
}
__attribute__((__packed__))XSdPs_Adma2Descriptor32;
#endif
/**
@ -325,11 +271,11 @@ typedef struct {
u8 IsTuningDone; /**< Flag to indicate HS200 tuning complete */
#ifdef __ICCARM__
#pragma data_alignment = 32
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32];
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32];
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32]; /**< ADMA descriptor table 32 Bit */
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32]; /**< ADMA descriptor table 64 Bit */
#else
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32)));
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32)));
XSdPs_Adma2Descriptor32 Adma2_DescrTbl32[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 32 Bit */
XSdPs_Adma2Descriptor64 Adma2_DescrTbl64[32] __attribute__ ((aligned(32))); /**< ADMA descriptor table 64 Bit */
#endif
} XSdPs;
@ -355,10 +301,24 @@ typedef struct {
*/
#define ENABLE_HS400_MODE
/************************** Variable Definitions *****************************/
/**
* XSdPs Configuration Table
*/
#ifndef SDT
extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
#else
extern XSdPs_Config XSdPs_ConfigTable[];
#endif
/************************** Function Prototypes ******************************/
#ifndef SDT
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
#else
XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress);
#endif
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
u32 EffectiveAddr);
UINTPTR EffectiveAddr);
s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
@ -380,6 +340,7 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
s32 XSdPs_Erase(XSdPs *InstancePtr, u32 StartAddr, u32 EndAddr);
s32 XSdPs_Sanitize(XSdPs *InstancePtr);
#ifdef __cplusplus
}

521
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_card.c
View File

File diff suppressed because it is too large Load Diff

11
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_core.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,10 +8,10 @@
/**
*
* @file xsdps_core.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* The xsdps_core.h header file contains the identifiers and basic HW access driver
* The xsdps_core.h header file contains the identifiers and basic hardware access driver
* functions (or macros) that can be used to access the device. Other driver
* functions are defined in xsdps.h.
*
@ -27,6 +27,7 @@
* mn 11/28/21 Fix MISRA-C violations.
* 4.0 sk 02/25/22 Add support for eMMC5.1.
* 4.1 sa 01/06/23 Include xil_util.h in this file.
* 4.2 ap 08/09/23 Add XSdPs_SetTapDelay APIs.
* </pre>
*
******************************************************************************/
@ -110,6 +111,10 @@ void XSdPs_ConfigInterrupt(XSdPs *InstancePtr);
s32 XSdPs_SendErase(XSdPs *InstancePtr);
s32 XSdPs_SetEndAddr(XSdPs *InstancePtr, u32 EndAddr);
s32 XSdPs_SetStartAddr(XSdPs *InstancePtr, u32 StartAddr);
void XSdPs_SetTapDelay_SDR104(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_SDR50(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_DDR50(XSdPs *InstancePtr);
void XSdPs_SetTapDelay_SDR25(XSdPs *InstancePtr);
#ifdef VERSAL_NET
u32 XSdPs_Select_HS400(XSdPs *InstancePtr);
#endif

7
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_g.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +8,7 @@
/**
*
* @file xsdps_g.c
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* The xsdps_g.c file contains a configuration table that specifies the
@ -54,7 +54,8 @@ XSdPs_Config XSdPs_ConfigTable[] =
XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY,
XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY,
XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY,
XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY
XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY,
XPAR_XSDPS_0_CLK_200_DDR_OTAP_DLY
}
};
/** @} */

727
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_host.c
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File diff suppressed because it is too large Load Diff

215
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_hw.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +8,7 @@
/**
*
* @file xsdps_hw.h
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{{
*
* The xsdps_hw.h header file contains the identifiers and basic HW access driver
@ -45,6 +45,9 @@
* 4.0 sk 02/25/22 Add support for eMMC5.1.
* sk 04/07/22 Fix typo in 'XSDPS_MMC_1_BIT_BUS_ARG' macro definition.
* 4.1 sk 11/10/22 Add SD/eMMC Tap delay support for Versal Net.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
* 4.3 ap 11/29/23 Add support for Sanitize feature.
* 4.3 ap 12/22/23 Add support to read custom HS400 tap delay value from design for eMMC.
*
* </pre>
*
@ -63,8 +66,8 @@ extern "C" {
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "bspconfig.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
@ -76,8 +79,8 @@ extern "C" {
#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
Register */
#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
/**< SDMA System Address
Low Register */
/**< SDMA System Address
Low Register */
#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
High Register */
@ -87,7 +90,7 @@ extern "C" {
#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
/**< Argument1 Register */
/**< Argument1 Register */
#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
@ -714,16 +717,16 @@ extern "C" {
#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
(u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
/** @} */
@ -929,18 +932,24 @@ extern "C" {
#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
#define EXT_CSD_SANITIZE_START (0x1U)
#define EXT_CSD_PART_CONFIG_BYTE (179U)
#define EXT_CSD_SANIT_CONFIG_BYTE (165U)
#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)(0U) << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)(0U) << 8U))
#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
| ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
#define XSDPS_MMC_START_SANITIZE_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
| ((u32)EXT_CSD_SANIT_CONFIG_BYTE << 16U) \
| ((u32)EXT_CSD_SANITIZE_START << 8U))
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
@ -952,14 +961,14 @@ extern "C" {
#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
/* DDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
/* SDR mode @1.2V I/O */
#define EXT_CSD_BUS_WIDTH_BYTE 183U
#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
@ -992,44 +1001,44 @@ extern "C" {
* SD/MMC Arguments for Bus Speed and Bus Width.
*/
#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
#define XSDPS_MMC_HS400_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS400 << 8))
| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
| ((u32)EXT_CSD_HS_TIMING_HS400 << 8))
#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_1_BIT << 8))
#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
| ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
| ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
| ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
| ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
| ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
| ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
@ -1196,6 +1205,8 @@ extern "C" {
#define SD_ITAPCHGWIN 0x00000200U
#define SD_ITAPDLYENA 0x00000100U
#define SD_OTAPDLYENA 0x00000040U
#define SD_OTAPDLYSEL_SD104_B0 0x00000002U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000007U
#define SD_OTAPDLYSEL_HS200_B2 0x00000007U
#define SD_OTAPDLYSEL_HS400 0x00000004U
@ -1224,6 +1235,8 @@ extern "C" {
#define SD_ITAPCHGWIN 0x00000200U
#define SD_ITAPDLYENA 0x00000100U
#define SD_OTAPDLYENA 0x00000040U
#define SD_OTAPDLYSEL_SD104_B0 0x00000002U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
#define SD_ITAPDLYSEL_SD50 0x0000000EU
@ -1255,6 +1268,8 @@ extern "C" {
#define SD1_ITAPCHGWIN 0x02000000U
#define SD1_ITAPDLYENA 0x01000000U
#define SD1_OTAPDLYENA 0x00400000U
#define SD_OTAPDLYSEL_SD104_B0 0x00000003U
#define SD_OTAPDLYSEL_SD104_B2 0x00000002U
#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
#define SD_ITAPDLYSEL_SD50 0x00000014U
@ -1273,7 +1288,7 @@ extern "C" {
#endif
/** @} */
#ifdef __MICROBLAZE__
#if defined (__MICROBLAZE__) || defined (__riscv)
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
#endif
@ -1294,16 +1309,16 @@ extern "C" {
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param InstancePtr is the pointer to the sdps instance.
* @param RegOffset contains the offset from the 1st register of the
* @param InstancePtr Pointer to the sdps instance.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
@ -1311,36 +1326,36 @@ extern "C" {
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param InstancePtr is the pointer to the sdps instance.
* @param RegOffset contains the offset from the 1st register of the
* @param InstancePtr Pointer to the sdps instance.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
* u64 RegisterValue)
* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
* u64 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
(RegisterValue))
(RegisterValue))
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u32 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
#define XSdPs_ReadReg(BaseAddress, RegOffset) \
@ -1348,18 +1363,18 @@ extern "C" {
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
@ -1367,25 +1382,25 @@ extern "C" {
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u16 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
static INLINE u16 XSdPs_ReadReg16(UINTPTR BaseAddress, u8 RegOffset)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg >>= ((RegOffset & 0x3)*8);
Reg >>= ((RegOffset & 0x3) * 8);
return (u16)Reg;
#else
return XSdPs_In16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset));
@ -1394,29 +1409,29 @@ static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u16 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u16 RegisterValue)
*
******************************************************************************/
static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
static INLINE void XSdPs_WriteReg16(UINTPTR BaseAddress, u8 RegOffset, u16 RegisterValue)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
Reg &= ~(0xFFFFU << ((RegOffset & 0x3) * 8));
Reg |= RegisterValue << ((RegOffset & 0x3) * 8);
XSdPs_Out32(BaseAddress, Reg);
#else
XSdPs_Out16((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue));
@ -1425,25 +1440,25 @@ static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterV
/****************************************************************************/
/**
* Read a register.
* Reads a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
* u8 XSdPs_ReadReg(UINTPTR BaseAddress. int RegOffset)
*
******************************************************************************/
static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
static INLINE u8 XSdPs_ReadReg8(UINTPTR BaseAddress, u8 RegOffset)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg >>= ((RegOffset & 0x3)*8);
Reg >>= ((RegOffset & 0x3) * 8);
return (u8)Reg;
#else
return XSdPs_In8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset));
@ -1451,28 +1466,28 @@ static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
}
/***************************************************************************/
/**
* Write to a register.
* Writes to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* @param BaseAddress Contains the base address of the device.
* @param RegOffset Contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
* @param RegisterValue Value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
static INLINE void XSdPs_WriteReg8(UINTPTR BaseAddress, u8 RegOffset, u8 RegisterValue)
{
#if defined (__MICROBLAZE__)
#if defined (__MICROBLAZE__) || defined (__riscv)
u32 Reg;
BaseAddress += RegOffset & 0xFC;
Reg = XSdPs_In32(BaseAddress);
Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
Reg |= RegisterValue <<((RegOffset & 0x3)*8);
Reg &= ~(0xFFU << ((RegOffset & 0x3) * 8));
Reg |= RegisterValue << ((RegOffset & 0x3) * 8);
XSdPs_Out32(BaseAddress, Reg);
#else
XSdPs_Out8((UINTPTR)(BaseAddress) + (UINTPTR)(RegOffset), (RegisterValue));
@ -1480,19 +1495,19 @@ static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterVal
}
/***************************************************************************/
/**
* Macro to get present status register
* Macro to get present status register.
*
* @param BaseAddress contains the base address of the device.
* @param BaseAddress Contains the base address of the device.
*
* @return None.
*
* @note C-Style signature:
* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
* u8 RegisterValue)
* void XSdPs_WriteReg(UINTPTR BaseAddress, int RegOffset,
* u8 RegisterValue)
*
******************************************************************************/
#define XSdPs_GetPresentStatusReg(BaseAddress) \
XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
/************************** Function Prototypes ******************************/

95
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_options.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +8,7 @@
/**
*
* @file xsdps_options.c
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* The xsdps_options.c file ontains APIs for changing the various options in host and card.
@ -82,11 +82,11 @@
/**
*
* @brief
* API to change clock freq to given value.
* API to change clock frequency to a given value.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param SelFreq - Clock frequency in Hz.
* @param InstancePtr Pointer to the XSdPs instance.
* @param SelFreq Clock frequency in Hz.
*
* @return None
*
@ -148,10 +148,10 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
/*****************************************************************************/
/**
* @brief
* Update Block size for read/write operations.
* Updates Block size for read/write operations.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param BlkSize - Block size passed by the user.
* @param InstancePtr Pointer to the instance to be worked on.
* @param BlkSize Block size passed by the user.
*
* @return None
*
@ -193,11 +193,11 @@ RETURN_PATH:
/**
*
* @brief
* API to get bus width support by card.
* Gets bus width support by card.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param ReadBuff - buffer to store SCR register returned by card.
* @param InstancePtr Pointer to the XSdPs instance.
* @param ReadBuff Buffer to store SCR register returned by card.
*
* @return
* - XST_SUCCESS if successful.
@ -262,16 +262,15 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
/**
*
* @brief
* API to set bus width to 4-bit in card and host
* Sets bus width to 4-bit in card and host.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param InstancePtr Pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
@ -366,11 +365,11 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
/**
*
* @brief
* API to get bus speed supported by card.
* Gets bus speed supported by card.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param ReadBuff - buffer to store function group support data
* @param InstancePtr Pointer to the XSdPs instance.
* @param ReadBuff Buffer to store function group support data
* returned by card.
*
* @return
@ -431,17 +430,16 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
/**
*
* @brief
* API to get SD card status information.
* Gets SD card status information.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param SdStatReg - buffer to store status data returned by card.
* @param InstancePtr Pointer to the XSdPs instance.
* @param SdStatReg Buffer to store status data returned by card.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
@ -494,16 +492,15 @@ s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
/**
*
* @brief
* API to set high speed in card and host. Changes clock in host accordingly.
* Sets high speed in card and host. Changes clock in host accordingly.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param InstancePtr Pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
@ -575,17 +572,16 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
/**
*
* @brief
* API to get EXT_CSD register of eMMC.
* Gets EXT_CSD register of eMMC.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param ReadBuff - buffer to store EXT_CSD
* @param InstancePtr Pointer to the XSdPs instance.
* @param ReadBuff Buffer to store EXT_CSD
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
@ -638,17 +634,16 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
/**
*
* @brief
* API to write EXT_CSD register of eMMC.
* Writes EXT_CSD register of eMMC.
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param Arg is the argument to be sent along with the command
* @param InstancePtr Pointer to the XSdPs instance.
* @param Arg Argument to be sent along with the command.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
@ -682,16 +677,15 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
/**
*
* @brief
* API to send pullup command to card before using DAT line 3(using 4-bit bus)
* Sends pullup command to card before using DAT line 3(using 4-bit bus).
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param InstancePtr Pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Pullup(XSdPs *InstancePtr)
@ -728,14 +722,13 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr)
* Selects card and sets default block size
*
*
* @param InstancePtr is a pointer to the XSdPs instance.
* @param InstancePtr Pointer to the XSdPs instance.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE if fail.
* - XSDPS_CT_ERROR if Command Transfer fail.
*
* @note None.
*
******************************************************************************/
s32 XSdPs_Select_Card (XSdPs *InstancePtr)
@ -755,13 +748,13 @@ s32 XSdPs_Select_Card (XSdPs *InstancePtr)
/*****************************************************************************/
/**
* @brief
* This function performs SD read in polled mode.
* Performs SD read in polled mode.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* @param InstancePtr Pointer to the instance to be worked on.
* @param Arg Address passed by the user that is to be sent as
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
* @param BlkCnt Block count passed by the user.
* @param Buff Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if Transfer initialization was successful
@ -803,13 +796,13 @@ RETURN_PATH:
/*****************************************************************************/
/**
* @brief
* This function start SD write transfer.
* Starts SD write transfer.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Arg is the address passed by the user that is to be sent as
* @param InstancePtr Pointer to the instance to be worked on.
* @param Arg Address passed by the user that is to be sent as
* argument along with the command.
* @param BlkCnt - Block count passed by the user.
* @param Buff - Pointer to the data buffer for a DMA transfer.
* @param BlkCnt Block count passed by the user.
* @param Buff Pointer to the data buffer for a DMA transfer.
*
* @return
* - XST_SUCCESS if Transfer initialization was successful
@ -851,9 +844,9 @@ RETURN_PATH:
/*****************************************************************************/
/**
* @brief
* This function is used to check if the transfer is completed successfully.
* Checks if the transfer is completed successfully.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param InstancePtr Pointer to the instance to be worked on.
*
* @return
* - XST_SUCCESS if transfer was successful
@ -876,9 +869,9 @@ s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr)
/*****************************************************************************/
/**
* @brief
* This function is used to check for the write transfer completed.
* Checks for the write transfer completed.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param InstancePtr Pointer to the instance to be worked on.
*
* @return
* - XST_SUCCESS if transfer was successful

34
bsp_z7/ps7_cortexa9_0/libsrc/sdps/src/xsdps_sinit.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,11 +8,11 @@
/**
*
* @file xsdps_sinit.c
* @addtogroup sdps Overview
* @addtogroup sdps_api SDPS APIs
* @{
*
* The implementation of the XSdPs component's static initialization
* functionality.
* The file contains the implementation of the static initialization
* functionality of the XSdPs component.
*
* <pre>
* MODIFICATION HISTORY:
@ -22,6 +22,7 @@
* 1.00a hk/sg 10/17/13 Initial release
* kvn 07/15/15 Modified the code according to MISRAC-2012.
* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
* 4.2 ro 06/12/23 Added support for system device-tree flow.
*
* </pre>
*
@ -40,10 +41,6 @@
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/**
* XSdPs Configuration Table
*/
extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
/*****************************************************************************/
/**
@ -52,7 +49,7 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
* Looks up the device configuration based on the unique device ID. A table
* contains the configuration info for each device in the system.
*
* @param DeviceId contains the ID of the device to look up the
* @param DeviceId Contains the ID of the device to look up the
* configuration for.
*
* @return
@ -60,9 +57,9 @@ extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
* A pointer to the configuration found or NULL if the specified device ID was
* not found. See xsdps.h for the definition of XSdPs_Config.
*
* @note None.
*
******************************************************************************/
#ifndef SDT
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
{
XSdPs_Config *CfgPtr = NULL;
@ -76,4 +73,21 @@ XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
}
return (XSdPs_Config *)CfgPtr;
}
#else
XSdPs_Config *XSdPs_LookupConfig(u32 BaseAddress)
{
XSdPs_Config *CfgPtr = NULL;
u32 Index;
for (Index = 0U; XSdPs_ConfigTable[Index].Name != NULL; Index++) {
if ((XSdPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
!BaseAddress) {
CfgPtr = &XSdPs_ConfigTable[Index];
break;
}
}
return (XSdPs_Config *)CfgPtr;
}
#endif
/** @} */

31
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/boot.S
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
@ -64,6 +65,8 @@
* 742230 and 743622. These do not apply to
* Cortex-A9 revision r3p0 being used in Zynq
* platforms.
* 9.0 mus 07/27/23 Removed dependency on XPAR_CPU_ID, updated logic to use
* CPU affinity register to read CPU ID.
*
* </pre>
*
@ -73,7 +76,10 @@
*
******************************************************************************/
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#include "xil_errata.h"
.globl MMUTable
@ -146,16 +152,12 @@
_prestart:
_boot:
#if XPAR_CPU_ID==0
/* only allow cpu0 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #0
beq CheckEFUSE
EndlessLoop0:
wfe
b EndlessLoop0
b OKToRun
CheckEFUSE:
ldr r0,=EFUSEStaus
@ -177,24 +179,6 @@ CheckEFUSE:
ldr r1,=SLCRlockKey /* set lock key */
str r1, [r0] /* lock SLCR */
#elif XPAR_CPU_ID==1
/* only allow cpu1 through */
mrc p15,0,r1,c0,c0,5
and r1, r1, #0xf
cmp r1, #1
beq CheckEFUSE1
b EndlessLoop1
CheckEFUSE1:
ldr r0,=EFUSEStaus
ldr r1,[r0] /* Read eFuse setting */
ands r1,r1,#0x80 /* Check whether device is having single core */
beq OKToRun
EndlessLoop1:
wfe
b EndlessLoop1
#endif
OKToRun:
mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
and r5, r0, #0x00f00000
@ -204,7 +188,6 @@ OKToRun:
/* set VBAR to the _vector_table address in linker script */
ldr r0, =vector_base
mcr p15, 0, r0, c12, c0, 0
MRC p15, 0, r1, c12, c0, 0
/*invalidate scu*/
#if USE_AMP!=1

4
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/outbyte.c
View File

@ -8,12 +8,12 @@
#ifdef __cplusplus
extern "C" {
#endif
void outbyte(uint8_t c);
void outbyte(char c);
#ifdef __cplusplus
}
#endif
void outbyte(uint8_t c) {
void outbyte(char c) {
XUartPs_SendByte(STDOUT_BASEADDRESS, c);
}

268
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/pm_api_version.h Normal file
View File

@ -0,0 +1,268 @@
/******************************************************************************
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_api_version.h
*
* @addtogroup xpm_versal_apis XilPM APIs
*****************************************************************************/
#ifndef PM_API_VERSION_H_
#define PM_API_VERSION_H_
/*****************************************************************************/
/**
* @section EEMI_API_DETAIL XilPM EEMI API Version Detail
*
* This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
*
* | NAME | ID | Platform | Version| Description |
* |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
* | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API |
* | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device |
* | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality |
* | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event |
* | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem |
* | PM_SELF_SUSPEND | 0x7 | Both | 3 | V1 - The API is used to suspend a child subsystem |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | V3 - Added support of CPU off state |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal and Versal NET but ZynqMP supports only V1|
* | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem |
* | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem |
* | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source |
* | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system |
* | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use |
* | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device |
* | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device |
* | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state |
* | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices |
* | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip |
* | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin |
* | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin |
* | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function |
* | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function |
* | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value |
* | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value |
* | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 |
* | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 |
* | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock |
* | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock |
* | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state |
* | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock |
* | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider |
* | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock |
* | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent |
* | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock |
* | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock |
* | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock |
* | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock |
* | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
*
* This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|---------------------------------------|
* | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode |
* | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode |
* | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config |
* | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config |
* | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass |
* | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset |
* | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay |
* | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode |
* | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode |
* | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data |
* | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data |
* | IOCTL_WRITE_GGS | 12 | Both | Write GGS |
* | IOCTL_READ_GGS | 13 | Both | Read GGS |
* | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS |
* | IOCTL_READ_PGGS | 15 | Both | Read PGGS |
* | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset |
* | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status |
* | IOCTL_AFI | 18 | ZynqMP | AFI |
* | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select |
* | IOCTL_USB_SET_STATE | 22 | Versal | USB set state |
* | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason |
* | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear |
* | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF |
* | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config |
* | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config |
* | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register |
* | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register |
* | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value |
* | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value |
* | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value |
* | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations |
* | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value |
* | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode |
* | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode |
* | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down |
* | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
*
* This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |--------------------------------------------|-------|---------------|---------------------------------------|
* | XPM_QID_INVALID | 0 | Both | Invalid Query ID |
* | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name |
* | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology |
* | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter |
* | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources |
* | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes |
* | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups |
* | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name |
* | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups |
* | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups |
* | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks |
* | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor |
* | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent |
* | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
*
* This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|-----------------------------------------------|
* | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power |
* | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature |
* | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency |
*
*****************************************************************************/
/**
* PM API IDs
*/
typedef enum {
PM_API_MIN, /**< 0x0 */
PM_GET_API_VERSION, /**< 0x1 */
PM_SET_CONFIGURATION, /**< 0x2 */
PM_GET_NODE_STATUS, /**< 0x3 */
PM_GET_OP_CHARACTERISTIC, /**< 0x4 */
PM_REGISTER_NOTIFIER, /**< 0x5 */
PM_REQUEST_SUSPEND, /**< 0x6 */
PM_SELF_SUSPEND, /**< 0x7 */
PM_FORCE_POWERDOWN, /**< 0x8 */
PM_ABORT_SUSPEND, /**< 0x9 */
PM_REQUEST_WAKEUP, /**< 0xA */
PM_SET_WAKEUP_SOURCE, /**< 0xB */
PM_SYSTEM_SHUTDOWN, /**< 0xC */
PM_REQUEST_NODE, /**< 0xD */
PM_RELEASE_NODE, /**< 0xE */
PM_SET_REQUIREMENT, /**< 0xF */
PM_SET_MAX_LATENCY, /**< 0x10 */
PM_RESET_ASSERT, /**< 0x11 */
PM_RESET_GET_STATUS, /**< 0x12 */
PM_MMIO_WRITE, /**< 0x13 */
PM_MMIO_READ, /**< 0x14 */
PM_INIT_FINALIZE, /**< 0x15 */
PM_FPGA_LOAD, /**< 0x16 */
PM_FPGA_GET_STATUS, /**< 0x17 */
PM_GET_CHIPID, /**< 0x18 */
PM_SECURE_RSA_AES, /**< 0x19 */
PM_SECURE_SHA, /**< 0x1A */
PM_SECURE_RSA, /**< 0x1B */
PM_PINCTRL_REQUEST, /**< 0x1C */
PM_PINCTRL_RELEASE, /**< 0x1D */
PM_PINCTRL_GET_FUNCTION, /**< 0x1E */
PM_PINCTRL_SET_FUNCTION, /**< 0x1F */
PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */
PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */
PM_IOCTL, /**< 0x22 */
PM_QUERY_DATA, /**< 0x23 */
PM_CLOCK_ENABLE, /**< 0x24 */
PM_CLOCK_DISABLE, /**< 0x25 */
PM_CLOCK_GETSTATE, /**< 0x26 */
PM_CLOCK_SETDIVIDER, /**< 0x27 */
PM_CLOCK_GETDIVIDER, /**< 0x28 */
PM_CLOCK_SETRATE, /**< 0x29 */
/* PM_CLOCK_GETRATE API is deprecated */
PM_RESERVE_ID, /**< 0x2A */
PM_CLOCK_SETPARENT, /**< 0x2B */
PM_CLOCK_GETPARENT, /**< 0x2C */
PM_SECURE_IMAGE, /**< 0x2D */
PM_FPGA_READ, /**< 0x2E */
PM_SECURE_AES, /**< 0x2F */
PM_PLL_SET_PARAMETER, /**< 0x30 */
PM_PLL_GET_PARAMETER, /**< 0x31 */
PM_PLL_SET_MODE, /**< 0x32 */
PM_PLL_GET_MODE, /**< 0x33 */
PM_REGISTER_ACCESS, /**< 0x34 */
PM_EFUSE_ACCESS, /**< 0x35 */
PM_ADD_SUBSYSTEM, /**< 0x36 */
PM_DESTROY_SUBSYSTEM, /**< 0x37 */
PM_DESCRIBE_NODES, /**< 0x38 */
PM_ADD_NODE, /**< 0x39 */
PM_ADD_NODE_PARENT, /**< 0x3A */
PM_ADD_NODE_NAME, /**< 0x3B */
PM_ADD_REQUIREMENT, /**< 0x3C */
PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */
PM_INIT_NODE, /**< 0x3E */
PM_FEATURE_CHECK, /**< 0x3F */
PM_ISO_CONTROL, /**< 0x40 */
PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */
PM_SET_NODE_ACCESS, /**< 0x42 */
PM_BISR, /**< 0x43 */
PM_APPLY_TRIM, /**< 0x44 */
PM_NOC_CLOCK_ENABLE, /**< 0x45 */
PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */
PM_FORCE_HOUSECLEAN, /**< 0x47 */
PM_FPGA_GET_VERSION, /**< 0x48 */
PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */
PM_API_MAX /**< 0x4A */
} XPm_ApiId;
#endif /* PM_API_VERSION_H_ */

13
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/print.c
View File

@ -12,19 +12,22 @@
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
*/
*****************************************************************************/
/***************************** Include Files *********************************/
/*
* print -- do a raw print of a string
*/
#include "xil_printf.h"
/*****************************************************************************/
/**
* print -- do a raw print of a string
*
******************************************************************************/
void print(const char8 *ptr)
{
#if defined (__aarch64__) && (HYP_GUEST == 1) && (EL1_NONSECURE == 1) && defined (XEN_USE_PV_CONSOLE)
XPVXenConsole_Write(ptr);
#else
#ifdef STDOUT_BASEADDRESS
#if defined(STDOUT_BASEADDRESS) || defined(SDT)
while (*ptr != (char8)0) {
outbyte (*ptr);
ptr++;

11
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/putnum.c
View File

@ -11,11 +11,7 @@
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
* putnum -- print a 32 bit number in hex
*/
*****************************************************************************/
/***************************** Include Files *********************************/
#include "xil_types.h"
@ -24,6 +20,11 @@
/************************** Function Prototypes ******************************/
void putnum(u32 num);
/*****************************************************************************/
/**
* putnum -- print a 32 bit number in hex
*
******************************************************************************/
void putnum(u32 num)
{
char8 buf[9];

8
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/read.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +9,10 @@
*/
#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -28,7 +32,7 @@ __attribute__((weak)) s32 read (s32 fd, char8* buf, s32 nbytes);
__attribute__((weak)) s32
read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
#if defined (STDIN_BASEADDRESS) || defined(SDT)
s32 i;
s32 numbytes = 0;
char8* LocalBuf = buf;
@ -56,7 +60,7 @@ read (s32 fd, char8* buf, s32 nbytes)
__attribute__((weak)) s32
_read (s32 fd, char8* buf, s32 nbytes)
{
#ifdef STDIN_BASEADDRESS
#if defined(STDIN_BASEADDRESS) || defined(SDT)
s32 i;
s32 numbytes = 0;
char8* LocalBuf = buf;

9
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -21,7 +22,7 @@
* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
* implementation. Now sleep routines will use Timer
* specified by the user (i.e. Global timer/TTC timer)
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
@ -36,7 +37,7 @@
#endif
/*****************************************************************************/
/*
/**
*
* This API is used to provide delays in seconds
*
@ -46,7 +47,7 @@
*
* @note None.
*
****************************************************************************/
******************************************************************************/
unsigned sleep_A9(unsigned int seconds)
{
#if defined (SLEEP_TIMER_BASEADDR)

11
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/sleep.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -30,7 +31,8 @@
* 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to
* u32 and usleep_MB parameter type from unsigned long to
* ULONG to fix misra_c_2012_rule_4_6 violation.
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* 9.1 mus 10/24/23 Add support for RISC-V.
* </pre>
*
******************************************************************************/
@ -87,6 +89,7 @@ extern "C" {
(timeout>0) ? 0 : -1; \
} )
/************************** Function Prototypes ******************************/
void usleep(ULONG useconds);
void sleep(u32 seconds);
void usleep_R5(ULONG useconds);
@ -97,6 +100,10 @@ int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
void sleep_riscv(u32 seconds);
void usleep_riscv(ULONG useconds);
/*****************************************************************************/
#ifdef __cplusplus
}

11
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/translation_table.S
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
@ -67,7 +68,12 @@
*
*
******************************************************************************/
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#else
#include "xmem_config.h"
#endif
.globl MMUTable
.section .mmu_tbl,"a"
@ -84,6 +90,11 @@ MMUTable:
.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
.set DDR_SIZE, (DDR_END - DDR_START)+1
.set DDR_REG, DDR_SIZE/0x100000
#elif defined(XPAR_PS7_DDR_0_BASEADDRESS)
.set DDR_START, XPAR_PS7_DDR_0_BASEADDRESS
.set DDR_END, XPAR_PS7_DDR_0_HIGHADDRESS
.set DDR_SIZE, (DDR_END - DDR_START)+1
.set DDR_REG, DDR_SIZE/0x100000
#else
.set DDR_REG, 0
#endif

4
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/usleep.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -25,6 +26,7 @@
* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
* implementation. Now sleep routines will use Timer
* specified by the user (i.e. Global timer/TTC timer)
* 9.0 ml 03/03/23 Added description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
@ -45,7 +47,7 @@
#if defined (SLEEP_TIMER_BASEADDR)
#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
#else
/* Global Timer is always clocked at half of the CPU frequency */
/**< Global Timer is always clocked at half of the CPU frequency */
#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
#endif

8
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/write.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -8,7 +9,10 @@
*/
#ifndef UNDEFINE_FILE_OPS
#include "xil_printf.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -30,7 +34,7 @@ __attribute__((weak)) sint32
write (sint32 fd, char8* buf, sint32 nbytes)
{
#ifdef STDOUT_BASEADDRESS
#if defined(STDOUT_BASEADDRESS) || defined(SDT)
s32 i;
char8* LocalBuf = buf;
@ -69,7 +73,7 @@ _write (sint32 fd, char8* buf, sint32 nbytes)
length = XPVXenConsole_Write(buf);
return length;
#else
#ifdef STDOUT_BASEADDRESS
#if defined(STDOUT_BASEADDRESS) || defined(SDT)
s32 i;
char8* LocalBuf = buf;

18
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9.h Normal file
View File

@ -0,0 +1,18 @@
/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
/**************************** Type Definitions ******************************/
typedef struct {
u32 CpuFreq;
} XCortexa9_Config;
#endif /* XIL_XCORTEXA9_H_ */

18
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xcortexa9_config.h Normal file
View File

@ -0,0 +1,18 @@
/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xcortexa9.h"
/************************** Variable Definitions ****************************/
extern XCortexa9_Config XCortexa9_ConfigTable;
/***************** Macros (Inline Functions) Definitions ********************/
#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq
#endif /* XIL_XCORTEXA9_CONFIG_H_ */

6
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xdebug.h
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -61,13 +61,13 @@ int printf(const char *format, ...);
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x)
#define xdbg_stmnt(x) /**< Debug statement */
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...)
#define xdbg_printf(...) /**< Debug printf */
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */

4
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil-crt0.S
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
@ -25,6 +26,7 @@
* Now the TTC instance as specified by the user will be
* started.
* 7.7 adk 11/30/21 Added support for xiltimer library.
* 9.1 dp 01/24/24 Dont invoke XTime_StartTTCTimer when xiltimer is enabled
* </pre>
*
* @note
@ -93,7 +95,7 @@ _start:
mov r1, #0x0
/* Reset and start Triple Timer Counter */
#if defined SLEEP_TIMER_BASEADDR
#if defined SLEEP_TIMER_BASEADDR && !defined(XPAR_XILTIMER_ENABLED)
bl XTime_StartTTCTimer
#endif

100
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
* Copyright (c) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -89,6 +89,18 @@
* 8.1 asa 02/13/23 The existing Xil_DCacheInvalidateRange has a bug where
* the last cache line will not get invalidated under certain
* scenarios. Changes are made to fix the same.
* 9.0 ml 03/03/23 Added description to fix doxygen warnings.
* mus 09/21/23 Fix infinite loop in Xil_DCacheInvalidateRange when
* USE_AMP=1.
* 9.1 asa 01/12/24 Fix issues in Xil_DCacheInvalidateRange.
* 9.1 asa 01/29/24 In an unlikely scenario where the start address
* passed is 0x0 and length is less than 0x20 (cache line),
* the XilDCacheInvalidateRange API will result in
* a probable crash as it will try to invalidate the
* complete 4 GB address range.
* Changes are made to fix the same.
* 9.1 asa 31/01/24 Fix overflow issues under corner cases for various
* cache maintenance APIs.
* </pre>
*
******************************************************************************/
@ -109,7 +121,9 @@
/************************** Variable Definitions *****************************/
#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
#define IRQ_FIQ_MASK 0xC0U /**< Mask IRQ and FIQ interrupts in cpsr */
#define MAX_ADDR 0xFFFFFFFFU
#define LAST_CACHELINE_START 0xFFFFFFE0U
#ifdef __GNUC__
extern s32 _stack_end;
@ -117,7 +131,8 @@
#endif
#ifndef USE_AMP
/****************************************************************************
/***************************************************************************/
/**
*
* Access L2 Debug Control Register.
*
@ -139,7 +154,8 @@ static void Xil_L2WriteDebugCtrl(u32 Value)
#endif
}
/****************************************************************************
/***************************************************************************/
/**
*
* Perform L2 Cache Sync Operation.
*
@ -300,13 +316,14 @@ void Xil_DCacheInvalidateLine(u32 adr)
* @return None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len)
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
const u32 cacheline = 32U;
INTPTR tempadr;
INTPTR opendaddr;
INTPTR endaddr;
u32 currmask;
u32 unalignedstart = 0x0;
volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
XPS_L2CC_CACHE_INVLD_PA_OFFSET);
@ -314,27 +331,29 @@ void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len)
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
opendaddr = opstartaddr + len;
((MAX_ADDR - (u32)adr) < len) ? (opendaddr = MAX_ADDR) : (opendaddr = adr + len);
endaddr = opendaddr;
if ((opstartaddr & (cacheline-1U)) != 0U) {
opstartaddr &= (~(cacheline - 1U));
if ((adr & (cacheline-1U)) != 0U) {
adr &= (~(cacheline - 1U));
unalignedstart = 1;
Xil_L1DCacheFlushLine(opstartaddr);
Xil_L1DCacheFlushLine(adr);
#ifndef USE_AMP
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3U);
Xil_L2CacheFlushLine(opstartaddr);
Xil_L2CacheFlushLine(adr);
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0U);
Xil_L2CacheSync();
#endif
opstartaddr += cacheline;
tempadr = adr;
(u32)adr >= LAST_CACHELINE_START ? (adr = endaddr) : (adr += cacheline);
}
if ((opendaddr & (cacheline-1U)) != 0U) {
opendaddr &= (~(cacheline - 1U));
if (opendaddr != opstartaddr) {
if ((opendaddr != tempadr) || (unalignedstart == 0x0U)) {
Xil_L1DCacheFlushLine(opendaddr);
#ifndef USE_AMP
/* Disable Write-back and line fills */
@ -343,31 +362,32 @@ void Xil_DCacheInvalidateRange(INTPTR opstartaddr, u32 len)
/* Enable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x0U);
Xil_L2CacheSync();
(u32)endaddr >= cacheline ? (endaddr -= cacheline) : (endaddr = 0);
#endif
}
}
tempadr = opstartaddr;
tempadr = adr;
while (tempadr < endaddr) {
#ifndef USE_AMP
while (tempadr < endaddr) {
/* Invalidate L2 cache line */
*L2CCOffset = tempadr;
Xil_L2CacheSync();
tempadr += cacheline;
#endif
((MAX_ADDR - (u32)tempadr) < cacheline) ? (tempadr = MAX_ADDR) : (tempadr += cacheline) ;
}
#endif
while (opstartaddr < endaddr) {
while (adr < endaddr) {
/* Invalidate L1 Data cache line */
#if defined (__GNUC__) || defined (__ICCARM__)
asm_cp15_inval_dc_line_mva_poc(opstartaddr);
asm_cp15_inval_dc_line_mva_poc(adr);
#else
{ volatile register u32 Reg
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
Reg = opstartaddr; }
Reg = adr; }
#endif
opstartaddr += cacheline;
((MAX_ADDR - (u32)adr) < cacheline) ? (adr = MAX_ADDR) : (adr += cacheline) ;
}
/* Wait for L1 cache invalidation to complete */
dsb();
@ -444,7 +464,7 @@ void Xil_DCacheFlushLine(u32 adr)
* @return None.
*
****************************************************************************/
void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len)
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
{
const u32 cacheline = 32U;
u32 opendadr;
@ -458,10 +478,10 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len)
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
opendadr = opstartadr + len;
opstartadr &= ~(cacheline - 1U);
((MAX_ADDR - (u32)adr) < len) ? (opendadr = MAX_ADDR) : (opendadr = adr + len);
adr &= ~(cacheline - 1U);
tempadr = opstartadr;
tempadr = adr;
while (tempadr < opendadr) {
/* Flush L1 Data cache line */
@ -472,7 +492,7 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len)
__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
Reg = tempadr; }
#endif
tempadr += cacheline;
((MAX_ADDR - (u32)tempadr) < cacheline) ? (tempadr = MAX_ADDR) : (tempadr += cacheline);
}
/* Wait for L1 cache clean and invalidation to complete */
dsb();
@ -480,11 +500,11 @@ void Xil_DCacheFlushRange(INTPTR opstartadr, u32 len)
#ifndef USE_AMP
/* Disable Write-back and line fills */
Xil_L2WriteDebugCtrl(0x3U);
while ((u32)opstartadr < opendadr) {
while ((u32)adr < opendadr) {
/* Flush L2 cache line */
*L2CCOffset = opstartadr;
*L2CCOffset = adr;
Xil_L2CacheSync();
opstartadr += cacheline;
((MAX_ADDR - (u32)adr) < cacheline) ? (adr = MAX_ADDR) : (adr += cacheline);
}
Xil_L2WriteDebugCtrl(0x0U);
#endif
@ -627,7 +647,7 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
while (LocalAddr < end) {
@ -645,7 +665,7 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
Reg = LocalAddr; }
#endif
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline) ;
}
/* Wait for L1 I cache invalidation to complete */
dsb();
@ -860,7 +880,7 @@ void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
while (LocalAddr < end) {
@ -872,7 +892,7 @@ void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
Reg = LocalAddr; }
#endif
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline);
}
/* Wait for L1 cache invalidation to complete */
@ -1006,7 +1026,7 @@ void Xil_L1DCacheFlushRange(u32 adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
while (LocalAddr < end) {
@ -1018,7 +1038,7 @@ void Xil_L1DCacheFlushRange(u32 adr, u32 len)
__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
Reg = LocalAddr; }
#endif
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline);
}
/* Wait for L1 cache clean and invalidation to complete */
@ -1182,7 +1202,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
while (LocalAddr < end) {
@ -1194,7 +1214,7 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
Reg = LocalAddr; }
#endif
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline);
}
/* Wait for L1 cache invalidation to complete */
@ -1378,7 +1398,7 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
/* Disable Write-back and line fills */
@ -1387,7 +1407,7 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
while (LocalAddr < end) {
*L2CCOffset = LocalAddr;
Xil_L2CacheSync();
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline);
}
/* Enable Write-back and line fills */
@ -1489,7 +1509,7 @@ void Xil_L2CacheFlushRange(u32 adr, u32 len)
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
((MAX_ADDR - LocalAddr) < len) ? (end = MAX_ADDR) : (end = LocalAddr + len);
LocalAddr = LocalAddr & ~(cacheline - 1U);
/* Disable Write-back and line fills */
@ -1498,7 +1518,7 @@ void Xil_L2CacheFlushRange(u32 adr, u32 len)
while (LocalAddr < end) {
*L2CCOffset = LocalAddr;
Xil_L2CacheSync();
LocalAddr += cacheline;
((MAX_ADDR - LocalAddr) < cacheline) ? (LocalAddr = MAX_ADDR) : (LocalAddr += cacheline);
}
/* Enable Write-back and line fills */

4
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cache.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -26,6 +27,7 @@
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
* APIs.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* 9.0 ml 03/03/23 Updated function prototypes.
* </pre>
*
******************************************************************************/

50
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_cryptoalginfo.h Normal file
View File

@ -0,0 +1,50 @@
/******************************************************************************/
/**
* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_cryptoalginfo.h
* @{
* @details
*
* Crypto algotithm information structure declaration.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 9.0 mmd 07/04/23 First release.
* </pre>
*
*****************************************************************************/
#ifndef XIL_CRYPTOALGINFO_H
#define XIL_CRYPTOALGINFO_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/**************************** Type Definitions *******************************/
typedef enum _Xil_CryptoAlgNistStatus {
NOT_APPLICABLE = 0x00,
NIST_COMPLIANT = 0x11,
NIST_NON_COMPLIANT = 0xFE,
} Xil_CryptoAlgNistStatus;
typedef struct _Xil_CryptoAlgInfo {
u32 Version;
Xil_CryptoAlgNistStatus NistStatus;
} Xil_CryptoAlgInfo;
#ifdef __cplusplus
}
#endif
#endif /* XIL_CRYPTOALGINFO_H */

32
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.c
View File

@ -1,7 +1,6 @@
/******************************************************************************
* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -44,10 +43,11 @@
* file to fix misra_c_2012_rule_5_6 violation.
* 8.1 asa 02/12/23 Updated data abort and prefetch abort fault
* status reporting for ARMv7.
* Updated Sync and SError fault status reporting
* for ARMv8.
*
*
* Updated Sync and SError fault status reporting
* for ARMv8.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* 9.0 ml 14/04/23 Add comment to default case in switch statement to fix
* misra-c violation.
* </pre>
*
*****************************************************************************/
@ -159,14 +159,14 @@ void Xil_ExceptionInit(void)
/*****************************************************************************/
/**
* @brief Register a handler for a specific exception. This handler is being
* called when the processor encounters the specified exception.
* called when the processor encounters the specified exception.
*
* @param Exception_id contains the ID of the exception source and should
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
* See xil_exception.h for further information.
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
* See xil_exception.h for further information.
* @param Handler to the Handler for that exception.
* @param Data is a reference to Data that will be passed to the
* Handler when it gets called.
* Handler when it gets called.
*
* @return None.
*
@ -175,7 +175,7 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data)
{
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
{
/*
@ -209,7 +209,7 @@ void Xil_GetExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler *Handler,
void **Data)
{
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
{
/*
@ -229,12 +229,12 @@ void Xil_GetExceptionRegisterHandler(u32 Exception_id,
/*****************************************************************************/
/**
*
* @brief Removes the Handler for a specific exception Id. The stub Handler
* is then registered for this exception Id.
* @brief Removes the Handler for a specific exception id. The stub Handler
* is then registered for this exception id.
*
* @param Exception_id contains the ID of the exception source and should
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
* See xil_exception.h for further information.
* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
* See xil_exception.h for further information.
*
* @return None.
*
@ -852,6 +852,8 @@ static u32 NotifyFaultStatusDetails(u32 Fault_Type, u32 FaultStatus)
break;
#endif
default:
/* if above cases doesn't match, then
default case will execute and terminate a statement sequence */
break;
}

10
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_exception.h
View File

@ -75,8 +75,10 @@
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#include "xdebug.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -228,7 +230,7 @@ extern "C" {
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
#else
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
@ -267,7 +269,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
@ -295,7 +297,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* @note None.
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
#else
@ -315,7 +317,7 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3) || defined(ARMR52)
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always disable FIQ

133
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_io.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -32,12 +33,12 @@
* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
* when -Werror=conversion compiler flag is enabled
* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
*
* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings.
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H /* by using protection macros */
#ifndef XIL_IO_H /**< prevent circular inclusions */
#define XIL_IO_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
@ -63,25 +64,25 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0)
# define DATA_SYNC mbar(1)
# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */
# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */
# else
# define SYNCHRONIZE_IO dmb()
# define INST_SYNC isb()
# define DATA_SYNC dsb()
# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */
# define INST_SYNC isb() /**< Instruction Synchronization Barrier */
# define DATA_SYNC dsb() /**< Data Synchronization Barrier */
# endif
#else
# define SYNCHRONIZE_IO
# define INST_SYNC
# define DATA_SYNC
# define INST_SYNC
# define DATA_SYNC
# define SYNCHRONIZE_IO /**< Data Memory Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline
#define INLINE inline /**< static inline keyword */
#else
#define INLINE __inline
#define INLINE __inline /**<static inline keyword */
#endif
/*****************************************************************************/
@ -91,7 +92,7 @@ extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
@ -109,7 +110,7 @@ static INLINE u8 Xil_In8(UINTPTR Addr)
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
@ -126,7 +127,7 @@ static INLINE u16 Xil_In16(UINTPTR Addr)
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
@ -143,7 +144,7 @@ static INLINE u32 Xil_In32(UINTPTR Addr)
* 64 bit Value read from that address.
*
*
* @param Addr: contains the address to perform the input operation
* @param Addr contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
@ -159,8 +160,8 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr: contains the address to perform the output operation
* @param Value: contains the 8 bit Value to be written at the specified
* @param Addr contains the address to perform the output operation
* @param Value contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
@ -275,7 +276,7 @@ static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
*
* @brief Perform a 16-bit endian conversion.
*
* @param Data: 16 bit value to be converted
* @param Data 16 bit value to be converted
*
* @return 16 bit Data with converted endianness
*
@ -290,7 +291,7 @@ static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
*
* @brief Perform a 32-bit endian conversion.
*
* @param Data: 32 bit value to be converted
* @param Data : 32 bit value to be converted
*
* @return 32 bit data with converted endianness
*
@ -317,42 +318,47 @@ static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# else
# define Xil_In16BE Xil_In16
# define Xil_In32BE Xil_In32
# define Xil_Out16BE Xil_Out16
# define Xil_Out32BE Xil_Out32
# define Xil_Htons(Data) (Data)
# define Xil_Htonl(Data) (Data)
# define Xil_Ntohs(Data) (Data)
# define Xil_Ntohl(Data) (Data)
# define Xil_In16BE Xil_In16 /**< Register Read of 16 Bits in Big Endian */
# define Xil_In32BE Xil_In32 /**< Register Read of 32 Bits in Big Endian */
# define Xil_Out16BE Xil_Out16 /**< Register Write of 16 Bits in Big Endian */
# define Xil_Out32BE Xil_Out32 /**< Register Write of 32 Bits in Big Endian */
# define Xil_Htons(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Htonl(Data) (Data) /**< Endian swap of 32 bits */
# define Xil_Ntohs(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Ntohl(Data) (Data) /**< Endian swap of 32 bits */
#endif
#else
# define Xil_In16LE Xil_In16
# define Xil_In32LE Xil_In32
# define Xil_Out16LE Xil_Out16
# define Xil_Out32LE Xil_Out32
# define Xil_Htons Xil_EndianSwap16
# define Xil_Htonl Xil_EndianSwap32
# define Xil_Ntohs Xil_EndianSwap16
# define Xil_Ntohl Xil_EndianSwap32
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr)
static INLINE u16 Xil_In16BE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Big Endian */
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr)
static INLINE u16 Xil_In16LE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
@ -362,11 +368,16 @@ static INLINE u16 Xil_In16BE(UINTPTR Addr)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr)
static INLINE u32 Xil_In32BE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Big Endian */
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr)
static INLINE u32 Xil_In32LE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 32 Bits in Big Endian.
**********************************************************************************/
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
@ -376,11 +387,16 @@ static INLINE u32 Xil_In32BE(UINTPTR Addr)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Big Endian */
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to write Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
@ -390,11 +406,16 @@ static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Big Endian */
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{

8
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mem.h
View File

@ -1,6 +1,6 @@
/******************************************************************************/
/**
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -23,12 +23,12 @@
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
* 7.0 mus 01/07/19 Add cpp extern macro
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
*****************************************************************************/
#ifndef XIL_MEM_H /* prevent circular inclusions */
#define XIL_MEM_H /* by using protection macros */
#ifndef XIL_MEM_H /**< prevent circular inclusions */
#define XIL_MEM_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {

8
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_misc_psreset_api.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -15,12 +16,13 @@
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
#define XIL_MISC_RESET_H /* by using protection macros */
#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */
#define XIL_MISC_RESET_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {

22
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_mmu.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -31,6 +32,7 @@
* redundant TLB invalidation in the same API at the beginning.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* It fixes CR#1008309.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
* @note
@ -52,8 +54,12 @@
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024 /**< Each TTB descriptor
* covers a 1MB region */
#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
/**< Mask off lower bits of addr */
/************************** Variable Definitions *****************************/
extern u32 MMUTable;
@ -65,8 +71,8 @@ extern u32 MMUTable;
* @brief This function sets the memory attributes for a section covering 1MB
* of memory in the translation table.
*
* @param Addr: 32-bit address for which memory attributes need to be set.
* @param attrib: Attribute for the given memory region. xil_mmu.h contains
* @param Addr 32-bit address for which memory attributes need to be set.
* @param attrib Attribute for the given memory region. xil_mmu.h contains
* definitions of commonly used memory attributes which can be
* utilized for this function.
*
@ -167,11 +173,11 @@ void Xil_DisableMMU(void)
/**
* @brief Memory mapping for Cortex A9 processor.
*
* @param PhysAddr is physical address.
* @param size is size of region.
* @param flags is flags used to set translation table.
* @param PhysAddr is physical address.
* @param size is size of region.
* @param flags is flags used to set translation table.
*
* @return Pointer to virtual address.
* @return Pointer to virtual address.
*
* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
* functionality is specific to A9 processor.

601
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 1995 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 1995 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/*---------------------------------------------------*/
@ -12,24 +13,38 @@
#include "xil_printf.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "bspconfig.h"
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
static void padding( const s32 l_flag,const struct params_s *par);
/************************** Function Prototypes ******************************/
static void padding( const s32 l_flag, const struct params_s *par);
static void outs(const charptr lp, struct params_s *par);
static s32 getnum( charptr* linep);
static s32 getnum( charptr *linep);
/**************************** Type Definitions *******************************/
typedef struct params_s {
s32 len;
s32 num1;
s32 num2;
char8 pad_character;
s32 do_padding;
s32 left_flag;
s32 unsigned_flag;
s32 len; /**< length */
s32 num1; /**< number 1 */
s32 num2; /**< number 2 */
char8 pad_character; /**< pad character */
s32 do_padding; /**< do padding */
s32 left_flag; /**< left flag */
s32 unsigned_flag; /**< unsigned flag */
} params_t;
/***************** Macros (Inline Functions) Definitions *********************/
#if (defined(__MICROBLAZE__)) && (!defined(__arch64__))
#define MICROBLAZE32
#endif
#if (!defined(MICROBLAZE32)) && (!defined(ZYNQMP_R5_FSBL_BSP)) && (!defined(DISABLE_64BIT_PRINT))
#define SUPPORT_64BIT_PRINT
#endif
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
@ -40,107 +55,109 @@ typedef struct params_s {
/*---------------------------------------------------*/
/*---------------------------------------------------*/
/* */
/* This routine puts pad characters into the output */
/* buffer. */
/* */
/*****************************************************************************/
/**
* This routine puts pad characters into the output buffer.
*
******************************************************************************/
static void padding( const s32 l_flag, const struct params_s *par)
{
s32 i;
s32 i;
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i=(par->len);
for (; i<(par->num1); i++) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( par->pad_character);
if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
i = (par->len);
for (; i < (par->num1); i++) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( par->pad_character);
#endif
}
}
}
}
/*---------------------------------------------------*/
/* */
/* This routine moves a string to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
/******************************************************************************/
/**
* This routine moves a string to the output buffer
* as directed by the padding and positioning flags.
*
*******************************************************************************/
static void outs(const charptr lp, struct params_s *par)
{
charptr LocalPtr;
charptr LocalPtr;
LocalPtr = lp;
/* pad on left if needed */
if(LocalPtr != NULL) {
/* pad on left if needed */
if (LocalPtr != NULL) {
par->len = (s32)strlen( LocalPtr);
padding( !(par->left_flag), par);
/* Move string to the buffer */
while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
(par->num2)--;
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte(*LocalPtr);
#endif
LocalPtr += 1;
}
}
/* Pad on right if needed */
/* CR 439175 - elided next stmt. Seemed bogus. */
padding( par->left_flag, par);
}
/* Pad on right if needed */
/* CR 439175 - elided next stmt. Seemed bogus. */
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
/* This routine moves a number to the output buffer */
/* as directed by the padding and positioning flags. */
/* */
/*****************************************************************************/
/**
*
* This routine moves a number to the output buffer
* as directed by the padding and positioning flags.
*
******************************************************************************/
static void outnum( const s32 n, const s32 base, struct params_s *par)
{
s32 negative;
s32 negative;
s32 i;
char8 outbuf[32];
const char8 digits[] = "0123456789ABCDEF";
u32 num;
for(i = 0; i<32; i++) {
outbuf[i] = '0';
}
char8 outbuf[32];
const char8 digits[] = "0123456789ABCDEF";
u32 num;
for (i = 0; i < 32; i++) {
outbuf[i] = '0';
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num =(-(n));
}
else{
num = n;
negative = 0;
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num = (-(n));
} else {
num = n;
negative = 0;
}
/* Build number (backwards) in outbuf */
i = 0;
do {
/* Build number (backwards) in outbuf */
i = 0;
do {
outbuf[i] = digits[(num % (u32)base)];
i++;
num /= base;
} while (num > 0U);
} while (num > 0U);
if (negative != 0) {
if (negative != 0) {
outbuf[i] = '-';
i++;
}
outbuf[i] = '\0';
i--;
outbuf[i] = '\0';
i--;
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( outbuf[i] );
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( outbuf[i] );
#endif
i--;
}
padding( par->left_flag, par);
}
padding( par->left_flag, par);
}
/*---------------------------------------------------*/
/* */
@ -148,96 +165,98 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
/* buffer as directed by the padding and positioning */
/* flags. */
/* */
#if defined (__aarch64__) || defined (__arch64__)
#if defined (SUPPORT_64BIT_PRINT)
static void outnum1( const s64 n, const s32 base, params_t *par)
{
s32 negative;
s32 negative;
s32 i;
char8 outbuf[64];
const char8 digits[] = "0123456789ABCDEF";
u64 num;
for(i = 0; i<64; i++) {
outbuf[i] = '0';
}
char8 outbuf[64];
const char8 digits[] = "0123456789ABCDEF";
u64 num;
for (i = 0; i < 64; i++) {
outbuf[i] = '0';
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num =(-(n));
}
else{
num = (n);
negative = 0;
}
/* Check if number is negative */
if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
negative = 1;
num = (-(n));
} else {
num = (n);
negative = 0;
}
/* Build number (backwards) in outbuf */
i = 0;
do {
/* Build number (backwards) in outbuf */
i = 0;
do {
outbuf[i] = digits[(num % base)];
i++;
num /= base;
} while (num > 0);
} while (num > 0);
if (negative != 0) {
if (negative != 0) {
outbuf[i] = '-';
i++;
}
outbuf[i] = '\0';
i--;
outbuf[i] = '\0';
i--;
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
outbyte( outbuf[i] );
/* Move the converted number to the buffer and */
/* add in the padding where needed. */
par->len = (s32)strlen(outbuf);
padding( !(par->left_flag), par);
while (&outbuf[i] >= outbuf) {
outbyte( outbuf[i] );
i--;
}
padding( par->left_flag, par);
}
padding( par->left_flag, par);
}
#endif
/*---------------------------------------------------*/
/* */
/* This routine gets a number from the format */
/* string. */
/* */
static s32 getnum(charptr* linep)
/*****************************************************************************/
/**
*
* This routine gets a number from the format string.
*
******************************************************************************/
static s32 getnum(charptr *linep)
{
s32 n = 0;
s32 ResultIsDigit = 0;
charptr cptr = *linep;
while (cptr != NULL) {
ResultIsDigit = isdigit(((u8)*cptr));
ResultIsDigit = isdigit(((u8) * cptr));
if (ResultIsDigit == 0) {
break;
}
n = ((n*10) + (((s32)*cptr) - (s32)'0'));
n = ((n * 10) + (((s32) * cptr) - (s32)'0'));
cptr += 1;
}
*linep = ((charptr)(cptr));
return(n);
return (n);
}
/*---------------------------------------------------*/
/* */
/* This routine operates just like a printf/sprintf */
/* routine. It outputs a set of data under the */
/* control of a formatting string. Not all of the */
/* standard C format control are supported. The ones */
/* provided are primarily those needed for embedded */
/* systems work. Primarily the floating point */
/* routines are omitted. Other formats could be */
/* added easily by following the examples shown for */
/* the supported formats. */
/* */
/* void esp_printf( const func_ptr f_ptr,
const charptr ctrl1, ...) */
/*****************************************************************************/
/**
* This routine operates just like a printf/sprintf
* routine. It outputs a set of data under the
* control of a formatting string. Not all of the
* standard C format control are supported. The ones
* provided are primarily those needed for embedded
* systems work. Primarily the floating point
* routines are omitted. Other formats could be
* added easily by following the examples shown for
* the supported formats.
* void esp_printf( const func_ptr f_ptr,
* const charptr ctrl1, ...)
*
*******************************************************************************/
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
void xil_printf( const char8 *ctrl1, ...){
void xil_printf( const char8 *ctrl1, ...)
{
XPVXenConsole_Printf(ctrl1);
}
#else
@ -253,195 +272,205 @@ void xil_printf( const char8 *ctrl1, ...)
}
#endif
/* This routine is equivalent to vprintf routine */
/*****************************************************************************/
/**
* This routine is equivalent to vprintf routine
******************************************************************************/
void xil_vprintf(const char8 *ctrl1, va_list argp)
{
s32 Check;
#if defined (__aarch64__) || defined (__arch64__)
s32 long_flag;
#if defined (SUPPORT_64BIT_PRINT)
s32 long_flag;
#endif
s32 dot_flag;
s32 dot_flag;
u32 width, index;
params_t par;
params_t par;
u8 ch;
char8 *ctrl = (char8 *)ctrl1;
const char *string;
u8 ch;
char8 *ctrl = (char8 *)ctrl1;
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
while ((ctrl != NULL) && (*ctrl != (char8)0)) {
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte(*ctrl);
/* move format string chars to buffer until a */
/* format control is found. */
if (*ctrl != '%') {
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte(*ctrl);
#endif
ctrl += 1;
continue;
}
continue;
}
/* initialize all the flags for this format. */
dot_flag = 0;
#if defined (__aarch64__) || defined (__arch64__)
/* initialize all the flags for this format. */
dot_flag = 0;
#if defined (SUPPORT_64BIT_PRINT)
long_flag = 0;
#endif
par.unsigned_flag = 0;
par.unsigned_flag = 0;
par.left_flag = 0;
par.do_padding = 0;
par.pad_character = ' ';
par.num2=32767;
par.num1=0;
par.len=0;
par.pad_character = ' ';
par.num2 = 32767;
par.num1 = 0;
par.len = 0;
try_next:
if(ctrl != NULL) {
try_next:
if (ctrl != NULL) {
ctrl += 1;
}
if(ctrl != NULL) {
ch = (u8)*ctrl;
if (ctrl != NULL) {
ch = (u8) * ctrl;
} else {
break;
}
if (isdigit(ch) != 0) {
if (dot_flag != 0) {
par.num2 = getnum(&ctrl);
}
else {
if (ch == (u8)'0') {
par.pad_character = '0';
if (isdigit(ch) != 0) {
if (dot_flag != 0) {
par.num2 = getnum(&ctrl);
} else {
if (ch == (u8)'0') {
par.pad_character = '0';
}
if(ctrl != NULL) {
par.num1 = getnum(&ctrl);
if (ctrl != NULL) {
par.num1 = getnum(&ctrl);
}
par.do_padding = 1;
}
if(ctrl != NULL) {
ctrl -= 1;
par.do_padding = 1;
}
goto try_next;
}
if (ctrl != NULL) {
ctrl -= 1;
}
goto try_next;
}
switch (tolower(ch)) {
case '%':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( '%');
switch (tolower(ch)) {
case '%':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( '%');
#endif
Check = 1;
break;
case '-':
par.left_flag = 1;
Check = 0;
break;
case '.':
dot_flag = 1;
Check = 0;
break;
case 'l':
#if defined (__aarch64__) || defined (__arch64__)
long_flag = 1;
#endif
Check = 0;
break;
case 'u':
par.unsigned_flag = 1;
/* fall through */
case 'i':
case 'd':
#if defined (__aarch64__) || defined (__arch64__)
if (long_flag != 0){
outnum1((s64)va_arg(argp, s64), 10L, &par);
}
else {
outnum( va_arg(argp, s32), 10L, &par);
}
#else
outnum( va_arg(argp, s32), 10L, &par);
#endif
Check = 1;
break;
case 'p':
#if defined (__aarch64__) || defined (__arch64__)
par.unsigned_flag = 1;
outnum1((s64)va_arg(argp, s64), 16L, &par);
Check = 1;
break;
#endif
case 'X':
case 'x':
par.unsigned_flag = 1;
#if defined (__aarch64__) || defined (__arch64__)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 16L, &par);
break;
case '-':
par.left_flag = 1;
Check = 0;
break;
case '.':
if ((*(ctrl + 1) == '*') && (*(ctrl + 2) == 's')) {
width = va_arg(argp, u32);
string = va_arg(argp, const char *);
for (index = 0; index < width && string[index] != '\0' ; index++) {
outbyte(string[index]);
}
ctrl += 2;
} else {
dot_flag = 1;
Check = 0;
}
else {
outnum((s32)va_arg(argp, s32), 16L, &par);
}
#else
outnum((s32)va_arg(argp, s32), 16L, &par);
#endif
Check = 1;
break;
break;
case 's':
outs( va_arg( argp, char *), &par);
Check = 1;
break;
case 'l':
#if defined (SUPPORT_64BIT_PRINT)
long_flag = 1;
#endif
Check = 0;
break;
case 'c':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( (char8)va_arg( argp, s32));
case 'u':
par.unsigned_flag = 1;
/* fall through */
case 'i':
case 'd':
#if defined (SUPPORT_64BIT_PRINT)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 10L, &par);
} else {
outnum( va_arg(argp, s32), 10L, &par);
}
#else
outnum( va_arg(argp, s32), 10L, &par);
#endif
Check = 1;
break;
Check = 1;
break;
case 'p':
#if defined (__aarch64__) || defined (__arch64__)
par.unsigned_flag = 1;
outnum1((s64)va_arg(argp, s64), 16L, &par);
Check = 1;
break;
#endif
case 'X':
case 'x':
par.unsigned_flag = 1;
#if defined (SUPPORT_64BIT_PRINT)
if (long_flag != 0) {
outnum1((s64)va_arg(argp, s64), 16L, &par);
} else {
outnum((s32)va_arg(argp, s32), 16L, &par);
}
#else
outnum((s32)va_arg(argp, s32), 16L, &par);
#endif
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x07));
#endif
break;
case 'h':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x08));
#endif
break;
case 'r':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x0D));
#endif
break;
case 'n':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
#endif
break;
default:
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
outbyte( *ctrl);
#endif
break;
}
ctrl += 1;
Check = 0;
break;
case 's':
outs( va_arg( argp, char *), &par);
Check = 1;
break;
default:
Check = 1;
break;
}
if(Check == 1) {
if(ctrl != NULL) {
case 'c':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( (char8)va_arg( argp, s32));
#endif
Check = 1;
break;
case '\\':
switch (*ctrl) {
case 'a':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x07));
#endif
break;
case 'h':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x08));
#endif
break;
case 'r':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x0D));
#endif
break;
case 'n':
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( ((char8)0x0D));
outbyte( ((char8)0x0A));
#endif
break;
default:
#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM) || defined(SDT)
outbyte( *ctrl);
#endif
break;
}
ctrl += 1;
Check = 0;
break;
default:
Check = 1;
break;
}
if (Check == 1) {
if (ctrl != NULL) {
ctrl += 1;
}
continue;
}
goto try_next;
}
continue;
}
goto try_next;
}
}
/*---------------------------------------------------*/

16
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_printf.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef XIL_PRINTF_H
@ -13,8 +14,10 @@ extern "C" {
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "xparameters.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
@ -38,13 +41,14 @@ struct params_s;
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/* */
/************************** Function Prototypes ******************************/
/**< prints the statement */
void xil_printf( const char8 *ctrl1, ...);
/**< This routine is equivalent to vprintf routine */
void xil_vprintf(const char8 *ctrl1, va_list argp);
void print( const char8 *ptr);
extern void outbyte (char c);
extern char inbyte(void);
extern void outbyte (char c); /**< To send byte */
extern char inbyte(void); /**< To receive byte */
#ifdef __cplusplus
}

6
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleepcommon.c
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -21,6 +22,7 @@
* violation.
* 8.0 sk 03/02/22 Update usleep argument type to fix misra_c_2012_
* directive_4_6 violation.
* 9.1 mus 10/24/23 Add support for RISC-V.
* </pre>
******************************************************************************/
@ -52,6 +54,8 @@
sleep_A53(seconds);
#elif defined (__MICROBLAZE__)
sleep_MB(seconds);
#elif defined (__riscv)
sleep_riscv(seconds);
#else
sleep_A9(seconds);
#endif
@ -78,6 +82,8 @@
usleep_A53(useconds);
#elif defined (__MICROBLAZE__)
usleep_MB(useconds);
#elif defined (__riscv)
usleep_riscv(useconds);
#else
usleep_A9(useconds);
#endif

11
bsp_z7/ps7_cortexa9_0/libsrc/standalone/src/xil_sleeptimer.h
View File

@ -1,5 +1,6 @@
/******************************************************************************
* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
@ -24,7 +25,7 @@
* misra_c_2012_rule_12_1 violation.
* 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration
* to fix misra_c_2012_rule_8_2 violation.
*
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*****************************************************************************/
@ -103,8 +104,12 @@ extern "C" {
*/
/************************** Function Prototypes ******************************/
/**< This is a helper function used by sleep/usleep APIs to
* have delay in sec/usec */
void Xil_SleepTTCCommon(u32 delay, u64 frequency);
void XTime_StartTTCTimer(void);
void XTime_StartTTCTimer(void); /**< This API starts the Triple
* Timer Counter */
#endif

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