152 Commits

Author SHA1 Message Date
c32c018025 v1
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2024-12-18 14:44:11 +01:00
f904f40f92 v1
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2024-12-18 14:41:58 +01:00
22d2e932a1 v1
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2024-12-18 14:40:45 +01:00
1b81639b27 v1
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2024-12-18 14:39:06 +01:00
99db0b1420 v1
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2024-12-18 14:36:03 +01:00
a9ff327036 ci
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2024-12-18 14:32:18 +01:00
c195ea451f CI
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2024-12-17 15:13:22 +01:00
8cd505dba0 CI
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2024-12-17 15:12:32 +01:00
753beba2f4 CI
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2024-12-17 15:09:41 +01:00
e0242e515d ci workflow and docker files 2024-10-30 22:32:44 +01:00
164b8ed6c2 relative path for lwip submodule mohr_ci v1.2.3 v1.2.4 2024-10-17 15:36:07 +02:00
7e0d346962 documentation 2024-10-17 14:56:32 +02:00
35b951597a corrected commit in lwip submodule 2024-10-17 14:34:08 +02:00
b341a0f7bf using our fork of lwip 2024-10-17 14:20:30 +02:00
d3af5e1519 additional adjustment to xil_eth 2024-10-17 14:00:32 +02:00
242b8e4958 moving FreeRTOS into contrib 2024-10-17 14:00:05 +02:00
6ff33beecc adjusting xil eth to work for us 2024-10-14 14:15:07 +02:00
fd2c5a544f xilinx eth lwip version xilinx_v2024.1 2024-10-14 14:06:49 +02:00
65299e46c4 documentation 2024-10-14 13:36:46 +02:00
fb4b12c8f9 xilinx ps7_cortexa9 code Version xilinx_v2024.1 2024-10-14 13:36:25 +02:00
dd9c39af30 further cleanup 2024-10-10 16:04:18 +02:00
791428e6c0 making the linker happy 2024-10-07 16:55:20 +02:00
944e45cad2 refactoring, added second binary for sim interface, added second lwip implementation for sim interface 2024-09-30 17:38:37 +02:00
8fa5cddc23 cleanup 2024-09-09 17:37:41 +02:00
44ffb09ee9 ps7_init for zedboard
uart0 is 1000000 baud
uart1 is 230400 baud
2024-09-09 16:28:27 +02:00
5ad8853fef uart1 IO 2024-08-29 14:48:16 +02:00
8e7424bb2f io interface; relying on patched lwip 2024-08-26 23:03:38 +02:00
ee06c79bf4 xilinx eth in own folder. found another bug/challenge with dma 2024-08-26 12:03:31 +02:00
8497fe754c cleanup 2024-08-23 12:06:35 +02:00
ae47ca8291 found it. DMA can obviously not handle fragmented pbufs to receive packets. -> debug cleanup needed 2024-08-22 18:14:51 +02:00
497e380860 RX working, still a bit messy 2024-08-20 22:38:02 +02:00
6c556b8fbf better, not done 2024-08-20 15:13:03 +02:00
2d8d8aeb0a working on RX, broke FreeRTOS 2024-08-20 11:26:27 +02:00
910553df45 added xilinx lwip drivers, outgoing is working incoming TODO 2024-08-19 16:52:10 +02:00
fe5629fa85 switched to UDP from UNIX Socket 2024-08-02 01:05:11 +02:00
926ef26000 z7 uart0 buffered read 2024-07-23 17:08:11 +02:00
cbe8184fab portable device access api based on unix file descriptors 2024-07-20 00:27:24 +02:00
49c19ba675 procmac to not forget writing open calls 2024-07-16 23:11:38 +02:00
02a7d525be Using write() for output for better portability 2024-07-16 14:12:15 +02:00
716fdd7fa0 Merge branch 'mohr/rust' 2024-07-12 16:57:48 +02:00
976e079d02 added freeRTOS on linux build 2024-07-12 16:56:31 +02:00
paul nehlich
c3ae428da7 Readme minor update 2024-07-11 14:06:05 +02:00
paul nehlich
f2b3319973 Tutorial minor change 2024-07-11 13:53:54 +02:00
paul nehlich
5707c9f8ae Docker Tutorial updated (by Andy, just pasting it here) 2024-06-26 16:23:02 +02:00
a7336c7f75 handling failed freeRTOS assertion as panic 2024-06-25 13:19:31 +02:00
c9a81c025f removed unused fsfw submodule file 2024-06-25 13:19:19 +02:00
paul nehlich
5c9df20ed1 Should build now, sorry 2024-06-25 12:12:09 +02:00
paul nehlich
af95ae60b1 Merge branch 'main' of egit.irs.uni-stuttgart.de:romeo/obsw 2024-06-17 12:39:26 +02:00
paul nehlich
6eec534116 Added submodule to provide zedboard fsbl 2024-06-17 12:39:12 +02:00
2aec6c3931 BUILD_WITH_CMAKE.md aktualisiert 2024-06-17 12:30:38 +02:00