prep patch v0.5.2

CHANGELOG.md

@@ -6,6 +6,13 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
+## [v0.5.2] 2024-06-16
+
+## Fixed
+
+- Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
+  compilers.
+
 ## [v0.5.1]
 
 ### Changes

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.5.1"
+version = "0.5.2"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -16,7 +16,7 @@ cortex-m = "0.7"
 cortex-m-rt = "0.7"
 nb = "1"
 paste = "1.0"
-libm = "0.2.2"
+libm = "0.2"
 
 [dependencies.embedded-hal]
 version = "0.2.7"
@@ -27,7 +27,7 @@ version = "1.0"
 default-features = false
 
 [dependencies.once_cell]
-version = "1.12.0"
+version = "1.14"
 default-features = false
 
 [features]

README.md

@@ -63,7 +63,7 @@ is contained within the
 
 1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
 2. Create a new binary crate with `cargo init`
-3. To ensure that `cargo build` cross-compiles, it is recommended to create a `cargo/config.toml`
+3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml`
    file. A sample `.cargo/config.toml` file is provided in this repository as well
 4. Copy the `memory.x` file into your project. This file contains information required by the linker.
 5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate

automation/Dockerfile

@@ -7,5 +7,7 @@ RUN apt-get --yes upgrade
 # tzdata is a dependency, won't install otherwise
 ARG DEBIAN_FRONTEND=noninteractive
 
-RUN rustup target add thumbv6m-none-eabi && \
+RUN rustup install nightly && \
+	rustup target add thumbv6m-none-eabi && \
+	rustup +nightly target add thumbv6m-none-eabi && \
 	rustup component add rustfmt clippy

automation/Jenkinsfile

@@ -1,47 +1,34 @@
 pipeline {
-    agent any
+    agent {
+        dockerfile {
+            dir 'automation'
+            reuseNode true
+        }
+    }
+
 
     stages {
         stage('Clippy') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo clippy'
             }
         }
         stage('Rustfmt') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo fmt'
             }
         }
-        stage('Check') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
+        stage('Docs') {
+            steps {
+                sh 'cargo +nightly doc'
             }
+        }
+        stage('Check') {
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi'
             }
         }
         stage('Check Examples') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi --examples'
             }

src/gpio/dynpins.rs

@@ -150,7 +150,7 @@ pub enum DynGroup {
 }
 
 /// Value-level `struct` representing pin IDs
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub struct DynPinId {
     pub group: DynGroup,
     pub num: u8,

src/i2c.rs

@@ -119,14 +119,14 @@ impl TimingCfg {
     }
 
     pub fn reg(&self) -> u32 {
-        ((self.tbuf as u32) << 28
+        (self.tbuf as u32) << 28
             | (self.thd_sta as u32) << 24
             | (self.tsu_sta as u32) << 20
             | (self.tsu_sto as u32) << 16
             | (self.tlow as u32) << 12
             | (self.thigh as u32) << 8
             | (self.tf as u32) << 4
-            | (self.tr as u32)) as u32
+            | (self.tr as u32)
     }
 }
 

src/uart.rs

@@ -354,7 +354,7 @@ impl<UART: Instance> UartBase<UART> {
         };
         let x = sys_clk.0 as f32 / (config.baudrate.0 * baud_multiplier) as f32;
         let integer_part = floorf(x) as u32;
-        let frac = floorf((64.0 * (x - integer_part as f32) + 0.5) as f32) as u32;
+        let frac = floorf(64.0 * (x - integer_part as f32) + 0.5) as u32;
         self.uart
             .clkscale
             .write(|w| unsafe { w.bits(integer_part * 64 + frac) });
@@ -900,11 +900,10 @@ impl<UART: Instance> serial::Write<u8> for Tx<UART> {
             return Err(nb::Error::WouldBlock);
         } else {
             // DPARITY bit not supported yet
+            // NOTE(unsafe) atomic write to data register
             unsafe {
                 // NOTE(unsafe) atomic write to data register
-                // NOTE(write_volatile) 8-bit write that's not
-                // possible through the svd2rust API
-                ptr::write_volatile(&(*UART::ptr()).data as *const _ as *mut _, word);
+                (*UART::ptr()).data.write(|w| w.bits(word as u32));
             }
         }
         Ok(())