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v0.4.2
Author | SHA1 | Date | |
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87b0180e6f | |||
f39863e59f | |||
fb158caf6e | |||
3fc8ce519a | |||
2ad405d325 | |||
063a7a56e5 | |||
1db363fe1a | |||
659b7e8f27 |
25
CHANGELOG.md
25
CHANGELOG.md
@ -6,6 +6,31 @@ All notable changes to this project will be documented in this file.
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|||||||
The format is based on [Keep a Changelog](http://keepachangelog.com/)
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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## [v0.4.2]
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### Added
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- `port_mux` function to set pin function select manually
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### Changed
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- Clear TX and RX FIFO in SPI transfer function
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## [v0.4.1]
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### Fixed
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- Initial blockmode setting was not set in SPI constructor
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## [v0.4.0]
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### Changed
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- Replaced `Hertz` by `impl Into<Hertz>` completely and removed
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`+ Copy` where not necessary
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## [v0.3.1]
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## [v0.3.1]
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- Updated all links to point to new repository
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- Updated all links to point to new repository
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@ -1,6 +1,6 @@
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[package]
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[package]
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name = "va108xx-hal"
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name = "va108xx-hal"
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version = "0.3.1"
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version = "0.4.2"
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
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edition = "2021"
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edition = "2021"
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description = "HAL for the Vorago VA108xx family of microcontrollers"
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description = "HAL for the Vorago VA108xx family of microcontrollers"
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@ -114,12 +114,8 @@ fn main() -> ! {
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match SPI_BUS_SEL {
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match SPI_BUS_SEL {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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let transfer_cfg = TransferConfig::new_no_hw_cs(
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let transfer_cfg =
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SPI_SPEED_KHZ.khz().into(),
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TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.khz(), SPI_MODE, BLOCKMODE, false);
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SPI_MODE,
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BLOCKMODE,
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false,
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);
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spi.cfg_transfer(&transfer_cfg);
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spi.cfg_transfer(&transfer_cfg);
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}
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}
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}
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}
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@ -127,7 +123,7 @@ fn main() -> ! {
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if let Some(ref mut spi) = *spib_ref.borrow_mut() {
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if let Some(ref mut spi) = *spib_ref.borrow_mut() {
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let hw_cs_pin = pinsb.pb2.into_funsel_1();
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let hw_cs_pin = pinsb.pb2.into_funsel_1();
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let transfer_cfg = TransferConfig::new(
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let transfer_cfg = TransferConfig::new(
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SPI_SPEED_KHZ.khz().into(),
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SPI_SPEED_KHZ.khz(),
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SPI_MODE,
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SPI_MODE,
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Some(hw_cs_pin),
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Some(hw_cs_pin),
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BLOCKMODE,
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BLOCKMODE,
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@ -25,7 +25,7 @@ fn main() -> ! {
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(tx, rx),
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(tx, rx),
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115200.bps(),
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115200.bps(),
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&mut dp.SYSCONFIG,
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&mut dp.SYSCONFIG,
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50.mhz().into(),
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50.mhz(),
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);
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);
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let (mut tx, mut rx) = uartb.split();
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let (mut tx, mut rx) = uartb.split();
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writeln!(tx, "Hello World\r").unwrap();
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writeln!(tx, "Hello World\r").unwrap();
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@ -57,14 +57,17 @@
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//! operation, the trait functions will return
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//! operation, the trait functions will return
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//! [`InvalidPinType`](PinError::InvalidPinType).
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//! [`InvalidPinType`](PinError::InvalidPinType).
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use super::pins::{
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use super::{
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common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
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pins::{
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PinMode, PinState,
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common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
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PinMode, PinState,
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},
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reg::RegisterInterface,
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};
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};
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use super::reg::RegisterInterface;
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use crate::{
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use crate::{
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clock::FilterClkSel,
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clock::FilterClkSel,
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pac::{self, IRQSEL, SYSCONFIG},
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pac::{self, IRQSEL, SYSCONFIG},
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utility::Funsel,
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};
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};
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use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
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use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
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use paste::paste;
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use paste::paste;
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@ -98,13 +101,7 @@ pub enum DynOutput {
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ReadableOpenDrain,
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ReadableOpenDrain,
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}
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}
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/// Value-level `enum` for alternate peripheral function configurations
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pub type DynAlternate = Funsel;
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#[derive(PartialEq, Eq, Clone, Copy)]
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pub enum DynAlternate {
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Funsel1,
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Funsel2,
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Funsel3,
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}
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//==================================================================================================
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//==================================================================================================
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// DynPinMode
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// DynPinMode
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@ -60,18 +60,7 @@ impl From<DynPinMode> for ModeFields {
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}
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}
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}
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}
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Alternate(config) => {
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Alternate(config) => {
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use dynpins::DynAlternate::*;
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fields.funsel = config as u8;
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match config {
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Funsel1 => {
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fields.funsel = 1;
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}
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Funsel2 => {
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fields.funsel = 2;
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}
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Funsel3 => {
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fields.funsel = 3;
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}
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}
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}
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}
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}
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}
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fields
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fields
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@ -231,7 +231,7 @@ macro_rules! i2c_base {
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impl I2cBase<$I2CX> {
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impl I2cBase<$I2CX> {
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pub fn $i2cx(
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pub fn $i2cx(
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i2c: $I2CX,
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i2c: $I2CX,
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sys_clk: impl Into<Hertz> + Copy,
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sys_clk: impl Into<Hertz>,
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speed_mode: I2cSpeed,
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speed_mode: I2cSpeed,
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ms_cfg: Option<&MasterConfig>,
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ms_cfg: Option<&MasterConfig>,
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sl_cfg: Option<&SlaveConfig>,
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sl_cfg: Option<&SlaveConfig>,
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@ -740,7 +740,7 @@ macro_rules! i2c_slave {
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fn $i2cx_slave(
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fn $i2cx_slave(
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i2c: $I2CX,
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i2c: $I2CX,
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cfg: SlaveConfig,
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cfg: SlaveConfig,
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sys_clk: impl Into<Hertz> + Copy,
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sys_clk: impl Into<Hertz>,
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speed_mode: I2cSpeed,
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speed_mode: I2cSpeed,
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sys_cfg: Option<&mut SYSCONFIG>,
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sys_cfg: Option<&mut SYSCONFIG>,
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) -> Self {
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) -> Self {
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@ -897,7 +897,7 @@ macro_rules! i2c_slave {
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pub fn i2ca(
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pub fn i2ca(
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i2c: $I2CX,
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i2c: $I2CX,
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cfg: SlaveConfig,
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cfg: SlaveConfig,
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sys_clk: impl Into<Hertz> + Copy,
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sys_clk: impl Into<Hertz>,
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speed_mode: I2cSpeed,
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speed_mode: I2cSpeed,
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sys_cfg: Option<&mut SYSCONFIG>,
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sys_cfg: Option<&mut SYSCONFIG>,
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) -> Result<Self, Error> {
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) -> Result<Self, Error> {
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@ -912,7 +912,7 @@ macro_rules! i2c_slave {
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pub fn $i2cx(
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pub fn $i2cx(
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i2c: $I2CX,
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i2c: $I2CX,
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cfg: SlaveConfig,
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cfg: SlaveConfig,
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sys_clk: impl Into<Hertz> + Copy,
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sys_clk: impl Into<Hertz>,
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speed_mode: I2cSpeed,
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speed_mode: I2cSpeed,
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sys_cfg: Option<&mut SYSCONFIG>,
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sys_cfg: Option<&mut SYSCONFIG>,
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) -> Self {
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) -> Self {
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28
src/spi.rs
28
src/spi.rs
@ -218,9 +218,9 @@ pub struct ReducedTransferConfig {
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}
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}
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impl TransferConfig<NoneT> {
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impl TransferConfig<NoneT> {
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pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
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pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
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TransferConfig {
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TransferConfig {
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spi_clk,
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spi_clk: spi_clk.into(),
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mode,
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mode,
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hw_cs: None,
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hw_cs: None,
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sod,
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sod,
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@ -231,14 +231,14 @@ impl TransferConfig<NoneT> {
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impl<HWCS: HwCs> TransferConfig<HWCS> {
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impl<HWCS: HwCs> TransferConfig<HWCS> {
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pub fn new(
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pub fn new(
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spi_clk: Hertz,
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spi_clk: impl Into<Hertz>,
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mode: Mode,
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mode: Mode,
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hw_cs: Option<HWCS>,
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hw_cs: Option<HWCS>,
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blockmode: bool,
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blockmode: bool,
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sod: bool,
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sod: bool,
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) -> Self {
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) -> Self {
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TransferConfig {
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TransferConfig {
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spi_clk,
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spi_clk: spi_clk.into(),
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mode,
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mode,
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hw_cs,
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hw_cs,
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sod,
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sod,
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@ -428,6 +428,7 @@ macro_rules! spi {
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w.sod().bit(sod);
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w.sod().bit(sod);
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w.ms().bit(ms);
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w.ms().bit(ms);
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w.mdlycap().bit(mdlycap);
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w.mdlycap().bit(mdlycap);
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w.blockmode().bit(init_blockmode);
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unsafe { w.ss().bits(ss) }
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unsafe { w.ss().bits(ss) }
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});
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});
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@ -452,7 +453,7 @@ macro_rules! spi {
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}
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}
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#[inline]
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#[inline]
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pub fn cfg_clock(&mut self, spi_clk: Hertz) {
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pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
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self.spi_base.cfg_clock(spi_clk);
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self.spi_base.cfg_clock(spi_clk);
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}
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}
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|
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@ -482,8 +483,8 @@ macro_rules! spi {
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impl<WORD: Word> SpiBase<$SPIX, WORD> {
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impl<WORD: Word> SpiBase<$SPIX, WORD> {
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#[inline]
|
#[inline]
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pub fn cfg_clock(&mut self, spi_clk: Hertz) {
|
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
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let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
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let clk_prescale = self.sys_clk.0 / (spi_clk.into().0 * (self.cfg.scrdv as u32 + 1));
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self.spi
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self.spi
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.clkprescale
|
.clkprescale
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.write(|w| unsafe { w.bits(clk_prescale) });
|
.write(|w| unsafe { w.bits(clk_prescale) });
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@ -503,6 +504,16 @@ macro_rules! spi {
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});
|
});
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}
|
}
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|
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|
#[inline]
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pub fn clear_tx_fifo(&self) {
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self.spi.fifo_clr.write(|w| w.txfifo().set_bit());
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|
}
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|
|
||||||
|
#[inline]
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|
pub fn clear_rx_fifo(&self) {
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|
self.spi.fifo_clr.write(|w| w.rxfifo().set_bit());
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|
}
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|
|
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#[inline]
|
#[inline]
|
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pub fn perid(&self) -> u32 {
|
pub fn perid(&self) -> u32 {
|
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self.spi.perid.read().bits()
|
self.spi.perid.read().bits()
|
||||||
@ -639,6 +650,9 @@ macro_rules! spi {
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// FIFO has a depth of 16.
|
// FIFO has a depth of 16.
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const FILL_DEPTH: usize = 12;
|
const FILL_DEPTH: usize = 12;
|
||||||
|
|
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|
self.clear_tx_fifo();
|
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|
self.clear_rx_fifo();
|
||||||
|
|
||||||
if self.blockmode {
|
if self.blockmode {
|
||||||
self.spi.ctrl1.modify(|_, w| {
|
self.spi.ctrl1.modify(|_, w| {
|
||||||
w.mtxpause().set_bit()
|
w.mtxpause().set_bit()
|
||||||
|
@ -306,12 +306,12 @@ macro_rules! uart_impl {
|
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pins: PINS,
|
pins: PINS,
|
||||||
config: impl Into<Config>,
|
config: impl Into<Config>,
|
||||||
syscfg: &mut SYSCONFIG,
|
syscfg: &mut SYSCONFIG,
|
||||||
sys_clk: Hertz
|
sys_clk: impl Into<Hertz>
|
||||||
) -> Self
|
) -> Self
|
||||||
{
|
{
|
||||||
enable_peripheral_clock(syscfg, $clk_enb_enum);
|
enable_peripheral_clock(syscfg, $clk_enb_enum);
|
||||||
Uart { uart, pins, tx: Tx::new(), rx: Rx::new() }.init(
|
Uart { uart, pins, tx: Tx::new(), rx: Rx::new() }.init(
|
||||||
config.into(), sys_clk
|
config.into(), sys_clk.into()
|
||||||
)
|
)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -3,11 +3,25 @@
|
|||||||
//! Some more information about the recommended scrub rates can be found on the
|
//! Some more information about the recommended scrub rates can be found on the
|
||||||
//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
|
//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
|
||||||
//! application note AN1212
|
//! application note AN1212
|
||||||
use va108xx::SYSCONFIG;
|
use va108xx::{IOCONFIG, SYSCONFIG};
|
||||||
|
|
||||||
#[derive(PartialEq, Debug)]
|
#[derive(PartialEq, Debug)]
|
||||||
pub enum UtilityError {
|
pub enum UtilityError {
|
||||||
InvalidCounterResetVal,
|
InvalidCounterResetVal,
|
||||||
|
InvalidPin,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Debug, Eq, Copy, Clone, PartialEq)]
|
||||||
|
pub enum Funsel {
|
||||||
|
Funsel1 = 0b01,
|
||||||
|
Funsel2 = 0b10,
|
||||||
|
Funsel3 = 0b11,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Debug, Copy, Clone, PartialEq)]
|
||||||
|
pub enum PortSel {
|
||||||
|
PortA,
|
||||||
|
PortB,
|
||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Copy, Clone, PartialEq)]
|
#[derive(Copy, Clone, PartialEq)]
|
||||||
@ -72,3 +86,28 @@ pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
|
|||||||
.peripheral_reset
|
.peripheral_reset
|
||||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Can be used to manually manipulate the function select of port pins
|
||||||
|
pub fn port_mux(
|
||||||
|
ioconfig: &mut IOCONFIG,
|
||||||
|
port: PortSel,
|
||||||
|
pin: u8,
|
||||||
|
funsel: Funsel,
|
||||||
|
) -> Result<(), UtilityError> {
|
||||||
|
match port {
|
||||||
|
PortSel::PortA => {
|
||||||
|
if pin > 31 {
|
||||||
|
return Err(UtilityError::InvalidPin);
|
||||||
|
}
|
||||||
|
ioconfig.porta[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
PortSel::PortB => {
|
||||||
|
if pin > 23 {
|
||||||
|
return Err(UtilityError::InvalidPin);
|
||||||
|
}
|
||||||
|
ioconfig.portb[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Reference in New Issue
Block a user