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Author SHA1 Message Date
87b0180e6f Merge pull request 'HAL update' (#4) from mueller/hal-update into main
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Reviewed-on: #4
2021-12-12 14:39:13 +01:00
f39863e59f bump version
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2021-12-12 14:35:15 +01:00
fb158caf6e HAL update
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- SPI: Clear TX and RX FIFO for transfers
- Added `port_mux` function to manually select function for pins
2021-12-12 14:21:49 +01:00
3fc8ce519a Merge pull request 'SPI Bugfix' (#3) from mueller/spi-bugfix into main
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Reviewed-on: #3
2021-12-11 17:53:11 +01:00
2ad405d325 update changelog, bump to v0.4.1
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2021-12-11 17:46:05 +01:00
063a7a56e5 init blockmode was not set 2021-12-11 17:45:06 +01:00
1db363fe1a Merge pull request 'Replaced Hertz by impl Into<Hertz> completely' (#2) from mueller/impl-into-hertz into main
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Reviewed-on: #2
2021-12-09 23:28:58 +01:00
659b7e8f27 Replaced Hertz by impl Into<Hertz> completely
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2021-12-09 23:19:21 +01:00
10 changed files with 106 additions and 46 deletions

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@ -6,6 +6,31 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.4.2]
### Added
- `port_mux` function to set pin function select manually
### Changed
- Clear TX and RX FIFO in SPI transfer function
## [v0.4.1]
### Fixed
- Initial blockmode setting was not set in SPI constructor
## [v0.4.0]
### Changed
- Replaced `Hertz` by `impl Into<Hertz>` completely and removed
`+ Copy` where not necessary
## [v0.3.1]
- Updated all links to point to new repository

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@ -1,6 +1,6 @@
[package]
name = "va108xx-hal"
version = "0.3.1"
version = "0.4.2"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"

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@ -114,12 +114,8 @@ fn main() -> ! {
match SPI_BUS_SEL {
SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
if let Some(ref mut spi) = *spia_ref.borrow_mut() {
let transfer_cfg = TransferConfig::new_no_hw_cs(
SPI_SPEED_KHZ.khz().into(),
SPI_MODE,
BLOCKMODE,
false,
);
let transfer_cfg =
TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.khz(), SPI_MODE, BLOCKMODE, false);
spi.cfg_transfer(&transfer_cfg);
}
}
@ -127,7 +123,7 @@ fn main() -> ! {
if let Some(ref mut spi) = *spib_ref.borrow_mut() {
let hw_cs_pin = pinsb.pb2.into_funsel_1();
let transfer_cfg = TransferConfig::new(
SPI_SPEED_KHZ.khz().into(),
SPI_SPEED_KHZ.khz(),
SPI_MODE,
Some(hw_cs_pin),
BLOCKMODE,

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@ -25,7 +25,7 @@ fn main() -> ! {
(tx, rx),
115200.bps(),
&mut dp.SYSCONFIG,
50.mhz().into(),
50.mhz(),
);
let (mut tx, mut rx) = uartb.split();
writeln!(tx, "Hello World\r").unwrap();

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@ -57,14 +57,17 @@
//! operation, the trait functions will return
//! [`InvalidPinType`](PinError::InvalidPinType).
use super::pins::{
common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
PinMode, PinState,
use super::{
pins::{
common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
PinMode, PinState,
},
reg::RegisterInterface,
};
use super::reg::RegisterInterface;
use crate::{
clock::FilterClkSel,
pac::{self, IRQSEL, SYSCONFIG},
utility::Funsel,
};
use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
use paste::paste;
@ -98,13 +101,7 @@ pub enum DynOutput {
ReadableOpenDrain,
}
/// Value-level `enum` for alternate peripheral function configurations
#[derive(PartialEq, Eq, Clone, Copy)]
pub enum DynAlternate {
Funsel1,
Funsel2,
Funsel3,
}
pub type DynAlternate = Funsel;
//==================================================================================================
// DynPinMode

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@ -60,18 +60,7 @@ impl From<DynPinMode> for ModeFields {
}
}
Alternate(config) => {
use dynpins::DynAlternate::*;
match config {
Funsel1 => {
fields.funsel = 1;
}
Funsel2 => {
fields.funsel = 2;
}
Funsel3 => {
fields.funsel = 3;
}
}
fields.funsel = config as u8;
}
}
fields

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@ -231,7 +231,7 @@ macro_rules! i2c_base {
impl I2cBase<$I2CX> {
pub fn $i2cx(
i2c: $I2CX,
sys_clk: impl Into<Hertz> + Copy,
sys_clk: impl Into<Hertz>,
speed_mode: I2cSpeed,
ms_cfg: Option<&MasterConfig>,
sl_cfg: Option<&SlaveConfig>,
@ -740,7 +740,7 @@ macro_rules! i2c_slave {
fn $i2cx_slave(
i2c: $I2CX,
cfg: SlaveConfig,
sys_clk: impl Into<Hertz> + Copy,
sys_clk: impl Into<Hertz>,
speed_mode: I2cSpeed,
sys_cfg: Option<&mut SYSCONFIG>,
) -> Self {
@ -897,7 +897,7 @@ macro_rules! i2c_slave {
pub fn i2ca(
i2c: $I2CX,
cfg: SlaveConfig,
sys_clk: impl Into<Hertz> + Copy,
sys_clk: impl Into<Hertz>,
speed_mode: I2cSpeed,
sys_cfg: Option<&mut SYSCONFIG>,
) -> Result<Self, Error> {
@ -912,7 +912,7 @@ macro_rules! i2c_slave {
pub fn $i2cx(
i2c: $I2CX,
cfg: SlaveConfig,
sys_clk: impl Into<Hertz> + Copy,
sys_clk: impl Into<Hertz>,
speed_mode: I2cSpeed,
sys_cfg: Option<&mut SYSCONFIG>,
) -> Self {

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@ -218,9 +218,9 @@ pub struct ReducedTransferConfig {
}
impl TransferConfig<NoneT> {
pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
TransferConfig {
spi_clk,
spi_clk: spi_clk.into(),
mode,
hw_cs: None,
sod,
@ -231,14 +231,14 @@ impl TransferConfig<NoneT> {
impl<HWCS: HwCs> TransferConfig<HWCS> {
pub fn new(
spi_clk: Hertz,
spi_clk: impl Into<Hertz>,
mode: Mode,
hw_cs: Option<HWCS>,
blockmode: bool,
sod: bool,
) -> Self {
TransferConfig {
spi_clk,
spi_clk: spi_clk.into(),
mode,
hw_cs,
sod,
@ -428,6 +428,7 @@ macro_rules! spi {
w.sod().bit(sod);
w.ms().bit(ms);
w.mdlycap().bit(mdlycap);
w.blockmode().bit(init_blockmode);
unsafe { w.ss().bits(ss) }
});
@ -452,7 +453,7 @@ macro_rules! spi {
}
#[inline]
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
self.spi_base.cfg_clock(spi_clk);
}
@ -482,8 +483,8 @@ macro_rules! spi {
impl<WORD: Word> SpiBase<$SPIX, WORD> {
#[inline]
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
let clk_prescale = self.sys_clk.0 / (spi_clk.into().0 * (self.cfg.scrdv as u32 + 1));
self.spi
.clkprescale
.write(|w| unsafe { w.bits(clk_prescale) });
@ -503,6 +504,16 @@ macro_rules! spi {
});
}
#[inline]
pub fn clear_tx_fifo(&self) {
self.spi.fifo_clr.write(|w| w.txfifo().set_bit());
}
#[inline]
pub fn clear_rx_fifo(&self) {
self.spi.fifo_clr.write(|w| w.rxfifo().set_bit());
}
#[inline]
pub fn perid(&self) -> u32 {
self.spi.perid.read().bits()
@ -639,6 +650,9 @@ macro_rules! spi {
// FIFO has a depth of 16.
const FILL_DEPTH: usize = 12;
self.clear_tx_fifo();
self.clear_rx_fifo();
if self.blockmode {
self.spi.ctrl1.modify(|_, w| {
w.mtxpause().set_bit()

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@ -306,12 +306,12 @@ macro_rules! uart_impl {
pins: PINS,
config: impl Into<Config>,
syscfg: &mut SYSCONFIG,
sys_clk: Hertz
sys_clk: impl Into<Hertz>
) -> Self
{
enable_peripheral_clock(syscfg, $clk_enb_enum);
Uart { uart, pins, tx: Tx::new(), rx: Rx::new() }.init(
config.into(), sys_clk
config.into(), sys_clk.into()
)
}
}

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@ -3,11 +3,25 @@
//! Some more information about the recommended scrub rates can be found on the
//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
//! application note AN1212
use va108xx::SYSCONFIG;
use va108xx::{IOCONFIG, SYSCONFIG};
#[derive(PartialEq, Debug)]
pub enum UtilityError {
InvalidCounterResetVal,
InvalidPin,
}
#[derive(Debug, Eq, Copy, Clone, PartialEq)]
pub enum Funsel {
Funsel1 = 0b01,
Funsel2 = 0b10,
Funsel3 = 0b11,
}
#[derive(Debug, Copy, Clone, PartialEq)]
pub enum PortSel {
PortA,
PortB,
}
#[derive(Copy, Clone, PartialEq)]
@ -72,3 +86,28 @@ pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
.peripheral_reset
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
}
/// Can be used to manually manipulate the function select of port pins
pub fn port_mux(
ioconfig: &mut IOCONFIG,
port: PortSel,
pin: u8,
funsel: Funsel,
) -> Result<(), UtilityError> {
match port {
PortSel::PortA => {
if pin > 31 {
return Err(UtilityError::InvalidPin);
}
ioconfig.porta[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
Ok(())
}
PortSel::PortB => {
if pin > 23 {
return Err(UtilityError::InvalidPin);
}
ioconfig.portb[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
Ok(())
}
}
}