small fix for CI/CD

Reviewed-on: #4

.github/workflows/ci.yml

@@ -16,14 +16,11 @@ jobs:
           override: true
       - uses: actions-rs/cargo@v1
         with:
-          use-cross: true
           command: check
-          args: --target thumbv6m-none-eabi
       - uses: actions-rs/cargo@v1
         with:
-          use-cross: true
           command: check
-          args: --examples --target thumbv6m-none-eabi
+          args: --examples
 
   fmt:
     name: Rustfmt
@@ -55,9 +52,8 @@ jobs:
       - run: rustup component add clippy
       - uses: actions-rs/cargo@v1
         with:
-          use-cross: true
           command: clippy
-          args: --target thumbv6m-none-eabi -- -D warnings
+          args: -- -D warnings
 
   ci:
       if: ${{ success() }}

CHANGELOG.md

@@ -8,6 +8,29 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.4.3]
+
+- Various smaller fixes for READMEs, update of links in documentation
+- Simplified CI for github, do not use `cross`
+- New `blinky-pac` example
+- Use HAL delay in `blinky` example
+
+## [v0.4.2]
+
+### Added
+
+- `port_mux` function to set pin function select manually
+
+### Changed
+
+- Clear TX and RX FIFO in SPI transfer function
+
+## [v0.4.1]
+
+### Fixed
+
+- Initial blockmode setting was not set in SPI constructor
+
 ## [v0.4.0]
 
 ### Changed

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.4.0"
+version = "0.4.3"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -36,10 +36,16 @@ debug = true
 lto = false
 
 [profile.release]
-lto = true
+# Problematic because RTT won't work
+lto = false
 debug = true
 opt-level = "s"
 
+# Commented until named-profiles feature is stabilized
+# [profile.release-lto]
+# inherits = "release"
+# lto = true
+
 [[example]]
 name = "timer-ticks"
 required-features = ["rt"]

README.md

@@ -85,4 +85,4 @@ is contained within the
 
 7. Flashing the board might work differently for different boards and there is usually
    more than one way. You can find example instructions for the REB1 development board
-   [here](https://github.com/robamu-org/vorago-reb1-rs).
+   [here](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1).

examples/blinky-pac.rs

@@ -0,0 +1,47 @@
+//! Blinky examples using only the PAC
+//!
+//! Additional note on LEDs:
+//! Pulling the GPIOs low makes the LEDs blink. See REB1
+//! schematic for more details.
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use panic_halt as _;
+use va108xx as pac;
+
+// REB LED pin definitions. All on port A
+const LED_D2: u32 = 1 << 10;
+const LED_D3: u32 = 1 << 7;
+const LED_D4: u32 = 1 << 6;
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+    // Enable all peripheral clocks
+    dp.SYSCONFIG
+        .peripheral_clk_enable
+        .modify(|_, w| unsafe { w.bits(0xffffffff) });
+    dp.PORTA
+        .dir()
+        .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) });
+    dp.PORTA
+        .datamask()
+        .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) });
+    for _ in 0..10 {
+        dp.PORTA
+            .clrout()
+            .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) });
+        cortex_m::asm::delay(5_000_000);
+        dp.PORTA
+            .setout()
+            .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) });
+        cortex_m::asm::delay(5_000_000);
+    }
+    loop {
+        dp.PORTA
+            .togout()
+            .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) });
+        cortex_m::asm::delay(25_000_000);
+    }
+}

examples/blinky.rs

@@ -9,7 +9,7 @@
 use cortex_m_rt::entry;
 use embedded_hal::digital::v2::ToggleableOutputPin;
 use panic_halt as _;
-use va108xx_hal::{gpio::PinsA, pac, prelude::*};
+use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::set_up_ms_timer};
 
 #[entry]
 fn main() -> ! {
@@ -18,22 +18,29 @@ fn main() -> ! {
     let mut led1 = porta.pa10.into_push_pull_output();
     let mut led2 = porta.pa7.into_push_pull_output();
     let mut led3 = porta.pa6.into_push_pull_output();
+    let mut delay = set_up_ms_timer(
+        &mut dp.SYSCONFIG,
+        &mut dp.IRQSEL,
+        50.mhz().into(),
+        dp.TIM0,
+        pac::Interrupt::OC0,
+    );
     for _ in 0..10 {
         led1.set_low().ok();
         led2.set_low().ok();
         led3.set_low().ok();
-        cortex_m::asm::delay(5_000_000);
+        delay.delay_ms(200_u16);
         led1.set_high().ok();
         led2.set_high().ok();
         led3.set_high().ok();
-        cortex_m::asm::delay(5_000_000);
+        delay.delay_ms(200_u16);
     }
     loop {
         led1.toggle().ok();
-        cortex_m::asm::delay(5_000_000);
+        delay.delay_ms(200_u16);
         led2.toggle().ok();
-        cortex_m::asm::delay(5_000_000);
+        delay.delay_ms(200_u16);
         led3.toggle().ok();
-        cortex_m::asm::delay(5_000_000);
+        delay.delay_ms(200_u16);
     }
 }

src/gpio/dynpins.rs

@@ -57,14 +57,17 @@
 //! operation, the trait functions will return
 //! [`InvalidPinType`](PinError::InvalidPinType).
 
-use super::pins::{
-    common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
-    PinMode, PinState,
+use super::{
+    pins::{
+        common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
+        PinMode, PinState,
+    },
+    reg::RegisterInterface,
 };
-use super::reg::RegisterInterface;
 use crate::{
     clock::FilterClkSel,
     pac::{self, IRQSEL, SYSCONFIG},
+    utility::Funsel,
 };
 use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
 use paste::paste;
@@ -98,13 +101,7 @@ pub enum DynOutput {
     ReadableOpenDrain,
 }
 
-/// Value-level `enum` for alternate peripheral function configurations
-#[derive(PartialEq, Eq, Clone, Copy)]
-pub enum DynAlternate {
-    Funsel1,
-    Funsel2,
-    Funsel3,
-}
+pub type DynAlternate = Funsel;
 
 //==================================================================================================
 //  DynPinMode

src/gpio/reg.rs

@@ -60,18 +60,7 @@ impl From<DynPinMode> for ModeFields {
                 }
             }
             Alternate(config) => {
-                use dynpins::DynAlternate::*;
-                match config {
-                    Funsel1 => {
-                        fields.funsel = 1;
-                    }
-                    Funsel2 => {
-                        fields.funsel = 2;
-                    }
-                    Funsel3 => {
-                        fields.funsel = 3;
-                    }
-                }
+                fields.funsel = config as u8;
             }
         }
         fields

src/i2c.rs

@@ -2,7 +2,7 @@
 //!
 //! ## Examples
 //!
-//! - [REB1 I2C temperature sensor example](https://github.com/robamu-org/vorago-reb1-rs/blob/main/examples/temp-sensor.rs)
+//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/vorago-reb1/src/branch/main/examples/adt75-temp-sensor.rs)
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
     pac::{I2CA, I2CB, SYSCONFIG},

src/spi.rs

@@ -428,6 +428,7 @@ macro_rules! spi {
                         w.sod().bit(sod);
                         w.ms().bit(ms);
                         w.mdlycap().bit(mdlycap);
+                        w.blockmode().bit(init_blockmode);
                         unsafe { w.ss().bits(ss) }
                     });
 
@@ -503,6 +504,16 @@ macro_rules! spi {
                     });
                 }
 
+                #[inline]
+                pub fn clear_tx_fifo(&self) {
+                    self.spi.fifo_clr.write(|w| w.txfifo().set_bit());
+                }
+
+                #[inline]
+                pub fn clear_rx_fifo(&self) {
+                    self.spi.fifo_clr.write(|w| w.rxfifo().set_bit());
+                }
+
                 #[inline]
                 pub fn perid(&self) -> u32 {
                     self.spi.perid.read().bits()
@@ -639,6 +650,9 @@ macro_rules! spi {
                         // FIFO has a depth of 16.
                         const FILL_DEPTH: usize = 12;
 
+                        self.clear_tx_fifo();
+                        self.clear_rx_fifo();
+
                         if self.blockmode {
                             self.spi.ctrl1.modify(|_, w| {
                                 w.mtxpause().set_bit()

src/utility.rs

@@ -3,11 +3,25 @@
 //! Some more information about the recommended scrub rates can be found on the
 //! [Vorago White Paper website](https://www.voragotech.com/resources) in the
 //! application note AN1212
-use va108xx::SYSCONFIG;
+use va108xx::{IOCONFIG, SYSCONFIG};
 
 #[derive(PartialEq, Debug)]
 pub enum UtilityError {
     InvalidCounterResetVal,
+    InvalidPin,
+}
+
+#[derive(Debug, Eq, Copy, Clone, PartialEq)]
+pub enum Funsel {
+    Funsel1 = 0b01,
+    Funsel2 = 0b10,
+    Funsel3 = 0b11,
+}
+
+#[derive(Debug, Copy, Clone, PartialEq)]
+pub enum PortSel {
+    PortA,
+    PortB,
 }
 
 #[derive(Copy, Clone, PartialEq)]
@@ -72,3 +86,28 @@ pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
         .peripheral_reset
         .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
 }
+
+/// Can be used to manually manipulate the function select of port pins
+pub fn port_mux(
+    ioconfig: &mut IOCONFIG,
+    port: PortSel,
+    pin: u8,
+    funsel: Funsel,
+) -> Result<(), UtilityError> {
+    match port {
+        PortSel::PortA => {
+            if pin > 31 {
+                return Err(UtilityError::InvalidPin);
+            }
+            ioconfig.porta[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
+            Ok(())
+        }
+        PortSel::PortB => {
+            if pin > 23 {
+                return Err(UtilityError::InvalidPin);
+            }
+            ioconfig.portb[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
+            Ok(())
+        }
+    }
+}