that should do the job

CHANGELOG.md

@@ -13,7 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Updated dependencies:
   - `cortex-m-rtic` (dev-depencency) to 1.1.2
   - `once_cell` to 1.12.0
-  - Other depencies: Only revision has changed
+  - Other dependencies: Only revision has changed
 
 ## [v0.5.0]
 

Cargo.toml

@@ -16,7 +16,7 @@ cortex-m = "0.7"
 cortex-m-rt = "0.7"
 nb = "1"
 paste = "1.0"
-libm = "0.2.2"
+libm = "0.2"
 
 [dependencies.embedded-hal]
 version = "0.2.7"
@@ -27,7 +27,7 @@ version = "1.0"
 default-features = false
 
 [dependencies.once_cell]
-version = "1.12.0"
+version = "1.14"
 default-features = false
 
 [features]

README.md

@@ -1,5 +1,5 @@
 [![Crates.io](https://img.shields.io/crates/v/va108xx-hal)](https://crates.io/crates/va108xx-hal)
-[![ci](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml)
+[![ci](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml)
 [![docs.rs](https://img.shields.io/docsrs/va108xx-hal)](https://docs.rs/va108xx-hal)
 
 # HAL for the Vorago VA108xx MCU family
@@ -63,7 +63,7 @@ is contained within the
 
 1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
 2. Create a new binary crate with `cargo init`
-3. To ensure that `cargo build` cross-compiles, it is recommended to create a `cargo/config.toml`
+3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml`
    file. A sample `.cargo/config.toml` file is provided in this repository as well
 4. Copy the `memory.x` file into your project. This file contains information required by the linker.
 5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate

automation/Dockerfile

@@ -7,5 +7,7 @@ RUN apt-get --yes upgrade
 # tzdata is a dependency, won't install otherwise
 ARG DEBIAN_FRONTEND=noninteractive
 
-RUN rustup target add thumbv6m-none-eabi && \
+RUN rustup install nightly && \
+	rustup target add thumbv6m-none-eabi && \
+	rustup +nightly target add thumbv6m-none-eabi && \
 	rustup component add rustfmt clippy

automation/Jenkinsfile

@@ -1,47 +1,34 @@
 pipeline {
-    agent any
+    agent {
+        dockerfile {
+            dir 'automation'
+            reuseNode true
+        }
+    }
+
 
     stages {
         stage('Clippy') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo clippy'
             }
         }
         stage('Rustfmt') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo fmt'
             }
         }
-        stage('Check') {
+        stage('Docs') {
-            agent {
+            steps {
-                dockerfile {
+                sh 'cargo +nightly doc'
-                    dir 'automation'
-                    reuseNode true
-                }
             }
+        }
+        stage('Check') {
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi'
             }
         }
         stage('Check Examples') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi --examples'
             }

src/clock.rs

@@ -11,7 +11,7 @@ static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
 
 pub type PeripheralClocks = PeripheralSelect;
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterClkSel {
     SysClk = 0,
     Clk1 = 1,

src/gpio/dynpins.rs

@@ -143,14 +143,14 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Funse
 //==================================================================================================
 
 /// Value-level `enum` for pin groups
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub enum DynGroup {
     A,
     B,
 }
 
 /// Value-level `struct` representing pin IDs
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub struct DynPinId {
     pub group: DynGroup,
     pub num: u8,

src/gpio/pins.rs

@@ -106,27 +106,27 @@ use paste::paste;
 //  Errors and Definitions
 //==================================================================================================
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptEdge {
     HighToLow,
     LowToHigh,
     BothEdges,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptLevel {
     Low = 0,
     High = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinState {
     Low = 0,
     High = 1,
 }
 
 /// GPIO error type
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinError {
     /// The pin did not have the correct ID or mode for the requested operation.
     /// [`DynPin`](crate::gpio::DynPin)s are not tracked and verified at compile-time, so run-time
@@ -182,7 +182,7 @@ pub struct Input<C: InputConfig> {
 
 impl<C: InputConfig> Sealed for Input<C> {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterType {
     SystemClock = 0,
     DirectInputWithSynchronization = 1,

src/i2c.rs

@@ -18,13 +18,13 @@ pub use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress};
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum FifoEmptyMode {
     Stall = 0,
     EndTransaction = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum Error {
     InvalidTimingParams,
     ArbitrationLost,
@@ -46,19 +46,19 @@ enum I2cCmd {
     Cancel = 0b100,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cSpeed {
     Regular100khz = 0,
     Fast400khz = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum I2cDirection {
     Send = 0,
     Read = 1,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cAddress {
     Regular(u8),
     TenBit(u16),
@@ -119,14 +119,14 @@ impl TimingCfg {
     }
 
     pub fn reg(&self) -> u32 {
-        ((self.tbuf as u32) << 28
+        (self.tbuf as u32) << 28
             | (self.thd_sta as u32) << 24
             | (self.tsu_sta as u32) << 20
             | (self.tsu_sto as u32) << 16
             | (self.tlow as u32) << 12
             | (self.thigh as u32) << 8
             | (self.tf as u32) << 4
-            | (self.tr as u32)) as u32
+            | (self.tr as u32)
     }
 }
 

src/spi.rs

@@ -25,7 +25,7 @@ use embedded_hal::{
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum HwChipSelectId {
     Id0 = 0,
     Id1 = 1,
@@ -38,7 +38,7 @@ pub enum HwChipSelectId {
     Invalid = 0xff,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum WordSize {
     OneBit = 0x00,
     FourBits = 0x03,

src/time.rs

@@ -6,7 +6,7 @@
 //! allowing it to be converted into frequencies.
 
 /// Bits per second
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Bps(pub u32);
 
 /// Hertz
@@ -25,7 +25,7 @@ pub struct Bps(pub u32);
 ///
 /// let freq = 60.hz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Hertz(pub u32);
 
 /// Kilohertz
@@ -47,7 +47,7 @@ pub struct Hertz(pub u32);
 ///
 /// let freq = 100.khz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct KiloHertz(pub u32);
 
 /// Megahertz
@@ -68,14 +68,14 @@ pub struct KiloHertz(pub u32);
 ///
 /// let freq = 8.mhz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct MegaHertz(pub u32);
 
 /// Time unit
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MilliSeconds(pub u32);
 
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MicroSeconds(pub u32);
 
 /// Extension trait that adds convenience methods to the `u32` type

src/timer.rs

@@ -45,7 +45,7 @@ pub enum Event {
     TimeOut,
 }
 
-#[derive(Default, Debug, PartialEq, Copy, Clone)]
+#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
 pub struct CascadeCtrl {
     /// Enable Cascade 0 signal active as a requirement for counting
     pub enb_start_src_csd0: bool,
@@ -74,7 +74,7 @@ pub struct CascadeCtrl {
     pub trg_csd2: bool,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSel {
     Csd0 = 0,
     Csd1 = 1,
@@ -82,7 +82,7 @@ pub enum CascadeSel {
 }
 
 /// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSource {
     PortABase = 0,
     PortBBase = 32,
@@ -95,7 +95,7 @@ pub enum CascadeSource {
     ClockDividerBase = 120,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum TimerErrors {
     Canceled,
     /// Invalid input for Cascade source

src/uart.rs

@@ -60,7 +60,7 @@ pub enum Error {
     IrqError,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum Event {
     // Receiver FIFO interrupt enable. Generates interrupt
     // when FIFO is at least half full. Half full is defined as FIFO
@@ -84,20 +84,20 @@ pub enum Event {
     TxCts,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum Parity {
     None,
     Odd,
     Even,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum StopBits {
     One = 0,
     Two = 1,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum WordSize {
     Five = 0,
     Six = 1,
@@ -354,7 +354,7 @@ impl<UART: Instance> UartBase<UART> {
         };
         let x = sys_clk.0 as f32 / (config.baudrate.0 * baud_multiplier) as f32;
         let integer_part = floorf(x) as u32;
-        let frac = floorf((64.0 * (x - integer_part as f32) + 0.5) as f32) as u32;
+        let frac = floorf(64.0 * (x - integer_part as f32) + 0.5) as u32;
         self.uart
             .clkscale
             .write(|w| unsafe { w.bits(integer_part * 64 + frac) });

src/utility.rs

@@ -6,7 +6,7 @@
 use crate::pac;
 use va108xx::{IOCONFIG, SYSCONFIG};
 
-#[derive(PartialEq, Debug)]
+#[derive(PartialEq, Eq, Debug)]
 pub enum UtilityError {
     InvalidCounterResetVal,
     InvalidPin,
@@ -19,13 +19,13 @@ pub enum Funsel {
     Funsel3 = 0b11,
 }
 
-#[derive(Debug, Copy, Clone, PartialEq)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum PortSel {
     PortA,
     PortB,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum PeripheralSelect {
     PortA = 0,
     PortB = 1,
@@ -46,7 +46,7 @@ pub enum PeripheralSelect {
 /// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
 /// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
 /// this steps themselves
-#[derive(Debug, PartialEq, Clone, Copy)]
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
 pub struct IrqCfg {
     /// Interrupt target vector. Should always be set, might be required for disabling IRQs
     pub irq: pac::Interrupt,