First building PAC version

Generated a first building version of the PAC.
The PAC was generated with a specially patched version
of svd2rust 0.19.0: https://github.com/robamu/svd2rust/tree/mueller/develop

Cargo.toml

@@ -0,0 +1,18 @@
+[package]
+name = "va108xx"
+version = "0.1.0"
+edition = "2018"
+description = "Peripheral access API for Vorago VA108XX microcontrollers"
+license = "Apache-2.0 or MIT"
+authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
+
+[dependencies]
+cortex-m = "0.7.3"
+vcell = "0.1.3"
+
+[dependencies.cortex-m-rt]
+optional = true
+version = ">=0.6.15,<0.8"
+
+[features]
+rt = ["cortex-m-rt/device"]

build.rs

@@ -1 +1,16 @@
-use std :: env ; use std :: fs :: File ; use std :: io :: Write ; use std :: path :: PathBuf ; fn main () { if env :: var_os ("CARGO_FEATURE_RT") . is_some () { let out = & PathBuf :: from (env :: var_os ("OUT_DIR") . unwrap ()) ; File :: create (out . join ("device.x")) . unwrap () . write_all (include_bytes ! ("device.x")) . unwrap () ; println ! ("cargo:rustc-link-search={}" , out . display ()) ; println ! ("cargo:rerun-if-changed=device.x") ; } println ! ("cargo:rerun-if-changed=build.rs") ; }
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

src/generic.rs

@@ -0,0 +1,260 @@
+use core::marker;
+#[doc = " Raw register type"]
+pub trait RegisterSpec {
+    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: Copy;
+}
+#[doc = " Trait implemented by readable registers to enable the `read` method."]
+#[doc = ""]
+#[doc = " Registers marked with `Writable` can be also `modify`'ed."]
+pub trait Readable: RegisterSpec {
+    #[doc = " Result from a call to `read` and argument to `modify`."]
+    type Reader: From<R<Self>> + core::ops::Deref<Target = R<Self>>;
+}
+#[doc = " Trait implemented by writeable registers."]
+#[doc = ""]
+#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
+#[doc = ""]
+#[doc = " Registers marked with `Readable` can be also `modify`'ed."]
+pub trait Writable: RegisterSpec {
+    #[doc = " Writer type argument to `write`, et al."]
+    type Writer: From<W<Self>> + core::ops::DerefMut<Target = W<Self>>;
+}
+#[doc = " Reset value of the register."]
+#[doc = ""]
+#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
+#[doc = " register by using the `reset` method."]
+pub trait Resettable: RegisterSpec {
+    #[doc = " Reset value of the register."]
+    fn reset_value() -> Self::Ux;
+}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> REG::Reader {
+        REG::Reader::from(R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        })
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::reset_value())
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut REG::Writer::from(W {
+                bits: REG::reset_value(),
+                _reg: marker::PhantomData,
+            }))
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG>
+where
+    REG::Ux: Default,
+{
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            (*f(&mut REG::Writer::from(W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })))
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&REG::Reader, &'w mut REG::Writer) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &REG::Reader::from(R {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+                &mut REG::Writer::from(W {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+            )
+            .bits,
+        );
+    }
+}
+#[doc = " Register reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
+#[doc = " method."]
+pub struct R<REG: RegisterSpec + ?Sized> {
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> R<REG> {
+    #[doc = " Reads raw bits from register."]
+    #[inline(always)]
+    pub fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy + Into<REG::Ux>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+#[doc = " Register writer."]
+#[doc = ""]
+#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
+pub struct W<REG: RegisterSpec + ?Sized> {
+    #[doc = "Writable bits"]
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> W<REG> {
+    #[doc = " Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = " Field reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of fields."]
+pub struct FieldReader<U, T> {
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<T>,
+}
+impl<U, T> FieldReader<U, T>
+where
+    U: Copy,
+{
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: U) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+    #[doc = " Reads raw bits from field."]
+    #[inline(always)]
+    pub fn bits(&self) -> U {
+        self.bits
+    }
+}
+impl<U, T, FI> PartialEq<FI> for FieldReader<U, T>
+where
+    U: PartialEq,
+    FI: Copy + Into<U>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+impl<FI> FieldReader<bool, FI> {
+    #[doc = " Value of the field as raw bits."]
+    #[inline(always)]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = " Returns `true` if the bit is clear (0)."]
+    #[inline(always)]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = " Returns `true` if the bit is set (1)."]
+    #[inline(always)]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}

src/i2ca.rs

@@ -0,0 +1,240 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Control Register"]
+    pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
+    #[doc = "0x04 - Clock Scale divide value"]
+    pub clkscale: crate::Reg<clkscale::CLKSCALE_SPEC>,
+    #[doc = "0x08 - Word Count value"]
+    pub words: crate::Reg<words::WORDS_SPEC>,
+    #[doc = "0x0c - I2C Address value"]
+    pub address: crate::Reg<address::ADDRESS_SPEC>,
+    #[doc = "0x10 - Data Input/Output"]
+    pub data: crate::Reg<data::DATA_SPEC>,
+    #[doc = "0x14 - Command Register"]
+    pub cmd: crate::Reg<cmd::CMD_SPEC>,
+    #[doc = "0x18 - I2C Controller Status Register"]
+    pub status: crate::Reg<status::STATUS_SPEC>,
+    #[doc = "0x1c - Internal STATE of I2C Master Controller"]
+    pub state: crate::Reg<state::STATE_SPEC>,
+    #[doc = "0x20 - TX Count Register"]
+    pub txcount: crate::Reg<txcount::TXCOUNT_SPEC>,
+    #[doc = "0x24 - RX Count Register"]
+    pub rxcount: crate::Reg<rxcount::RXCOUNT_SPEC>,
+    #[doc = "0x28 - Interrupt Enable Register"]
+    pub irq_enb: crate::Reg<irq_enb::IRQ_ENB_SPEC>,
+    #[doc = "0x2c - Raw Interrupt Status Register"]
+    pub irq_raw: crate::Reg<irq_raw::IRQ_RAW_SPEC>,
+    #[doc = "0x30 - Enabled Interrupt Status Register"]
+    pub irq_end: crate::Reg<irq_end::IRQ_END_SPEC>,
+    #[doc = "0x34 - Clear Interrupt Status Register"]
+    pub irq_clr: crate::Reg<irq_clr::IRQ_CLR_SPEC>,
+    #[doc = "0x38 - Rx FIFO IRQ Trigger Level"]
+    pub rxfifoirqtrg: crate::Reg<rxfifoirqtrg::RXFIFOIRQTRG_SPEC>,
+    #[doc = "0x3c - Tx FIFO IRQ Trigger Level"]
+    pub txfifoirqtrg: crate::Reg<txfifoirqtrg::TXFIFOIRQTRG_SPEC>,
+    #[doc = "0x40 - Clear FIFO Register"]
+    pub fifo_clr: crate::Reg<fifo_clr::FIFO_CLR_SPEC>,
+    #[doc = "0x44 - Timing Config Register"]
+    pub tmconfig: crate::Reg<tmconfig::TMCONFIG_SPEC>,
+    #[doc = "0x48 - Clock Low Timeout Limit Register"]
+    pub clktolimit: crate::Reg<clktolimit::CLKTOLIMIT_SPEC>,
+    _reserved19: [u8; 0xb4],
+    #[doc = "0x100 - Slave Control Register"]
+    pub s0_ctrl: crate::Reg<s0_ctrl::S0_CTRL_SPEC>,
+    #[doc = "0x104 - Slave MaxWords Register"]
+    pub s0_maxwords: crate::Reg<s0_maxwords::S0_MAXWORDS_SPEC>,
+    #[doc = "0x108 - Slave I2C Address Value"]
+    pub s0_address: crate::Reg<s0_address::S0_ADDRESS_SPEC>,
+    #[doc = "0x10c - Slave I2C Address Mask value"]
+    pub s0_addressmask: crate::Reg<s0_addressmask::S0_ADDRESSMASK_SPEC>,
+    #[doc = "0x110 - Slave Data Input/Output"]
+    pub s0_data: crate::Reg<s0_data::S0_DATA_SPEC>,
+    #[doc = "0x114 - Slave I2C Last Address value"]
+    pub s0_lastaddress: crate::Reg<s0_lastaddress::S0_LASTADDRESS_SPEC>,
+    #[doc = "0x118 - Slave I2C Controller Status Register"]
+    pub s0_status: crate::Reg<s0_status::S0_STATUS_SPEC>,
+    #[doc = "0x11c - Internal STATE of I2C Slave Controller"]
+    pub s0_state: crate::Reg<s0_state::S0_STATE_SPEC>,
+    #[doc = "0x120 - Slave TX Count Register"]
+    pub s0_txcount: crate::Reg<s0_txcount::S0_TXCOUNT_SPEC>,
+    #[doc = "0x124 - Slave RX Count Register"]
+    pub s0_rxcount: crate::Reg<s0_rxcount::S0_RXCOUNT_SPEC>,
+    #[doc = "0x128 - Slave Interrupt Enable Register"]
+    pub s0_irq_enb: crate::Reg<s0_irq_enb::S0_IRQ_ENB_SPEC>,
+    #[doc = "0x12c - Slave Raw Interrupt Status Register"]
+    pub s0_irq_raw: crate::Reg<s0_irq_raw::S0_IRQ_RAW_SPEC>,
+    #[doc = "0x130 - Slave Enabled Interrupt Status Register"]
+    pub s0_irq_end: crate::Reg<s0_irq_end::S0_IRQ_END_SPEC>,
+    #[doc = "0x134 - Slave Clear Interrupt Status Register"]
+    pub s0_irq_clr: crate::Reg<s0_irq_clr::S0_IRQ_CLR_SPEC>,
+    #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"]
+    pub s0_rxfifoirqtrg: crate::Reg<s0_rxfifoirqtrg::S0_RXFIFOIRQTRG_SPEC>,
+    #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"]
+    pub s0_txfifoirqtrg: crate::Reg<s0_txfifoirqtrg::S0_TXFIFOIRQTRG_SPEC>,
+    #[doc = "0x140 - Slave Clear FIFO Register"]
+    pub s0_fifo_clr: crate::Reg<s0_fifo_clr::S0_FIFO_CLR_SPEC>,
+    #[doc = "0x144 - Slave I2C Address B Value"]
+    pub s0_addressb: crate::Reg<s0_addressb::S0_ADDRESSB_SPEC>,
+    #[doc = "0x148 - Slave I2C Address B Mask value"]
+    pub s0_addressmaskb: crate::Reg<s0_addressmaskb::S0_ADDRESSMASKB_SPEC>,
+    _reserved38: [u8; 0x0eb0],
+    #[doc = "0xffc - Peripheral ID Register"]
+    pub perid: crate::Reg<perid::PERID_SPEC>,
+}
+#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
+pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
+#[doc = "Control Register"]
+pub mod ctrl;
+#[doc = "CLKSCALE register accessor: an alias for `Reg<CLKSCALE_SPEC>`"]
+pub type CLKSCALE = crate::Reg<clkscale::CLKSCALE_SPEC>;
+#[doc = "Clock Scale divide value"]
+pub mod clkscale;
+#[doc = "WORDS register accessor: an alias for `Reg<WORDS_SPEC>`"]
+pub type WORDS = crate::Reg<words::WORDS_SPEC>;
+#[doc = "Word Count value"]
+pub mod words;
+#[doc = "ADDRESS register accessor: an alias for `Reg<ADDRESS_SPEC>`"]
+pub type ADDRESS = crate::Reg<address::ADDRESS_SPEC>;
+#[doc = "I2C Address value"]
+pub mod address;
+#[doc = "DATA register accessor: an alias for `Reg<DATA_SPEC>`"]
+pub type DATA = crate::Reg<data::DATA_SPEC>;
+#[doc = "Data Input/Output"]
+pub mod data;
+#[doc = "CMD register accessor: an alias for `Reg<CMD_SPEC>`"]
+pub type CMD = crate::Reg<cmd::CMD_SPEC>;
+#[doc = "Command Register"]
+pub mod cmd;
+#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "I2C Controller Status Register"]
+pub mod status;
+#[doc = "STATE register accessor: an alias for `Reg<STATE_SPEC>`"]
+pub type STATE = crate::Reg<state::STATE_SPEC>;
+#[doc = "Internal STATE of I2C Master Controller"]
+pub mod state;
+#[doc = "TXCOUNT register accessor: an alias for `Reg<TXCOUNT_SPEC>`"]
+pub type TXCOUNT = crate::Reg<txcount::TXCOUNT_SPEC>;
+#[doc = "TX Count Register"]
+pub mod txcount;
+#[doc = "RXCOUNT register accessor: an alias for `Reg<RXCOUNT_SPEC>`"]
+pub type RXCOUNT = crate::Reg<rxcount::RXCOUNT_SPEC>;
+#[doc = "RX Count Register"]
+pub mod rxcount;
+#[doc = "IRQ_ENB register accessor: an alias for `Reg<IRQ_ENB_SPEC>`"]
+pub type IRQ_ENB = crate::Reg<irq_enb::IRQ_ENB_SPEC>;
+#[doc = "Interrupt Enable Register"]
+pub mod irq_enb;
+#[doc = "IRQ_RAW register accessor: an alias for `Reg<IRQ_RAW_SPEC>`"]
+pub type IRQ_RAW = crate::Reg<irq_raw::IRQ_RAW_SPEC>;
+#[doc = "Raw Interrupt Status Register"]
+pub mod irq_raw;
+#[doc = "IRQ_END register accessor: an alias for `Reg<IRQ_END_SPEC>`"]
+pub type IRQ_END = crate::Reg<irq_end::IRQ_END_SPEC>;
+#[doc = "Enabled Interrupt Status Register"]
+pub mod irq_end;
+#[doc = "IRQ_CLR register accessor: an alias for `Reg<IRQ_CLR_SPEC>`"]
+pub type IRQ_CLR = crate::Reg<irq_clr::IRQ_CLR_SPEC>;
+#[doc = "Clear Interrupt Status Register"]
+pub mod irq_clr;
+#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg<RXFIFOIRQTRG_SPEC>`"]
+pub type RXFIFOIRQTRG = crate::Reg<rxfifoirqtrg::RXFIFOIRQTRG_SPEC>;
+#[doc = "Rx FIFO IRQ Trigger Level"]
+pub mod rxfifoirqtrg;
+#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg<TXFIFOIRQTRG_SPEC>`"]
+pub type TXFIFOIRQTRG = crate::Reg<txfifoirqtrg::TXFIFOIRQTRG_SPEC>;
+#[doc = "Tx FIFO IRQ Trigger Level"]
+pub mod txfifoirqtrg;
+#[doc = "FIFO_CLR register accessor: an alias for `Reg<FIFO_CLR_SPEC>`"]
+pub type FIFO_CLR = crate::Reg<fifo_clr::FIFO_CLR_SPEC>;
+#[doc = "Clear FIFO Register"]
+pub mod fifo_clr;
+#[doc = "TMCONFIG register accessor: an alias for `Reg<TMCONFIG_SPEC>`"]
+pub type TMCONFIG = crate::Reg<tmconfig::TMCONFIG_SPEC>;
+#[doc = "Timing Config Register"]
+pub mod tmconfig;
+#[doc = "CLKTOLIMIT register accessor: an alias for `Reg<CLKTOLIMIT_SPEC>`"]
+pub type CLKTOLIMIT = crate::Reg<clktolimit::CLKTOLIMIT_SPEC>;
+#[doc = "Clock Low Timeout Limit Register"]
+pub mod clktolimit;
+#[doc = "S0_CTRL register accessor: an alias for `Reg<S0_CTRL_SPEC>`"]
+pub type S0_CTRL = crate::Reg<s0_ctrl::S0_CTRL_SPEC>;
+#[doc = "Slave Control Register"]
+pub mod s0_ctrl;
+#[doc = "S0_MAXWORDS register accessor: an alias for `Reg<S0_MAXWORDS_SPEC>`"]
+pub type S0_MAXWORDS = crate::Reg<s0_maxwords::S0_MAXWORDS_SPEC>;
+#[doc = "Slave MaxWords Register"]
+pub mod s0_maxwords;
+#[doc = "S0_ADDRESS register accessor: an alias for `Reg<S0_ADDRESS_SPEC>`"]
+pub type S0_ADDRESS = crate::Reg<s0_address::S0_ADDRESS_SPEC>;
+#[doc = "Slave I2C Address Value"]
+pub mod s0_address;
+#[doc = "S0_ADDRESSMASK register accessor: an alias for `Reg<S0_ADDRESSMASK_SPEC>`"]
+pub type S0_ADDRESSMASK = crate::Reg<s0_addressmask::S0_ADDRESSMASK_SPEC>;
+#[doc = "Slave I2C Address Mask value"]
+pub mod s0_addressmask;
+#[doc = "S0_DATA register accessor: an alias for `Reg<S0_DATA_SPEC>`"]
+pub type S0_DATA = crate::Reg<s0_data::S0_DATA_SPEC>;
+#[doc = "Slave Data Input/Output"]
+pub mod s0_data;
+#[doc = "S0_LASTADDRESS register accessor: an alias for `Reg<S0_LASTADDRESS_SPEC>`"]
+pub type S0_LASTADDRESS = crate::Reg<s0_lastaddress::S0_LASTADDRESS_SPEC>;
+#[doc = "Slave I2C Last Address value"]
+pub mod s0_lastaddress;
+#[doc = "S0_STATUS register accessor: an alias for `Reg<S0_STATUS_SPEC>`"]
+pub type S0_STATUS = crate::Reg<s0_status::S0_STATUS_SPEC>;
+#[doc = "Slave I2C Controller Status Register"]
+pub mod s0_status;
+#[doc = "S0_STATE register accessor: an alias for `Reg<S0_STATE_SPEC>`"]
+pub type S0_STATE = crate::Reg<s0_state::S0_STATE_SPEC>;
+#[doc = "Internal STATE of I2C Slave Controller"]
+pub mod s0_state;
+#[doc = "S0_TXCOUNT register accessor: an alias for `Reg<S0_TXCOUNT_SPEC>`"]
+pub type S0_TXCOUNT = crate::Reg<s0_txcount::S0_TXCOUNT_SPEC>;
+#[doc = "Slave TX Count Register"]
+pub mod s0_txcount;
+#[doc = "S0_RXCOUNT register accessor: an alias for `Reg<S0_RXCOUNT_SPEC>`"]
+pub type S0_RXCOUNT = crate::Reg<s0_rxcount::S0_RXCOUNT_SPEC>;
+#[doc = "Slave RX Count Register"]
+pub mod s0_rxcount;
+#[doc = "S0_IRQ_ENB register accessor: an alias for `Reg<S0_IRQ_ENB_SPEC>`"]
+pub type S0_IRQ_ENB = crate::Reg<s0_irq_enb::S0_IRQ_ENB_SPEC>;
+#[doc = "Slave Interrupt Enable Register"]
+pub mod s0_irq_enb;
+#[doc = "S0_IRQ_RAW register accessor: an alias for `Reg<S0_IRQ_RAW_SPEC>`"]
+pub type S0_IRQ_RAW = crate::Reg<s0_irq_raw::S0_IRQ_RAW_SPEC>;
+#[doc = "Slave Raw Interrupt Status Register"]
+pub mod s0_irq_raw;
+#[doc = "S0_IRQ_END register accessor: an alias for `Reg<S0_IRQ_END_SPEC>`"]
+pub type S0_IRQ_END = crate::Reg<s0_irq_end::S0_IRQ_END_SPEC>;
+#[doc = "Slave Enabled Interrupt Status Register"]
+pub mod s0_irq_end;
+#[doc = "S0_IRQ_CLR register accessor: an alias for `Reg<S0_IRQ_CLR_SPEC>`"]
+pub type S0_IRQ_CLR = crate::Reg<s0_irq_clr::S0_IRQ_CLR_SPEC>;
+#[doc = "Slave Clear Interrupt Status Register"]
+pub mod s0_irq_clr;
+#[doc = "S0_RXFIFOIRQTRG register accessor: an alias for `Reg<S0_RXFIFOIRQTRG_SPEC>`"]
+pub type S0_RXFIFOIRQTRG = crate::Reg<s0_rxfifoirqtrg::S0_RXFIFOIRQTRG_SPEC>;
+#[doc = "Slave Rx FIFO IRQ Trigger Level"]
+pub mod s0_rxfifoirqtrg;
+#[doc = "S0_TXFIFOIRQTRG register accessor: an alias for `Reg<S0_TXFIFOIRQTRG_SPEC>`"]
+pub type S0_TXFIFOIRQTRG = crate::Reg<s0_txfifoirqtrg::S0_TXFIFOIRQTRG_SPEC>;
+#[doc = "Slave Tx FIFO IRQ Trigger Level"]
+pub mod s0_txfifoirqtrg;
+#[doc = "S0_FIFO_CLR register accessor: an alias for `Reg<S0_FIFO_CLR_SPEC>`"]
+pub type S0_FIFO_CLR = crate::Reg<s0_fifo_clr::S0_FIFO_CLR_SPEC>;
+#[doc = "Slave Clear FIFO Register"]
+pub mod s0_fifo_clr;
+#[doc = "S0_ADDRESSB register accessor: an alias for `Reg<S0_ADDRESSB_SPEC>`"]
+pub type S0_ADDRESSB = crate::Reg<s0_addressb::S0_ADDRESSB_SPEC>;
+#[doc = "Slave I2C Address B Value"]
+pub mod s0_addressb;
+#[doc = "S0_ADDRESSMASKB register accessor: an alias for `Reg<S0_ADDRESSMASKB_SPEC>`"]
+pub type S0_ADDRESSMASKB = crate::Reg<s0_addressmaskb::S0_ADDRESSMASKB_SPEC>;
+#[doc = "Slave I2C Address B Mask value"]
+pub mod s0_addressmaskb;
+#[doc = "PERID register accessor: an alias for `Reg<PERID_SPEC>`"]
+pub type PERID = crate::Reg<perid::PERID_SPEC>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

src/i2ca/address.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `ADDRESS` reader"]
+pub struct R(crate::R<ADDRESS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ADDRESS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ADDRESS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ADDRESS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ADDRESS` writer"]
+pub struct W(crate::W<ADDRESS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ADDRESS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ADDRESS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ADDRESS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I2C Address value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [address](index.html) module"]
+pub struct ADDRESS_SPEC;
+impl crate::RegisterSpec for ADDRESS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [address::R](R) reader structure"]
+impl crate::Readable for ADDRESS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [address::W](W) writer structure"]
+impl crate::Writable for ADDRESS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ADDRESS to value 0"]
+impl crate::Resettable for ADDRESS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/clkscale.rs

@@ -0,0 +1,150 @@
+#[doc = "Register `CLKSCALE` reader"]
+pub struct R(crate::R<CLKSCALE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLKSCALE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLKSCALE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLKSCALE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CLKSCALE` writer"]
+pub struct W(crate::W<CLKSCALE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLKSCALE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLKSCALE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLKSCALE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `VALUE` reader - Enable FastMode"]
+pub struct VALUE_R(crate::FieldReader<u32, u32>);
+impl VALUE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u32) -> Self {
+        VALUE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for VALUE_R {
+    type Target = crate::FieldReader<u32, u32>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `VALUE` writer - Enable FastMode"]
+pub struct VALUE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> VALUE_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `FASTMODE` reader - Enable FastMode"]
+pub struct FASTMODE_R(crate::FieldReader<bool, bool>);
+impl FASTMODE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        FASTMODE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for FASTMODE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FASTMODE` writer - Enable FastMode"]
+pub struct FASTMODE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FASTMODE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:30 - Enable FastMode"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new(self.bits as u32)
+    }
+    #[doc = "Bit 31 - Enable FastMode"]
+    #[inline(always)]
+    pub fn fastmode(&self) -> FASTMODE_R {
+        FASTMODE_R::new(((self.bits >> 31) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:30 - Enable FastMode"]
+    #[inline(always)]
+    pub fn value(&mut self) -> VALUE_W {
+        VALUE_W { w: self }
+    }
+    #[doc = "Bit 31 - Enable FastMode"]
+    #[inline(always)]
+    pub fn fastmode(&mut self) -> FASTMODE_W {
+        FASTMODE_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clock Scale divide value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkscale](index.html) module"]
+pub struct CLKSCALE_SPEC;
+impl crate::RegisterSpec for CLKSCALE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clkscale::R](R) reader structure"]
+impl crate::Readable for CLKSCALE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [clkscale::W](W) writer structure"]
+impl crate::Writable for CLKSCALE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLKSCALE to value 0"]
+impl crate::Resettable for CLKSCALE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/clktolimit.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `CLKTOLIMIT` reader"]
+pub struct R(crate::R<CLKTOLIMIT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLKTOLIMIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLKTOLIMIT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLKTOLIMIT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CLKTOLIMIT` writer"]
+pub struct W(crate::W<CLKTOLIMIT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLKTOLIMIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLKTOLIMIT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLKTOLIMIT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clock Low Timeout Limit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clktolimit](index.html) module"]
+pub struct CLKTOLIMIT_SPEC;
+impl crate::RegisterSpec for CLKTOLIMIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clktolimit::R](R) reader structure"]
+impl crate::Readable for CLKTOLIMIT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [clktolimit::W](W) writer structure"]
+impl crate::Writable for CLKTOLIMIT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
+impl crate::Resettable for CLKTOLIMIT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/cmd.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `CMD` reader"]
+pub struct R(crate::R<CMD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CMD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CMD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CMD` writer"]
+pub struct W(crate::W<CMD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CMD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CMD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CMD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmd](index.html) module"]
+pub struct CMD_SPEC;
+impl crate::RegisterSpec for CMD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cmd::R](R) reader structure"]
+impl crate::Readable for CMD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cmd::W](W) writer structure"]
+impl crate::Writable for CMD_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CMD to value 0"]
+impl crate::Resettable for CMD_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/ctrl.rs

@@ -0,0 +1,489 @@
+#[doc = "Register `CTRL` reader"]
+pub struct R(crate::R<CTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CTRL` writer"]
+pub struct W(crate::W<CTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"]
+pub struct CLKENABLED_R(crate::FieldReader<bool, bool>);
+impl CLKENABLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CLKENABLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CLKENABLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"]
+pub struct CLKENABLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CLKENABLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `ENABLED` reader - I2C Activated"]
+pub struct ENABLED_R(crate::FieldReader<bool, bool>);
+impl ENABLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ENABLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ENABLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ENABLED` writer - I2C Activated"]
+pub struct ENABLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ENABLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `ENABLE` reader - I2C Active"]
+pub struct ENABLE_R(crate::FieldReader<bool, bool>);
+impl ENABLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ENABLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ENABLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ENABLE` writer - I2C Active"]
+pub struct ENABLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ENABLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
+pub struct TXFEMD_R(crate::FieldReader<bool, bool>);
+impl TXFEMD_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXFEMD_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXFEMD_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
+pub struct TXFEMD_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXFEMD_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
+pub struct RXFFMD_R(crate::FieldReader<bool, bool>);
+impl RXFFMD_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFFMD_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFFMD_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
+pub struct RXFFMD_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFFMD_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"]
+pub struct ALGFILTER_R(crate::FieldReader<bool, bool>);
+impl ALGFILTER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ALGFILTER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ALGFILTER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"]
+pub struct ALGFILTER_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ALGFILTER_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"]
+pub struct DLGFILTER_R(crate::FieldReader<bool, bool>);
+impl DLGFILTER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        DLGFILTER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for DLGFILTER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"]
+pub struct DLGFILTER_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> DLGFILTER_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"]
+pub struct LOOPBACK_R(crate::FieldReader<bool, bool>);
+impl LOOPBACK_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        LOOPBACK_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for LOOPBACK_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"]
+pub struct LOOPBACK_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> LOOPBACK_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"]
+pub struct TMCONFIGENB_R(crate::FieldReader<bool, bool>);
+impl TMCONFIGENB_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TMCONFIGENB_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TMCONFIGENB_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"]
+pub struct TMCONFIGENB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TMCONFIGENB_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2C CLK Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&self) -> CLKENABLED_R {
+        CLKENABLED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&self) -> ENABLED_R {
+        ENABLED_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&self) -> TXFEMD_R {
+        TXFEMD_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&self) -> RXFFMD_R {
+        RXFFMD_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
+    #[inline(always)]
+    pub fn algfilter(&self) -> ALGFILTER_R {
+        ALGFILTER_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
+    #[inline(always)]
+    pub fn dlgfilter(&self) -> DLGFILTER_R {
+        DLGFILTER_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Enable LoopBack Mode"]
+    #[inline(always)]
+    pub fn loopback(&self) -> LOOPBACK_R {
+        LOOPBACK_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Enable Timing Config Register"]
+    #[inline(always)]
+    pub fn tmconfigenb(&self) -> TMCONFIGENB_R {
+        TMCONFIGENB_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C CLK Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&mut self) -> CLKENABLED_W {
+        CLKENABLED_W { w: self }
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&mut self) -> ENABLED_W {
+        ENABLED_W { w: self }
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W {
+        ENABLE_W { w: self }
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&mut self) -> TXFEMD_W {
+        TXFEMD_W { w: self }
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&mut self) -> RXFFMD_W {
+        RXFFMD_W { w: self }
+    }
+    #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
+    #[inline(always)]
+    pub fn algfilter(&mut self) -> ALGFILTER_W {
+        ALGFILTER_W { w: self }
+    }
+    #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
+    #[inline(always)]
+    pub fn dlgfilter(&mut self) -> DLGFILTER_W {
+        DLGFILTER_W { w: self }
+    }
+    #[doc = "Bit 8 - Enable LoopBack Mode"]
+    #[inline(always)]
+    pub fn loopback(&mut self) -> LOOPBACK_W {
+        LOOPBACK_W { w: self }
+    }
+    #[doc = "Bit 9 - Enable Timing Config Register"]
+    #[inline(always)]
+    pub fn tmconfigenb(&mut self) -> TMCONFIGENB_W {
+        TMCONFIGENB_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/data.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `DATA` reader"]
+pub struct R(crate::R<DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DATA` writer"]
+pub struct W(crate::W<DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"]
+pub struct DATA_SPEC;
+impl crate::RegisterSpec for DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [data::R](R) reader structure"]
+impl crate::Readable for DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"]
+impl crate::Writable for DATA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATA to value 0"]
+impl crate::Resettable for DATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/fifo_clr.rs

@@ -0,0 +1,99 @@
+#[doc = "Register `FIFO_CLR` writer"]
+pub struct W(crate::W<FIFO_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FIFO_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FIFO_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FIFO_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub struct RXFIFO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFIFO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub struct TXFIFO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXFIFO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    pub fn rxfifo(&mut self) -> RXFIFO_W {
+        RXFIFO_W { w: self }
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    pub fn txfifo(&mut self) -> TXFIFO_W {
+        TXFIFO_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"]
+pub struct FIFO_CLR_SPEC;
+impl crate::RegisterSpec for FIFO_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"]
+impl crate::Writable for FIFO_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FIFO_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/irq_clr.rs

@@ -0,0 +1,423 @@
+#[doc = "Register `IRQ_CLR` writer"]
+pub struct W(crate::W<IRQ_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"]
+pub struct I2CIDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2CIDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub struct IDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub struct WAITING_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WAITING_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `STALLED` writer - Controller is Stalled"]
+pub struct STALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> STALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
+pub struct ARBLOST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ARBLOST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
+pub struct NACKADDR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKADDR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub struct NACKDATA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKDATA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"]
+pub struct CLKLOTO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CLKLOTO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct TXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub struct TXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub struct RXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
+        self.w
+    }
+}
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub struct TXEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
+        self.w
+    }
+}
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub struct RXFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&mut self) -> I2CIDLE_W {
+        I2CIDLE_W { w: self }
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&mut self) -> IDLE_W {
+        IDLE_W { w: self }
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&mut self) -> WAITING_W {
+        WAITING_W { w: self }
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&mut self) -> STALLED_W {
+        STALLED_W { w: self }
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&mut self) -> ARBLOST_W {
+        ARBLOST_W { w: self }
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&mut self) -> NACKADDR_W {
+        NACKADDR_W { w: self }
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&mut self) -> NACKDATA_W {
+        NACKDATA_W { w: self }
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&mut self) -> CLKLOTO_W {
+        CLKLOTO_W { w: self }
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&mut self) -> TXOVERFLOW_W {
+        TXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&mut self) -> RXOVERFLOW_W {
+        RXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&mut self) -> TXREADY_W {
+        TXREADY_W { w: self }
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&mut self) -> RXREADY_W {
+        RXREADY_W { w: self }
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&mut self) -> TXEMPTY_W {
+        TXEMPTY_W { w: self }
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&mut self) -> RXFULL_W {
+        RXFULL_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"]
+pub struct IRQ_CLR_SPEC;
+impl crate::RegisterSpec for IRQ_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"]
+impl crate::Writable for IRQ_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_CLR to value 0"]
+impl crate::Resettable for IRQ_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/irq_enb.rs

@@ -0,0 +1,724 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub struct R(crate::R<IRQ_ENB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_ENB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_ENB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_ENB` writer"]
+pub struct W(crate::W<IRQ_ENB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_ENB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_ENB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"]
+pub struct I2CIDLE_R(crate::FieldReader<bool, bool>);
+impl I2CIDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2CIDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2CIDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"]
+pub struct I2CIDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2CIDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub struct IDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub struct WAITING_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WAITING_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub struct STALLED_R(crate::FieldReader<bool, bool>);
+impl STALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        STALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for STALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `STALLED` writer - Controller is Stalled"]
+pub struct STALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> STALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
+impl ARBLOST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ARBLOST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ARBLOST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
+pub struct ARBLOST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ARBLOST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
+impl NACKADDR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKADDR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKADDR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
+pub struct NACKADDR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKADDR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub struct NACKDATA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKDATA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"]
+pub struct CLKLOTO_R(crate::FieldReader<bool, bool>);
+impl CLKLOTO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CLKLOTO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CLKLOTO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"]
+pub struct CLKLOTO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CLKLOTO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct TXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct TXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub struct TXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub struct RXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
+        self.w
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub struct TXEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
+        self.w
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub struct RXFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&self) -> I2CIDLE_R {
+        I2CIDLE_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> STALLED_R {
+        STALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ARBLOST_R {
+        ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NACKADDR_R {
+        NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&self) -> CLKLOTO_R {
+        CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&self) -> TXOVERFLOW_R {
+        TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&mut self) -> I2CIDLE_W {
+        I2CIDLE_W { w: self }
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&mut self) -> IDLE_W {
+        IDLE_W { w: self }
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&mut self) -> WAITING_W {
+        WAITING_W { w: self }
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&mut self) -> STALLED_W {
+        STALLED_W { w: self }
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&mut self) -> ARBLOST_W {
+        ARBLOST_W { w: self }
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&mut self) -> NACKADDR_W {
+        NACKADDR_W { w: self }
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&mut self) -> NACKDATA_W {
+        NACKDATA_W { w: self }
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&mut self) -> CLKLOTO_W {
+        CLKLOTO_W { w: self }
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&mut self) -> TXOVERFLOW_W {
+        TXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&mut self) -> RXOVERFLOW_W {
+        RXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&mut self) -> TXREADY_W {
+        TXREADY_W { w: self }
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&mut self) -> RXREADY_W {
+        RXREADY_W { w: self }
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&mut self) -> TXEMPTY_W {
+        TXEMPTY_W { w: self }
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&mut self) -> RXFULL_W {
+        RXFULL_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"]
+pub struct IRQ_ENB_SPEC;
+impl crate::RegisterSpec for IRQ_ENB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_enb::R](R) reader structure"]
+impl crate::Readable for IRQ_ENB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"]
+impl crate::Writable for IRQ_ENB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IRQ_ENB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/irq_end.rs

@@ -0,0 +1,313 @@
+#[doc = "Register `IRQ_END` reader"]
+pub struct R(crate::R<IRQ_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"]
+pub struct I2CIDLE_R(crate::FieldReader<bool, bool>);
+impl I2CIDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2CIDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2CIDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub struct STALLED_R(crate::FieldReader<bool, bool>);
+impl STALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        STALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for STALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
+impl ARBLOST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ARBLOST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ARBLOST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
+impl NACKADDR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKADDR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKADDR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"]
+pub struct CLKLOTO_R(crate::FieldReader<bool, bool>);
+impl CLKLOTO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CLKLOTO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CLKLOTO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct TXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&self) -> I2CIDLE_R {
+        I2CIDLE_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> STALLED_R {
+        STALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ARBLOST_R {
+        ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NACKADDR_R {
+        NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&self) -> CLKLOTO_R {
+        CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&self) -> TXOVERFLOW_R {
+        TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+#[doc = "Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"]
+pub struct IRQ_END_SPEC;
+impl crate::RegisterSpec for IRQ_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_end::R](R) reader structure"]
+impl crate::Readable for IRQ_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IRQ_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/irq_raw.rs

@@ -0,0 +1,313 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub struct R(crate::R<IRQ_RAW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_RAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_RAW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_RAW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"]
+pub struct I2CIDLE_R(crate::FieldReader<bool, bool>);
+impl I2CIDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2CIDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2CIDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub struct STALLED_R(crate::FieldReader<bool, bool>);
+impl STALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        STALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for STALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
+impl ARBLOST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ARBLOST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ARBLOST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
+impl NACKADDR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKADDR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKADDR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"]
+pub struct CLKLOTO_R(crate::FieldReader<bool, bool>);
+impl CLKLOTO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CLKLOTO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CLKLOTO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct TXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2C Bus is Idle"]
+    #[inline(always)]
+    pub fn i2cidle(&self) -> I2CIDLE_R {
+        I2CIDLE_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> STALLED_R {
+        STALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ARBLOST_R {
+        ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NACKADDR_R {
+        NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - I2C Clock Low Timeout"]
+    #[inline(always)]
+    pub fn clkloto(&self) -> CLKLOTO_R {
+        CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn txoverflow(&self) -> TXOVERFLOW_R {
+        TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"]
+pub struct IRQ_RAW_SPEC;
+impl crate::RegisterSpec for IRQ_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_raw::R](R) reader structure"]
+impl crate::Readable for IRQ_RAW_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_RAW to value 0"]
+impl crate::Resettable for IRQ_RAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/perid.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `PERID` reader"]
+pub struct R(crate::R<PERID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
+pub struct PERID_SPEC;
+impl crate::RegisterSpec for PERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perid::R](R) reader structure"]
+impl crate::Readable for PERID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PERID to value 0x0014_07e1"]
+impl crate::Resettable for PERID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0014_07e1
+    }
+}

src/i2ca/rxcount.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `RXCOUNT` reader"]
+pub struct R(crate::R<RXCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "RX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxcount](index.html) module"]
+pub struct RXCOUNT_SPEC;
+impl crate::RegisterSpec for RXCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxcount::R](R) reader structure"]
+impl crate::Readable for RXCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RXCOUNT to value 0"]
+impl crate::Resettable for RXCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/rxfifoirqtrg.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub struct R(crate::R<RXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXFIFOIRQTRG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXFIFOIRQTRG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub struct W(crate::W<RXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RXFIFOIRQTRG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RXFIFOIRQTRG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"]
+pub struct RXFIFOIRQTRG_SPEC;
+impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"]
+impl crate::Readable for RXFIFOIRQTRG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"]
+impl crate::Writable for RXFIFOIRQTRG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for RXFIFOIRQTRG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_address.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_ADDRESS` reader"]
+pub struct R(crate::R<S0_ADDRESS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_ADDRESS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_ADDRESS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_ADDRESS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_ADDRESS` writer"]
+pub struct W(crate::W<S0_ADDRESS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_ADDRESS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_ADDRESS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_ADDRESS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave I2C Address Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_address](index.html) module"]
+pub struct S0_ADDRESS_SPEC;
+impl crate::RegisterSpec for S0_ADDRESS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_address::R](R) reader structure"]
+impl crate::Readable for S0_ADDRESS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_address::W](W) writer structure"]
+impl crate::Writable for S0_ADDRESS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_ADDRESS to value 0"]
+impl crate::Resettable for S0_ADDRESS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_addressb.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_ADDRESSB` reader"]
+pub struct R(crate::R<S0_ADDRESSB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_ADDRESSB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_ADDRESSB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_ADDRESSB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_ADDRESSB` writer"]
+pub struct W(crate::W<S0_ADDRESSB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_ADDRESSB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_ADDRESSB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_ADDRESSB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave I2C Address B Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressb](index.html) module"]
+pub struct S0_ADDRESSB_SPEC;
+impl crate::RegisterSpec for S0_ADDRESSB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_addressb::R](R) reader structure"]
+impl crate::Readable for S0_ADDRESSB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_addressb::W](W) writer structure"]
+impl crate::Writable for S0_ADDRESSB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
+impl crate::Resettable for S0_ADDRESSB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_addressmask.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_ADDRESSMASK` reader"]
+pub struct R(crate::R<S0_ADDRESSMASK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_ADDRESSMASK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_ADDRESSMASK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_ADDRESSMASK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_ADDRESSMASK` writer"]
+pub struct W(crate::W<S0_ADDRESSMASK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_ADDRESSMASK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_ADDRESSMASK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_ADDRESSMASK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave I2C Address Mask value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressmask](index.html) module"]
+pub struct S0_ADDRESSMASK_SPEC;
+impl crate::RegisterSpec for S0_ADDRESSMASK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_addressmask::R](R) reader structure"]
+impl crate::Readable for S0_ADDRESSMASK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_addressmask::W](W) writer structure"]
+impl crate::Writable for S0_ADDRESSMASK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
+impl crate::Resettable for S0_ADDRESSMASK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_addressmaskb.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_ADDRESSMASKB` reader"]
+pub struct R(crate::R<S0_ADDRESSMASKB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_ADDRESSMASKB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_ADDRESSMASKB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_ADDRESSMASKB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_ADDRESSMASKB` writer"]
+pub struct W(crate::W<S0_ADDRESSMASKB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_ADDRESSMASKB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_ADDRESSMASKB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_ADDRESSMASKB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave I2C Address B Mask value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressmaskb](index.html) module"]
+pub struct S0_ADDRESSMASKB_SPEC;
+impl crate::RegisterSpec for S0_ADDRESSMASKB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_addressmaskb::R](R) reader structure"]
+impl crate::Readable for S0_ADDRESSMASKB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_addressmaskb::W](W) writer structure"]
+impl crate::Writable for S0_ADDRESSMASKB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
+impl crate::Resettable for S0_ADDRESSMASKB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_ctrl.rs

@@ -0,0 +1,301 @@
+#[doc = "Register `S0_CTRL` reader"]
+pub struct R(crate::R<S0_CTRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_CTRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_CTRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_CTRL` writer"]
+pub struct W(crate::W<S0_CTRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_CTRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_CTRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_CTRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CLKENABLED` reader - I2C Enabled"]
+pub struct CLKENABLED_R(crate::FieldReader<bool, bool>);
+impl CLKENABLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CLKENABLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CLKENABLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CLKENABLED` writer - I2C Enabled"]
+pub struct CLKENABLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CLKENABLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `ENABLED` reader - I2C Activated"]
+pub struct ENABLED_R(crate::FieldReader<bool, bool>);
+impl ENABLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ENABLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ENABLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ENABLED` writer - I2C Activated"]
+pub struct ENABLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ENABLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `ENABLE` reader - I2C Active"]
+pub struct ENABLE_R(crate::FieldReader<bool, bool>);
+impl ENABLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ENABLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ENABLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ENABLE` writer - I2C Active"]
+pub struct ENABLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ENABLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
+pub struct TXFEMD_R(crate::FieldReader<bool, bool>);
+impl TXFEMD_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXFEMD_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXFEMD_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
+pub struct TXFEMD_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXFEMD_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
+pub struct RXFFMD_R(crate::FieldReader<bool, bool>);
+impl RXFFMD_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFFMD_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFFMD_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
+pub struct RXFFMD_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFFMD_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2C Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&self) -> CLKENABLED_R {
+        CLKENABLED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&self) -> ENABLED_R {
+        ENABLED_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&self) -> TXFEMD_R {
+        TXFEMD_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&self) -> RXFFMD_R {
+        RXFFMD_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2C Enabled"]
+    #[inline(always)]
+    pub fn clkenabled(&mut self) -> CLKENABLED_W {
+        CLKENABLED_W { w: self }
+    }
+    #[doc = "Bit 1 - I2C Activated"]
+    #[inline(always)]
+    pub fn enabled(&mut self) -> ENABLED_W {
+        ENABLED_W { w: self }
+    }
+    #[doc = "Bit 2 - I2C Active"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W {
+        ENABLE_W { w: self }
+    }
+    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
+    #[inline(always)]
+    pub fn txfemd(&mut self) -> TXFEMD_W {
+        TXFEMD_W { w: self }
+    }
+    #[doc = "Bit 4 - RX FIFO Full Mode"]
+    #[inline(always)]
+    pub fn rxffmd(&mut self) -> RXFFMD_W {
+        RXFFMD_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_ctrl](index.html) module"]
+pub struct S0_CTRL_SPEC;
+impl crate::RegisterSpec for S0_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_ctrl::R](R) reader structure"]
+impl crate::Readable for S0_CTRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_ctrl::W](W) writer structure"]
+impl crate::Writable for S0_CTRL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_CTRL to value 0"]
+impl crate::Resettable for S0_CTRL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_data.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_DATA` reader"]
+pub struct R(crate::R<S0_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_DATA` writer"]
+pub struct W(crate::W<S0_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_data](index.html) module"]
+pub struct S0_DATA_SPEC;
+impl crate::RegisterSpec for S0_DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_data::R](R) reader structure"]
+impl crate::Readable for S0_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_data::W](W) writer structure"]
+impl crate::Writable for S0_DATA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_DATA to value 0"]
+impl crate::Resettable for S0_DATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_fifo_clr.rs

@@ -0,0 +1,99 @@
+#[doc = "Register `S0_FIFO_CLR` writer"]
+pub struct W(crate::W<S0_FIFO_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_FIFO_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_FIFO_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_FIFO_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub struct RXFIFO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFIFO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub struct TXFIFO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXFIFO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    pub fn rxfifo(&mut self) -> RXFIFO_W {
+        RXFIFO_W { w: self }
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    pub fn txfifo(&mut self) -> TXFIFO_W {
+        TXFIFO_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_fifo_clr](index.html) module"]
+pub struct S0_FIFO_CLR_SPEC;
+impl crate::RegisterSpec for S0_FIFO_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [s0_fifo_clr::W](W) writer structure"]
+impl crate::Writable for S0_FIFO_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
+impl crate::Resettable for S0_FIFO_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_irq_clr.rs

@@ -0,0 +1,477 @@
+#[doc = "Register `S0_IRQ_CLR` writer"]
+pub struct W(crate::W<S0_IRQ_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_IRQ_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_IRQ_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_IRQ_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"]
+pub struct COMPLETED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COMPLETED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub struct IDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub struct WAITING_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WAITING_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"]
+pub struct TXSTALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXSTALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"]
+pub struct RXSTALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXSTALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"]
+pub struct ADDRESSMATCH_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRESSMATCH_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub struct NACKDATA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKDATA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXDATAFIRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `I2C_START` writer - I2C Start Condition"]
+pub struct I2C_START_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_START_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"]
+pub struct I2C_STOP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_STOP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"]
+pub struct TXUNDERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXUNDERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub struct TXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub struct RXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
+        self.w
+    }
+}
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub struct TXEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
+        self.w
+    }
+}
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub struct RXFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&mut self) -> COMPLETED_W {
+        COMPLETED_W { w: self }
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&mut self) -> IDLE_W {
+        IDLE_W { w: self }
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&mut self) -> WAITING_W {
+        WAITING_W { w: self }
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&mut self) -> TXSTALLED_W {
+        TXSTALLED_W { w: self }
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&mut self) -> RXSTALLED_W {
+        RXSTALLED_W { w: self }
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&mut self) -> ADDRESSMATCH_W {
+        ADDRESSMATCH_W { w: self }
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&mut self) -> NACKDATA_W {
+        NACKDATA_W { w: self }
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&mut self) -> RXDATAFIRST_W {
+        RXDATAFIRST_W { w: self }
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&mut self) -> I2C_START_W {
+        I2C_START_W { w: self }
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&mut self) -> I2C_STOP_W {
+        I2C_STOP_W { w: self }
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&mut self) -> TXUNDERFLOW_W {
+        TXUNDERFLOW_W { w: self }
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&mut self) -> RXOVERFLOW_W {
+        RXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&mut self) -> TXREADY_W {
+        TXREADY_W { w: self }
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&mut self) -> RXREADY_W {
+        RXREADY_W { w: self }
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&mut self) -> TXEMPTY_W {
+        TXEMPTY_W { w: self }
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&mut self) -> RXFULL_W {
+        RXFULL_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_clr](index.html) module"]
+pub struct S0_IRQ_CLR_SPEC;
+impl crate::RegisterSpec for S0_IRQ_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [s0_irq_clr::W](W) writer structure"]
+impl crate::Writable for S0_IRQ_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_IRQ_CLR to value 0"]
+impl crate::Resettable for S0_IRQ_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_irq_enb.rs

@@ -0,0 +1,818 @@
+#[doc = "Register `S0_IRQ_ENB` reader"]
+pub struct R(crate::R<S0_IRQ_ENB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_IRQ_ENB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_IRQ_ENB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_IRQ_ENB` writer"]
+pub struct W(crate::W<S0_IRQ_ENB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_IRQ_ENB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_IRQ_ENB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub struct COMPLETED_R(crate::FieldReader<bool, bool>);
+impl COMPLETED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        COMPLETED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COMPLETED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"]
+pub struct COMPLETED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> COMPLETED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` writer - Controller is Idle"]
+pub struct IDLE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IDLE_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub struct WAITING_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WAITING_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub struct TXSTALLED_R(crate::FieldReader<bool, bool>);
+impl TXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"]
+pub struct TXSTALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXSTALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub struct RXSTALLED_R(crate::FieldReader<bool, bool>);
+impl RXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"]
+pub struct RXSTALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXSTALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub struct ADDRESSMATCH_R(crate::FieldReader<bool, bool>);
+impl ADDRESSMATCH_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ADDRESSMATCH_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRESSMATCH_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"]
+pub struct ADDRESSMATCH_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ADDRESSMATCH_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub struct NACKDATA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKDATA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_R(crate::FieldReader<bool, bool>);
+impl RXDATAFIRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXDATAFIRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXDATAFIRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXDATAFIRST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `I2C_START` reader - I2C Start Condition"]
+pub struct I2C_START_R(crate::FieldReader<bool, bool>);
+impl I2C_START_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_START_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_START_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_START` writer - I2C Start Condition"]
+pub struct I2C_START_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_START_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
+pub struct I2C_STOP_R(crate::FieldReader<bool, bool>);
+impl I2C_STOP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_STOP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_STOP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"]
+pub struct I2C_STOP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_STOP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
+pub struct TXUNDERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXUNDERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXUNDERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXUNDERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"]
+pub struct TXUNDERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXUNDERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXOVERFLOW_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
+pub struct TXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
+pub struct RXREADY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXREADY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
+        self.w
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
+pub struct TXEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
+        self.w
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` writer - RX FIFO Full"]
+pub struct RXFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> COMPLETED_R {
+        COMPLETED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TXSTALLED_R {
+        TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RXSTALLED_R {
+        RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> ADDRESSMATCH_R {
+        ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RXDATAFIRST_R {
+        RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&self) -> I2C_START_R {
+        I2C_START_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&self) -> I2C_STOP_R {
+        I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&self) -> TXUNDERFLOW_R {
+        TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&mut self) -> COMPLETED_W {
+        COMPLETED_W { w: self }
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&mut self) -> IDLE_W {
+        IDLE_W { w: self }
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&mut self) -> WAITING_W {
+        WAITING_W { w: self }
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&mut self) -> TXSTALLED_W {
+        TXSTALLED_W { w: self }
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&mut self) -> RXSTALLED_W {
+        RXSTALLED_W { w: self }
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&mut self) -> ADDRESSMATCH_W {
+        ADDRESSMATCH_W { w: self }
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&mut self) -> NACKDATA_W {
+        NACKDATA_W { w: self }
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&mut self) -> RXDATAFIRST_W {
+        RXDATAFIRST_W { w: self }
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&mut self) -> I2C_START_W {
+        I2C_START_W { w: self }
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&mut self) -> I2C_STOP_W {
+        I2C_STOP_W { w: self }
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&mut self) -> TXUNDERFLOW_W {
+        TXUNDERFLOW_W { w: self }
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&mut self) -> RXOVERFLOW_W {
+        RXOVERFLOW_W { w: self }
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&mut self) -> TXREADY_W {
+        TXREADY_W { w: self }
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&mut self) -> RXREADY_W {
+        RXREADY_W { w: self }
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&mut self) -> TXEMPTY_W {
+        TXEMPTY_W { w: self }
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&mut self) -> RXFULL_W {
+        RXFULL_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_enb](index.html) module"]
+pub struct S0_IRQ_ENB_SPEC;
+impl crate::RegisterSpec for S0_IRQ_ENB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_irq_enb::R](R) reader structure"]
+impl crate::Readable for S0_IRQ_ENB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_irq_enb::W](W) writer structure"]
+impl crate::Writable for S0_IRQ_ENB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
+impl crate::Resettable for S0_IRQ_ENB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_irq_end.rs

@@ -0,0 +1,353 @@
+#[doc = "Register `S0_IRQ_END` reader"]
+pub struct R(crate::R<S0_IRQ_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_IRQ_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_IRQ_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_IRQ_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub struct COMPLETED_R(crate::FieldReader<bool, bool>);
+impl COMPLETED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        COMPLETED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COMPLETED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub struct TXSTALLED_R(crate::FieldReader<bool, bool>);
+impl TXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub struct RXSTALLED_R(crate::FieldReader<bool, bool>);
+impl RXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub struct ADDRESSMATCH_R(crate::FieldReader<bool, bool>);
+impl ADDRESSMATCH_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ADDRESSMATCH_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRESSMATCH_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_R(crate::FieldReader<bool, bool>);
+impl RXDATAFIRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXDATAFIRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXDATAFIRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_START` reader - I2C Start Condition"]
+pub struct I2C_START_R(crate::FieldReader<bool, bool>);
+impl I2C_START_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_START_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_START_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
+pub struct I2C_STOP_R(crate::FieldReader<bool, bool>);
+impl I2C_STOP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_STOP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_STOP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
+pub struct TXUNDERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXUNDERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXUNDERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXUNDERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> COMPLETED_R {
+        COMPLETED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TXSTALLED_R {
+        TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RXSTALLED_R {
+        RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> ADDRESSMATCH_R {
+        ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RXDATAFIRST_R {
+        RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&self) -> I2C_START_R {
+        I2C_START_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&self) -> I2C_STOP_R {
+        I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&self) -> TXUNDERFLOW_R {
+        TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+#[doc = "Slave Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_end](index.html) module"]
+pub struct S0_IRQ_END_SPEC;
+impl crate::RegisterSpec for S0_IRQ_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_irq_end::R](R) reader structure"]
+impl crate::Readable for S0_IRQ_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_IRQ_END to value 0"]
+impl crate::Resettable for S0_IRQ_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_irq_raw.rs

@@ -0,0 +1,353 @@
+#[doc = "Register `S0_IRQ_RAW` reader"]
+pub struct R(crate::R<S0_IRQ_RAW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_IRQ_RAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_IRQ_RAW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_IRQ_RAW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub struct COMPLETED_R(crate::FieldReader<bool, bool>);
+impl COMPLETED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        COMPLETED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COMPLETED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub struct TXSTALLED_R(crate::FieldReader<bool, bool>);
+impl TXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub struct RXSTALLED_R(crate::FieldReader<bool, bool>);
+impl RXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub struct ADDRESSMATCH_R(crate::FieldReader<bool, bool>);
+impl ADDRESSMATCH_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ADDRESSMATCH_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRESSMATCH_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_R(crate::FieldReader<bool, bool>);
+impl RXDATAFIRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXDATAFIRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXDATAFIRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_START` reader - I2C Start Condition"]
+pub struct I2C_START_R(crate::FieldReader<bool, bool>);
+impl I2C_START_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_START_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_START_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
+pub struct I2C_STOP_R(crate::FieldReader<bool, bool>);
+impl I2C_STOP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_STOP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_STOP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
+pub struct TXUNDERFLOW_R(crate::FieldReader<bool, bool>);
+impl TXUNDERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXUNDERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXUNDERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
+pub struct RXOVERFLOW_R(crate::FieldReader<bool, bool>);
+impl RXOVERFLOW_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXOVERFLOW_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXOVERFLOW_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
+pub struct TXREADY_R(crate::FieldReader<bool, bool>);
+impl TXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
+pub struct RXREADY_R(crate::FieldReader<bool, bool>);
+impl RXREADY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXREADY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXREADY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> COMPLETED_R {
+        COMPLETED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TXSTALLED_R {
+        TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RXSTALLED_R {
+        RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> ADDRESSMATCH_R {
+        ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RXDATAFIRST_R {
+        RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - I2C Start Condition"]
+    #[inline(always)]
+    pub fn i2c_start(&self) -> I2C_START_R {
+        I2C_START_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - I2C Stop Condition"]
+    #[inline(always)]
+    pub fn i2c_stop(&self) -> I2C_STOP_R {
+        I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - TX FIFO Underflowed"]
+    #[inline(always)]
+    pub fn txunderflow(&self) -> TXUNDERFLOW_R {
+        TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - TX FIFO Overflowed"]
+    #[inline(always)]
+    pub fn rxoverflow(&self) -> RXOVERFLOW_R {
+        RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO Ready"]
+    #[inline(always)]
+    pub fn txready(&self) -> TXREADY_R {
+        TXREADY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - RX FIFO Ready"]
+    #[inline(always)]
+    pub fn rxready(&self) -> RXREADY_R {
+        RXREADY_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 14 - TX FIFO Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - RX FIFO Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+}
+#[doc = "Slave Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_raw](index.html) module"]
+pub struct S0_IRQ_RAW_SPEC;
+impl crate::RegisterSpec for S0_IRQ_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_irq_raw::R](R) reader structure"]
+impl crate::Readable for S0_IRQ_RAW_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_IRQ_RAW to value 0"]
+impl crate::Resettable for S0_IRQ_RAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_lastaddress.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `S0_LASTADDRESS` reader"]
+pub struct R(crate::R<S0_LASTADDRESS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_LASTADDRESS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_LASTADDRESS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_LASTADDRESS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Slave I2C Last Address value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_lastaddress](index.html) module"]
+pub struct S0_LASTADDRESS_SPEC;
+impl crate::RegisterSpec for S0_LASTADDRESS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_lastaddress::R](R) reader structure"]
+impl crate::Readable for S0_LASTADDRESS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
+impl crate::Resettable for S0_LASTADDRESS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_maxwords.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_MAXWORDS` reader"]
+pub struct R(crate::R<S0_MAXWORDS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_MAXWORDS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_MAXWORDS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_MAXWORDS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_MAXWORDS` writer"]
+pub struct W(crate::W<S0_MAXWORDS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_MAXWORDS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_MAXWORDS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_MAXWORDS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave MaxWords Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_maxwords](index.html) module"]
+pub struct S0_MAXWORDS_SPEC;
+impl crate::RegisterSpec for S0_MAXWORDS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_maxwords::R](R) reader structure"]
+impl crate::Readable for S0_MAXWORDS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_maxwords::W](W) writer structure"]
+impl crate::Writable for S0_MAXWORDS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
+impl crate::Resettable for S0_MAXWORDS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_rxcount.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `S0_RXCOUNT` reader"]
+pub struct R(crate::R<S0_RXCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_RXCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_RXCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_RXCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Slave RX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_rxcount](index.html) module"]
+pub struct S0_RXCOUNT_SPEC;
+impl crate::RegisterSpec for S0_RXCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_rxcount::R](R) reader structure"]
+impl crate::Readable for S0_RXCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
+impl crate::Resettable for S0_RXCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_rxfifoirqtrg.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_RXFIFOIRQTRG` reader"]
+pub struct R(crate::R<S0_RXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_RXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_RXFIFOIRQTRG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_RXFIFOIRQTRG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_RXFIFOIRQTRG` writer"]
+pub struct W(crate::W<S0_RXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_RXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_RXFIFOIRQTRG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_RXFIFOIRQTRG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_rxfifoirqtrg](index.html) module"]
+pub struct S0_RXFIFOIRQTRG_SPEC;
+impl crate::RegisterSpec for S0_RXFIFOIRQTRG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_rxfifoirqtrg::R](R) reader structure"]
+impl crate::Readable for S0_RXFIFOIRQTRG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_rxfifoirqtrg::W](W) writer structure"]
+impl crate::Writable for S0_RXFIFOIRQTRG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for S0_RXFIFOIRQTRG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_state.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `S0_STATE` reader"]
+pub struct R(crate::R<S0_STATE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_STATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_STATE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_STATE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Internal STATE of I2C Slave Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_state](index.html) module"]
+pub struct S0_STATE_SPEC;
+impl crate::RegisterSpec for S0_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_state::R](R) reader structure"]
+impl crate::Readable for S0_STATE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_STATE to value 0"]
+impl crate::Resettable for S0_STATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_status.rs

@@ -0,0 +1,373 @@
+#[doc = "Register `S0_STATUS` reader"]
+pub struct R(crate::R<S0_STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
+pub struct COMPLETED_R(crate::FieldReader<bool, bool>);
+impl COMPLETED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        COMPLETED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for COMPLETED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
+pub struct TXSTALLED_R(crate::FieldReader<bool, bool>);
+impl TXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
+pub struct RXSTALLED_R(crate::FieldReader<bool, bool>);
+impl RXSTALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXSTALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXSTALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
+pub struct ADDRESSMATCH_R(crate::FieldReader<bool, bool>);
+impl ADDRESSMATCH_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ADDRESSMATCH_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ADDRESSMATCH_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
+pub struct RXDATAFIRST_R(crate::FieldReader<bool, bool>);
+impl RXDATAFIRST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXDATAFIRST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXDATAFIRST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
+pub struct RXNEMPTY_R(crate::FieldReader<bool, bool>);
+impl RXNEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXNEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXNEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
+pub struct RXTRIGGER_R(crate::FieldReader<bool, bool>);
+impl RXTRIGGER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXTRIGGER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXTRIGGER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
+pub struct TXNFULL_R(crate::FieldReader<bool, bool>);
+impl TXNFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXNFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXNFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
+pub struct TXTRIGGER_R(crate::FieldReader<bool, bool>);
+impl TXTRIGGER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXTRIGGER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXTRIGGER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"]
+pub struct RAW_BUSY_R(crate::FieldReader<bool, bool>);
+impl RAW_BUSY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAW_BUSY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAW_BUSY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
+pub struct RAW_SDA_R(crate::FieldReader<bool, bool>);
+impl RAW_SDA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAW_SDA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAW_SDA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
+pub struct RAW_SCL_R(crate::FieldReader<bool, bool>);
+impl RAW_SCL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAW_SCL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAW_SCL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Controller Complted a Transaction"]
+    #[inline(always)]
+    pub fn completed(&self) -> COMPLETED_R {
+        COMPLETED_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Controller is Idle"]
+    #[inline(always)]
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Tx Stalled"]
+    #[inline(always)]
+    pub fn txstalled(&self) -> TXSTALLED_R {
+        TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Controller is Rx Stalled"]
+    #[inline(always)]
+    pub fn rxstalled(&self) -> RXSTALLED_R {
+        RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address Match"]
+    #[inline(always)]
+    pub fn addressmatch(&self) -> ADDRESSMATCH_R {
+        ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
+    #[inline(always)]
+    pub fn rxdatafirst(&self) -> RXDATAFIRST_R {
+        RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - RX FIFO is Not Empty"]
+    #[inline(always)]
+    pub fn rxnempty(&self) -> RXNEMPTY_R {
+        RXNEMPTY_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - RX FIFO is Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&self) -> RXTRIGGER_R {
+        RXTRIGGER_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO is Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - TX FIFO is Full"]
+    #[inline(always)]
+    pub fn txnfull(&self) -> TXNFULL_R {
+        TXNFULL_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&self) -> TXTRIGGER_R {
+        TXTRIGGER_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 29 - I2C Raw Busy value"]
+    #[inline(always)]
+    pub fn raw_busy(&self) -> RAW_BUSY_R {
+        RAW_BUSY_R::new(((self.bits >> 29) & 0x01) != 0)
+    }
+    #[doc = "Bit 30 - I2C Raw SDA value"]
+    #[inline(always)]
+    pub fn raw_sda(&self) -> RAW_SDA_R {
+        RAW_SDA_R::new(((self.bits >> 30) & 0x01) != 0)
+    }
+    #[doc = "Bit 31 - I2C Raw SCL value"]
+    #[inline(always)]
+    pub fn raw_scl(&self) -> RAW_SCL_R {
+        RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0)
+    }
+}
+#[doc = "Slave I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_status](index.html) module"]
+pub struct S0_STATUS_SPEC;
+impl crate::RegisterSpec for S0_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_status::R](R) reader structure"]
+impl crate::Readable for S0_STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_STATUS to value 0"]
+impl crate::Resettable for S0_STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_txcount.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `S0_TXCOUNT` reader"]
+pub struct R(crate::R<S0_TXCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_TXCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_TXCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_TXCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Slave TX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_txcount](index.html) module"]
+pub struct S0_TXCOUNT_SPEC;
+impl crate::RegisterSpec for S0_TXCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_txcount::R](R) reader structure"]
+impl crate::Readable for S0_TXCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
+impl crate::Resettable for S0_TXCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/s0_txfifoirqtrg.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `S0_TXFIFOIRQTRG` reader"]
+pub struct R(crate::R<S0_TXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<S0_TXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<S0_TXFIFOIRQTRG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<S0_TXFIFOIRQTRG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `S0_TXFIFOIRQTRG` writer"]
+pub struct W(crate::W<S0_TXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<S0_TXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<S0_TXFIFOIRQTRG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<S0_TXFIFOIRQTRG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_txfifoirqtrg](index.html) module"]
+pub struct S0_TXFIFOIRQTRG_SPEC;
+impl crate::RegisterSpec for S0_TXFIFOIRQTRG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [s0_txfifoirqtrg::R](R) reader structure"]
+impl crate::Readable for S0_TXFIFOIRQTRG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [s0_txfifoirqtrg::W](W) writer structure"]
+impl crate::Writable for S0_TXFIFOIRQTRG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for S0_TXFIFOIRQTRG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/state.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `STATE` reader"]
+pub struct R(crate::R<STATE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STATE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STATE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Internal STATE of I2C Master Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [state](index.html) module"]
+pub struct STATE_SPEC;
+impl crate::RegisterSpec for STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [state::R](R) reader structure"]
+impl crate::Readable for STATE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for STATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/status.rs

@@ -0,0 +1,677 @@
+#[doc = "Register `STATUS` reader"]
+pub struct R(crate::R<STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `STATUS` writer"]
+pub struct W(crate::W<STATUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<STATUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<STATUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `WAITING` reader - Controller is Waiting"]
+pub struct WAITING_R(crate::FieldReader<bool, bool>);
+impl WAITING_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        WAITING_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for WAITING_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `WAITING` writer - Controller is Waiting"]
+pub struct WAITING_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> WAITING_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+        self.w
+    }
+}
+#[doc = "Field `STALLED` reader - Controller is Stalled"]
+pub struct STALLED_R(crate::FieldReader<bool, bool>);
+impl STALLED_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        STALLED_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for STALLED_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `STALLED` writer - Controller is Stalled"]
+pub struct STALLED_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> STALLED_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+        self.w
+    }
+}
+#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
+pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
+impl ARBLOST_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ARBLOST_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ARBLOST_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
+pub struct ARBLOST_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> ARBLOST_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
+pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
+impl NACKADDR_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKADDR_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKADDR_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
+pub struct NACKADDR_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKADDR_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
+pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
+impl NACKDATA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        NACKDATA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for NACKDATA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
+pub struct NACKDATA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> NACKDATA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
+pub struct RXNEMPTY_R(crate::FieldReader<bool, bool>);
+impl RXNEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXNEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXNEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"]
+pub struct RXNEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXNEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
+pub struct RXFULL_R(crate::FieldReader<bool, bool>);
+impl RXFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXFULL` writer - RX FIFO is Full"]
+pub struct RXFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
+pub struct RXTRIGGER_R(crate::FieldReader<bool, bool>);
+impl RXTRIGGER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RXTRIGGER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RXTRIGGER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"]
+pub struct RXTRIGGER_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RXTRIGGER_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
+pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
+impl TXEMPTY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXEMPTY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXEMPTY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"]
+pub struct TXEMPTY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXEMPTY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
+pub struct TXNFULL_R(crate::FieldReader<bool, bool>);
+impl TXNFULL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXNFULL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXNFULL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXNFULL` writer - TX FIFO is Full"]
+pub struct TXNFULL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXNFULL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
+        self.w
+    }
+}
+#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
+pub struct TXTRIGGER_R(crate::FieldReader<bool, bool>);
+impl TXTRIGGER_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        TXTRIGGER_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for TXTRIGGER_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"]
+pub struct TXTRIGGER_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> TXTRIGGER_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+        self.w
+    }
+}
+#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
+pub struct RAW_SDA_R(crate::FieldReader<bool, bool>);
+impl RAW_SDA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAW_SDA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAW_SDA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"]
+pub struct RAW_SDA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAW_SDA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
+        self.w
+    }
+}
+#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
+pub struct RAW_SCL_R(crate::FieldReader<bool, bool>);
+impl RAW_SCL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        RAW_SCL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for RAW_SCL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"]
+pub struct RAW_SCL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> RAW_SCL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&self) -> WAITING_R {
+        WAITING_R::new(((self.bits >> 2) & 0x01) != 0)
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&self) -> STALLED_R {
+        STALLED_R::new(((self.bits >> 3) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&self) -> ARBLOST_R {
+        ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&self) -> NACKADDR_R {
+        NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&self) -> NACKDATA_R {
+        NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - RX FIFO is Not Empty"]
+    #[inline(always)]
+    pub fn rxnempty(&self) -> RXNEMPTY_R {
+        RXNEMPTY_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - RX FIFO is Full"]
+    #[inline(always)]
+    pub fn rxfull(&self) -> RXFULL_R {
+        RXFULL_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&self) -> RXTRIGGER_R {
+        RXTRIGGER_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - TX FIFO is Empty"]
+    #[inline(always)]
+    pub fn txempty(&self) -> TXEMPTY_R {
+        TXEMPTY_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bit 13 - TX FIFO is Full"]
+    #[inline(always)]
+    pub fn txnfull(&self) -> TXNFULL_R {
+        TXNFULL_R::new(((self.bits >> 13) & 0x01) != 0)
+    }
+    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&self) -> TXTRIGGER_R {
+        TXTRIGGER_R::new(((self.bits >> 15) & 0x01) != 0)
+    }
+    #[doc = "Bit 30 - I2C Raw SDA value"]
+    #[inline(always)]
+    pub fn raw_sda(&self) -> RAW_SDA_R {
+        RAW_SDA_R::new(((self.bits >> 30) & 0x01) != 0)
+    }
+    #[doc = "Bit 31 - I2C Raw SCL value"]
+    #[inline(always)]
+    pub fn raw_scl(&self) -> RAW_SCL_R {
+        RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 2 - Controller is Waiting"]
+    #[inline(always)]
+    pub fn waiting(&mut self) -> WAITING_W {
+        WAITING_W { w: self }
+    }
+    #[doc = "Bit 3 - Controller is Stalled"]
+    #[inline(always)]
+    pub fn stalled(&mut self) -> STALLED_W {
+        STALLED_W { w: self }
+    }
+    #[doc = "Bit 4 - I2C Arbitration was lost"]
+    #[inline(always)]
+    pub fn arblost(&mut self) -> ARBLOST_W {
+        ARBLOST_W { w: self }
+    }
+    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackaddr(&mut self) -> NACKADDR_W {
+        NACKADDR_W { w: self }
+    }
+    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
+    #[inline(always)]
+    pub fn nackdata(&mut self) -> NACKDATA_W {
+        NACKDATA_W { w: self }
+    }
+    #[doc = "Bit 8 - RX FIFO is Not Empty"]
+    #[inline(always)]
+    pub fn rxnempty(&mut self) -> RXNEMPTY_W {
+        RXNEMPTY_W { w: self }
+    }
+    #[doc = "Bit 9 - RX FIFO is Full"]
+    #[inline(always)]
+    pub fn rxfull(&mut self) -> RXFULL_W {
+        RXFULL_W { w: self }
+    }
+    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
+    #[inline(always)]
+    pub fn rxtrigger(&mut self) -> RXTRIGGER_W {
+        RXTRIGGER_W { w: self }
+    }
+    #[doc = "Bit 12 - TX FIFO is Empty"]
+    #[inline(always)]
+    pub fn txempty(&mut self) -> TXEMPTY_W {
+        TXEMPTY_W { w: self }
+    }
+    #[doc = "Bit 13 - TX FIFO is Full"]
+    #[inline(always)]
+    pub fn txnfull(&mut self) -> TXNFULL_W {
+        TXNFULL_W { w: self }
+    }
+    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
+    #[inline(always)]
+    pub fn txtrigger(&mut self) -> TXTRIGGER_W {
+        TXTRIGGER_W { w: self }
+    }
+    #[doc = "Bit 30 - I2C Raw SDA value"]
+    #[inline(always)]
+    pub fn raw_sda(&mut self) -> RAW_SDA_W {
+        RAW_SDA_W { w: self }
+    }
+    #[doc = "Bit 31 - I2C Raw SCL value"]
+    #[inline(always)]
+    pub fn raw_scl(&mut self) -> RAW_SCL_W {
+        RAW_SCL_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [status::R](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"]
+impl crate::Writable for STATUS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/tmconfig.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `TMCONFIG` reader"]
+pub struct R(crate::R<TMCONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TMCONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TMCONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TMCONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TMCONFIG` writer"]
+pub struct W(crate::W<TMCONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TMCONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TMCONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TMCONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Timing Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tmconfig](index.html) module"]
+pub struct TMCONFIG_SPEC;
+impl crate::RegisterSpec for TMCONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [tmconfig::R](R) reader structure"]
+impl crate::Readable for TMCONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [tmconfig::W](W) writer structure"]
+impl crate::Writable for TMCONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TMCONFIG to value 0"]
+impl crate::Resettable for TMCONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/txcount.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `TXCOUNT` reader"]
+pub struct R(crate::R<TXCOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXCOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXCOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXCOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "TX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txcount](index.html) module"]
+pub struct TXCOUNT_SPEC;
+impl crate::RegisterSpec for TXCOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txcount::R](R) reader structure"]
+impl crate::Readable for TXCOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets TXCOUNT to value 0"]
+impl crate::Resettable for TXCOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/txfifoirqtrg.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `TXFIFOIRQTRG` reader"]
+pub struct R(crate::R<TXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXFIFOIRQTRG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXFIFOIRQTRG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TXFIFOIRQTRG` writer"]
+pub struct W(crate::W<TXFIFOIRQTRG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TXFIFOIRQTRG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TXFIFOIRQTRG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TXFIFOIRQTRG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"]
+pub struct TXFIFOIRQTRG_SPEC;
+impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"]
+impl crate::Readable for TXFIFOIRQTRG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"]
+impl crate::Writable for TXFIFOIRQTRG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for TXFIFOIRQTRG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/i2ca/words.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `WORDS` reader"]
+pub struct R(crate::R<WORDS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<WORDS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<WORDS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<WORDS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `WORDS` writer"]
+pub struct W(crate::W<WORDS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<WORDS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<WORDS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<WORDS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Word Count value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [words](index.html) module"]
+pub struct WORDS_SPEC;
+impl crate::RegisterSpec for WORDS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [words::R](R) reader structure"]
+impl crate::Readable for WORDS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [words::W](W) writer structure"]
+impl crate::Writable for WORDS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets WORDS to value 0"]
+impl crate::Resettable for WORDS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/ioconfig.rs

@@ -0,0 +1,23 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x80 - PORTA Pin Configuration Register"]
+    pub porta: [crate::Reg<porta::PORTA_SPEC>; 32],
+    #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
+    pub portb: [crate::Reg<portb::PORTB_SPEC>; 32],
+    _reserved2: [u8; 0x0efc],
+    #[doc = "0xffc - Peripheral ID Register"]
+    pub perid: crate::Reg<perid::PERID_SPEC>,
+}
+#[doc = "PORTA register accessor: an alias for `Reg<PORTA_SPEC>`"]
+pub type PORTA = crate::Reg<porta::PORTA_SPEC>;
+#[doc = "PORTA Pin Configuration Register"]
+pub mod porta;
+#[doc = "PORTB register accessor: an alias for `Reg<PORTB_SPEC>`"]
+pub type PORTB = crate::Reg<portb::PORTB_SPEC>;
+#[doc = "PORTB Pin Configuration Register"]
+pub mod portb;
+#[doc = "PERID register accessor: an alias for `Reg<PERID_SPEC>`"]
+pub type PERID = crate::Reg<perid::PERID_SPEC>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

src/ioconfig/perid.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `PERID` reader"]
+pub struct R(crate::R<PERID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
+pub struct PERID_SPEC;
+impl crate::RegisterSpec for PERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perid::R](R) reader structure"]
+impl crate::Readable for PERID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PERID to value 0x0082_07e1"]
+impl crate::Resettable for PERID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0082_07e1
+    }
+}

src/ioconfig/porta.rs

@@ -0,0 +1,655 @@
+#[doc = "Register `PORTA[%s]` reader"]
+pub struct R(crate::R<PORTA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PORTA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PORTA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PORTA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PORTA[%s]` writer"]
+pub struct W(crate::W<PORTA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PORTA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PORTA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PORTA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum FLTTYPE_A {
+    #[doc = "0: Synchronize to system clock"]
+    SYNC = 0,
+    #[doc = "1: Direct input, no synchronization"]
+    DIRECT = 1,
+    #[doc = "2: Require 2 samples to have the same value"]
+    FILTER1 = 2,
+    #[doc = "3: Require 3 samples to have the same value"]
+    FILTER2 = 3,
+    #[doc = "4: Require 4 samples to have the same value"]
+    FILTER3 = 4,
+    #[doc = "5: Require 5 samples to have the same value"]
+    FILTER4 = 5,
+}
+impl From<FLTTYPE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: FLTTYPE_A) -> Self {
+        variant as _
+    }
+}
+#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"]
+pub struct FLTTYPE_R(crate::FieldReader<u8, FLTTYPE_A>);
+impl FLTTYPE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FLTTYPE_R(crate::FieldReader::new(bits))
+    }
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FLTTYPE_A> {
+        match self.bits {
+            0 => Some(FLTTYPE_A::SYNC),
+            1 => Some(FLTTYPE_A::DIRECT),
+            2 => Some(FLTTYPE_A::FILTER1),
+            3 => Some(FLTTYPE_A::FILTER2),
+            4 => Some(FLTTYPE_A::FILTER3),
+            5 => Some(FLTTYPE_A::FILTER4),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SYNC`"]
+    #[inline(always)]
+    pub fn is_sync(&self) -> bool {
+        **self == FLTTYPE_A::SYNC
+    }
+    #[doc = "Checks if the value of the field is `DIRECT`"]
+    #[inline(always)]
+    pub fn is_direct(&self) -> bool {
+        **self == FLTTYPE_A::DIRECT
+    }
+    #[doc = "Checks if the value of the field is `FILTER1`"]
+    #[inline(always)]
+    pub fn is_filter1(&self) -> bool {
+        **self == FLTTYPE_A::FILTER1
+    }
+    #[doc = "Checks if the value of the field is `FILTER2`"]
+    #[inline(always)]
+    pub fn is_filter2(&self) -> bool {
+        **self == FLTTYPE_A::FILTER2
+    }
+    #[doc = "Checks if the value of the field is `FILTER3`"]
+    #[inline(always)]
+    pub fn is_filter3(&self) -> bool {
+        **self == FLTTYPE_A::FILTER3
+    }
+    #[doc = "Checks if the value of the field is `FILTER4`"]
+    #[inline(always)]
+    pub fn is_filter4(&self) -> bool {
+        **self == FLTTYPE_A::FILTER4
+    }
+}
+impl core::ops::Deref for FLTTYPE_R {
+    type Target = crate::FieldReader<u8, FLTTYPE_A>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"]
+pub struct FLTTYPE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FLTTYPE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W {
+        unsafe { self.bits(variant.into()) }
+    }
+    #[doc = "Synchronize to system clock"]
+    #[inline(always)]
+    pub fn sync(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::SYNC)
+    }
+    #[doc = "Direct input, no synchronization"]
+    #[inline(always)]
+    pub fn direct(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::DIRECT)
+    }
+    #[doc = "Require 2 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter1(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER1)
+    }
+    #[doc = "Require 3 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter2(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER2)
+    }
+    #[doc = "Require 4 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter3(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER3)
+    }
+    #[doc = "Require 5 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter4(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER4)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"]
+pub struct FLTCLK_R(crate::FieldReader<u8, u8>);
+impl FLTCLK_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FLTCLK_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for FLTCLK_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"]
+pub struct FLTCLK_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FLTCLK_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
+        self.w
+    }
+}
+#[doc = "Field `INVINP` reader - Input Invert Selection"]
+pub struct INVINP_R(crate::FieldReader<bool, bool>);
+impl INVINP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        INVINP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for INVINP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `INVINP` writer - Input Invert Selection"]
+pub struct INVINP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> INVINP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `IEWO` reader - Input Enable While Output enabled"]
+pub struct IEWO_R(crate::FieldReader<bool, bool>);
+impl IEWO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IEWO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IEWO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IEWO` writer - Input Enable While Output enabled"]
+pub struct IEWO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IEWO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"]
+pub struct OPENDRN_R(crate::FieldReader<bool, bool>);
+impl OPENDRN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        OPENDRN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for OPENDRN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"]
+pub struct OPENDRN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> OPENDRN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `INVOUT` reader - Output Invert Selection"]
+pub struct INVOUT_R(crate::FieldReader<bool, bool>);
+impl INVOUT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        INVOUT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for INVOUT_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `INVOUT` writer - Output Invert Selection"]
+pub struct INVOUT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> INVOUT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"]
+pub struct PLEVEL_R(crate::FieldReader<bool, bool>);
+impl PLEVEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PLEVEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PLEVEL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"]
+pub struct PLEVEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PLEVEL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `PEN` reader - Enable Internal Pull up/down"]
+pub struct PEN_R(crate::FieldReader<bool, bool>);
+impl PEN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PEN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PEN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PEN` writer - Enable Internal Pull up/down"]
+pub struct PEN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PEN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `PWOA` reader - Enable Pull when output active"]
+pub struct PWOA_R(crate::FieldReader<bool, bool>);
+impl PWOA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PWOA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PWOA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PWOA` writer - Enable Pull when output active"]
+pub struct PWOA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PWOA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `FUNSEL` reader - Pin Function Selection"]
+pub struct FUNSEL_R(crate::FieldReader<u8, u8>);
+impl FUNSEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FUNSEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for FUNSEL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FUNSEL` writer - Pin Function Selection"]
+pub struct FUNSEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FUNSEL_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13);
+        self.w
+    }
+}
+#[doc = "Field `IODIS` reader - IO Pin Disable"]
+pub struct IODIS_R(crate::FieldReader<bool, bool>);
+impl IODIS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IODIS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IODIS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IODIS` writer - IO Pin Disable"]
+pub struct IODIS_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IODIS_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    pub fn flttype(&self) -> FLTTYPE_R {
+        FLTTYPE_R::new(self.bits as u8)
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    pub fn fltclk(&self) -> FLTCLK_R {
+        FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8)
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    pub fn invinp(&self) -> INVINP_R {
+        INVINP_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    pub fn iewo(&self) -> IEWO_R {
+        IEWO_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    pub fn opendrn(&self) -> OPENDRN_R {
+        OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    pub fn invout(&self) -> INVOUT_R {
+        INVOUT_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    pub fn plevel(&self) -> PLEVEL_R {
+        PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    pub fn pen(&self) -> PEN_R {
+        PEN_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    pub fn pwoa(&self) -> PWOA_R {
+        PWOA_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    pub fn funsel(&self) -> FUNSEL_R {
+        FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8)
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    pub fn iodis(&self) -> IODIS_R {
+        IODIS_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    pub fn flttype(&mut self) -> FLTTYPE_W {
+        FLTTYPE_W { w: self }
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    pub fn fltclk(&mut self) -> FLTCLK_W {
+        FLTCLK_W { w: self }
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    pub fn invinp(&mut self) -> INVINP_W {
+        INVINP_W { w: self }
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    pub fn iewo(&mut self) -> IEWO_W {
+        IEWO_W { w: self }
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    pub fn opendrn(&mut self) -> OPENDRN_W {
+        OPENDRN_W { w: self }
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    pub fn invout(&mut self) -> INVOUT_W {
+        INVOUT_W { w: self }
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    pub fn plevel(&mut self) -> PLEVEL_W {
+        PLEVEL_W { w: self }
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    pub fn pen(&mut self) -> PEN_W {
+        PEN_W { w: self }
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    pub fn pwoa(&mut self) -> PWOA_W {
+        PWOA_W { w: self }
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    pub fn funsel(&mut self) -> FUNSEL_W {
+        FUNSEL_W { w: self }
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    pub fn iodis(&mut self) -> IODIS_W {
+        IODIS_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PORTA Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [porta](index.html) module"]
+pub struct PORTA_SPEC;
+impl crate::RegisterSpec for PORTA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [porta::R](R) reader structure"]
+impl crate::Readable for PORTA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [porta::W](W) writer structure"]
+impl crate::Writable for PORTA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PORTA[%s]
+to value 0"]
+impl crate::Resettable for PORTA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/ioconfig/portb.rs

@@ -0,0 +1,655 @@
+#[doc = "Register `PORTB[%s]` reader"]
+pub struct R(crate::R<PORTB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PORTB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PORTB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PORTB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PORTB[%s]` writer"]
+pub struct W(crate::W<PORTB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PORTB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PORTB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PORTB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum FLTTYPE_A {
+    #[doc = "0: Synchronize to system clock"]
+    SYNC = 0,
+    #[doc = "1: Direct input, no synchronization"]
+    DIRECT = 1,
+    #[doc = "2: Require 2 samples to have the same value"]
+    FILTER1 = 2,
+    #[doc = "3: Require 3 samples to have the same value"]
+    FILTER2 = 3,
+    #[doc = "4: Require 4 samples to have the same value"]
+    FILTER3 = 4,
+    #[doc = "5: Require 5 samples to have the same value"]
+    FILTER4 = 5,
+}
+impl From<FLTTYPE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: FLTTYPE_A) -> Self {
+        variant as _
+    }
+}
+#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"]
+pub struct FLTTYPE_R(crate::FieldReader<u8, FLTTYPE_A>);
+impl FLTTYPE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FLTTYPE_R(crate::FieldReader::new(bits))
+    }
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FLTTYPE_A> {
+        match self.bits {
+            0 => Some(FLTTYPE_A::SYNC),
+            1 => Some(FLTTYPE_A::DIRECT),
+            2 => Some(FLTTYPE_A::FILTER1),
+            3 => Some(FLTTYPE_A::FILTER2),
+            4 => Some(FLTTYPE_A::FILTER3),
+            5 => Some(FLTTYPE_A::FILTER4),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SYNC`"]
+    #[inline(always)]
+    pub fn is_sync(&self) -> bool {
+        **self == FLTTYPE_A::SYNC
+    }
+    #[doc = "Checks if the value of the field is `DIRECT`"]
+    #[inline(always)]
+    pub fn is_direct(&self) -> bool {
+        **self == FLTTYPE_A::DIRECT
+    }
+    #[doc = "Checks if the value of the field is `FILTER1`"]
+    #[inline(always)]
+    pub fn is_filter1(&self) -> bool {
+        **self == FLTTYPE_A::FILTER1
+    }
+    #[doc = "Checks if the value of the field is `FILTER2`"]
+    #[inline(always)]
+    pub fn is_filter2(&self) -> bool {
+        **self == FLTTYPE_A::FILTER2
+    }
+    #[doc = "Checks if the value of the field is `FILTER3`"]
+    #[inline(always)]
+    pub fn is_filter3(&self) -> bool {
+        **self == FLTTYPE_A::FILTER3
+    }
+    #[doc = "Checks if the value of the field is `FILTER4`"]
+    #[inline(always)]
+    pub fn is_filter4(&self) -> bool {
+        **self == FLTTYPE_A::FILTER4
+    }
+}
+impl core::ops::Deref for FLTTYPE_R {
+    type Target = crate::FieldReader<u8, FLTTYPE_A>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"]
+pub struct FLTTYPE_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FLTTYPE_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W {
+        unsafe { self.bits(variant.into()) }
+    }
+    #[doc = "Synchronize to system clock"]
+    #[inline(always)]
+    pub fn sync(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::SYNC)
+    }
+    #[doc = "Direct input, no synchronization"]
+    #[inline(always)]
+    pub fn direct(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::DIRECT)
+    }
+    #[doc = "Require 2 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter1(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER1)
+    }
+    #[doc = "Require 3 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter2(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER2)
+    }
+    #[doc = "Require 4 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter3(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER3)
+    }
+    #[doc = "Require 5 samples to have the same value"]
+    #[inline(always)]
+    pub fn filter4(self) -> &'a mut W {
+        self.variant(FLTTYPE_A::FILTER4)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"]
+pub struct FLTCLK_R(crate::FieldReader<u8, u8>);
+impl FLTCLK_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FLTCLK_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for FLTCLK_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"]
+pub struct FLTCLK_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FLTCLK_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
+        self.w
+    }
+}
+#[doc = "Field `INVINP` reader - Input Invert Selection"]
+pub struct INVINP_R(crate::FieldReader<bool, bool>);
+impl INVINP_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        INVINP_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for INVINP_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `INVINP` writer - Input Invert Selection"]
+pub struct INVINP_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> INVINP_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `IEWO` reader - Input Enable While Output enabled"]
+pub struct IEWO_R(crate::FieldReader<bool, bool>);
+impl IEWO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IEWO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IEWO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IEWO` writer - Input Enable While Output enabled"]
+pub struct IEWO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IEWO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+        self.w
+    }
+}
+#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"]
+pub struct OPENDRN_R(crate::FieldReader<bool, bool>);
+impl OPENDRN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        OPENDRN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for OPENDRN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"]
+pub struct OPENDRN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> OPENDRN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `INVOUT` reader - Output Invert Selection"]
+pub struct INVOUT_R(crate::FieldReader<bool, bool>);
+impl INVOUT_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        INVOUT_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for INVOUT_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `INVOUT` writer - Output Invert Selection"]
+pub struct INVOUT_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> INVOUT_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"]
+pub struct PLEVEL_R(crate::FieldReader<bool, bool>);
+impl PLEVEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PLEVEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PLEVEL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"]
+pub struct PLEVEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PLEVEL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
+#[doc = "Field `PEN` reader - Enable Internal Pull up/down"]
+pub struct PEN_R(crate::FieldReader<bool, bool>);
+impl PEN_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PEN_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PEN_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PEN` writer - Enable Internal Pull up/down"]
+pub struct PEN_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PEN_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
+        self.w
+    }
+}
+#[doc = "Field `PWOA` reader - Enable Pull when output active"]
+pub struct PWOA_R(crate::FieldReader<bool, bool>);
+impl PWOA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PWOA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PWOA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PWOA` writer - Enable Pull when output active"]
+pub struct PWOA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PWOA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+        self.w
+    }
+}
+#[doc = "Field `FUNSEL` reader - Pin Function Selection"]
+pub struct FUNSEL_R(crate::FieldReader<u8, u8>);
+impl FUNSEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: u8) -> Self {
+        FUNSEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for FUNSEL_R {
+    type Target = crate::FieldReader<u8, u8>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `FUNSEL` writer - Pin Function Selection"]
+pub struct FUNSEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> FUNSEL_W<'a> {
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13);
+        self.w
+    }
+}
+#[doc = "Field `IODIS` reader - IO Pin Disable"]
+pub struct IODIS_R(crate::FieldReader<bool, bool>);
+impl IODIS_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IODIS_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IODIS_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IODIS` writer - IO Pin Disable"]
+pub struct IODIS_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IODIS_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    pub fn flttype(&self) -> FLTTYPE_R {
+        FLTTYPE_R::new(self.bits as u8)
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    pub fn fltclk(&self) -> FLTCLK_R {
+        FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8)
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    pub fn invinp(&self) -> INVINP_R {
+        INVINP_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    pub fn iewo(&self) -> IEWO_R {
+        IEWO_R::new(((self.bits >> 7) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    pub fn opendrn(&self) -> OPENDRN_R {
+        OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    pub fn invout(&self) -> INVOUT_R {
+        INVOUT_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    pub fn plevel(&self) -> PLEVEL_R {
+        PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    pub fn pen(&self) -> PEN_R {
+        PEN_R::new(((self.bits >> 11) & 0x01) != 0)
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    pub fn pwoa(&self) -> PWOA_R {
+        PWOA_R::new(((self.bits >> 12) & 0x01) != 0)
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    pub fn funsel(&self) -> FUNSEL_R {
+        FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8)
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    pub fn iodis(&self) -> IODIS_R {
+        IODIS_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Input Filter Selectoin"]
+    #[inline(always)]
+    pub fn flttype(&mut self) -> FLTTYPE_W {
+        FLTTYPE_W { w: self }
+    }
+    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
+    #[inline(always)]
+    pub fn fltclk(&mut self) -> FLTCLK_W {
+        FLTCLK_W { w: self }
+    }
+    #[doc = "Bit 6 - Input Invert Selection"]
+    #[inline(always)]
+    pub fn invinp(&mut self) -> INVINP_W {
+        INVINP_W { w: self }
+    }
+    #[doc = "Bit 7 - Input Enable While Output enabled"]
+    #[inline(always)]
+    pub fn iewo(&mut self) -> IEWO_W {
+        IEWO_W { w: self }
+    }
+    #[doc = "Bit 8 - Output Open Drain Mode"]
+    #[inline(always)]
+    pub fn opendrn(&mut self) -> OPENDRN_W {
+        OPENDRN_W { w: self }
+    }
+    #[doc = "Bit 9 - Output Invert Selection"]
+    #[inline(always)]
+    pub fn invout(&mut self) -> INVOUT_W {
+        INVOUT_W { w: self }
+    }
+    #[doc = "Bit 10 - Internal Pull up/down level"]
+    #[inline(always)]
+    pub fn plevel(&mut self) -> PLEVEL_W {
+        PLEVEL_W { w: self }
+    }
+    #[doc = "Bit 11 - Enable Internal Pull up/down"]
+    #[inline(always)]
+    pub fn pen(&mut self) -> PEN_W {
+        PEN_W { w: self }
+    }
+    #[doc = "Bit 12 - Enable Pull when output active"]
+    #[inline(always)]
+    pub fn pwoa(&mut self) -> PWOA_W {
+        PWOA_W { w: self }
+    }
+    #[doc = "Bits 13:15 - Pin Function Selection"]
+    #[inline(always)]
+    pub fn funsel(&mut self) -> FUNSEL_W {
+        FUNSEL_W { w: self }
+    }
+    #[doc = "Bit 16 - IO Pin Disable"]
+    #[inline(always)]
+    pub fn iodis(&mut self) -> IODIS_W {
+        IODIS_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PORTB Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portb](index.html) module"]
+pub struct PORTB_SPEC;
+impl crate::RegisterSpec for PORTB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [portb::R](R) reader structure"]
+impl crate::Readable for PORTB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [portb::W](W) writer structure"]
+impl crate::Writable for PORTB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PORTB[%s]
+to value 0x0800"]
+impl crate::Resettable for PORTB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0800
+    }
+}

src/irqsel.rs

@@ -0,0 +1,121 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
+    pub porta: [crate::Reg<porta::PORTA_SPEC>; 32],
+    #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
+    pub portb: [crate::Reg<portb::PORTB_SPEC>; 32],
+    #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
+    pub tim: [crate::Reg<tim::TIM_SPEC>; 32],
+    #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
+    pub uart: [crate::Reg<uart::UART_SPEC>; 4],
+    #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
+    pub spi: [crate::Reg<spi::SPI_SPEC>; 4],
+    #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
+    pub i2c_ms: [crate::Reg<i2c_ms::I2C_MS_SPEC>; 4],
+    #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
+    pub i2c_sl: [crate::Reg<i2c_sl::I2C_SL_SPEC>; 4],
+    #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
+    pub int_ram_sbe: crate::Reg<int_ram_sbe::INT_RAM_SBE_SPEC>,
+    #[doc = "0x1c4 - Internal Memory RAM MBE Interrupt Redirect Selection"]
+    pub int_ram_mbe: crate::Reg<int_ram_mbe::INT_RAM_MBE_SPEC>,
+    #[doc = "0x1c8 - Internal Memory ROM SBE Interrupt Redirect Selection"]
+    pub int_rom_sbe: crate::Reg<int_rom_sbe::INT_ROM_SBE_SPEC>,
+    #[doc = "0x1cc - Internal Memory ROM MBE Interrupt Redirect Selection"]
+    pub int_rom_mbe: crate::Reg<int_rom_mbe::INT_ROM_MBE_SPEC>,
+    #[doc = "0x1d0 - Processor TXEV Interrupt Redirect Selection"]
+    pub txev: crate::Reg<txev::TXEV_SPEC>,
+    _reserved12: [u8; 0x062c],
+    #[doc = "0x800..0x880 - Interrupt Status Register"]
+    pub irqs: [crate::Reg<irqs::IRQS_SPEC>; 32],
+    _reserved13: [u8; 0x68],
+    #[doc = "0x8e8 - EDBGRQ Status Register"]
+    pub edbgrq: crate::Reg<edbgrq::EDBGRQ_SPEC>,
+    #[doc = "0x8ec - MERESET Status Register"]
+    pub mereset: crate::Reg<mereset::MERESET_SPEC>,
+    #[doc = "0x8f0 - WATCHDOG Status Register"]
+    pub watchdog: crate::Reg<watchdog::WATCHDOG_SPEC>,
+    #[doc = "0x8f4 - RXEV Status Register"]
+    pub rxev: crate::Reg<rxev::RXEV_SPEC>,
+    #[doc = "0x8f8 - NMI Status Register"]
+    pub nmi: crate::Reg<nmi::NMI_SPEC>,
+    _reserved18: [u8; 0x0700],
+    #[doc = "0xffc - Peripheral ID Register"]
+    pub perid: crate::Reg<perid::PERID_SPEC>,
+}
+#[doc = "INT_RAM_SBE register accessor: an alias for `Reg<INT_RAM_SBE_SPEC>`"]
+pub type INT_RAM_SBE = crate::Reg<int_ram_sbe::INT_RAM_SBE_SPEC>;
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
+pub mod int_ram_sbe;
+#[doc = "PORTA register accessor: an alias for `Reg<PORTA_SPEC>`"]
+pub type PORTA = crate::Reg<porta::PORTA_SPEC>;
+#[doc = "PORTA Interrupt Redirect Selection"]
+pub mod porta;
+#[doc = "PORTB register accessor: an alias for `Reg<PORTB_SPEC>`"]
+pub type PORTB = crate::Reg<portb::PORTB_SPEC>;
+#[doc = "PORTB Interrupt Redirect Selection"]
+pub mod portb;
+#[doc = "TIM register accessor: an alias for `Reg<TIM_SPEC>`"]
+pub type TIM = crate::Reg<tim::TIM_SPEC>;
+#[doc = "TIM Interrupt Redirect Selection"]
+pub mod tim;
+#[doc = "UART register accessor: an alias for `Reg<UART_SPEC>`"]
+pub type UART = crate::Reg<uart::UART_SPEC>;
+#[doc = "UART Interrupt Redirect Selection"]
+pub mod uart;
+#[doc = "SPI register accessor: an alias for `Reg<SPI_SPEC>`"]
+pub type SPI = crate::Reg<spi::SPI_SPEC>;
+#[doc = "SPI Interrupt Redirect Selection"]
+pub mod spi;
+#[doc = "I2C_MS register accessor: an alias for `Reg<I2C_MS_SPEC>`"]
+pub type I2C_MS = crate::Reg<i2c_ms::I2C_MS_SPEC>;
+#[doc = "Master I2C Interrupt Redirect Selection"]
+pub mod i2c_ms;
+#[doc = "I2C_SL register accessor: an alias for `Reg<I2C_SL_SPEC>`"]
+pub type I2C_SL = crate::Reg<i2c_sl::I2C_SL_SPEC>;
+#[doc = "Slave I2C Interrupt Redirect Selection"]
+pub mod i2c_sl;
+#[doc = "INT_RAM_MBE register accessor: an alias for `Reg<INT_RAM_MBE_SPEC>`"]
+pub type INT_RAM_MBE = crate::Reg<int_ram_mbe::INT_RAM_MBE_SPEC>;
+#[doc = "Internal Memory RAM MBE Interrupt Redirect Selection"]
+pub mod int_ram_mbe;
+#[doc = "INT_ROM_SBE register accessor: an alias for `Reg<INT_ROM_SBE_SPEC>`"]
+pub type INT_ROM_SBE = crate::Reg<int_rom_sbe::INT_ROM_SBE_SPEC>;
+#[doc = "Internal Memory ROM SBE Interrupt Redirect Selection"]
+pub mod int_rom_sbe;
+#[doc = "INT_ROM_MBE register accessor: an alias for `Reg<INT_ROM_MBE_SPEC>`"]
+pub type INT_ROM_MBE = crate::Reg<int_rom_mbe::INT_ROM_MBE_SPEC>;
+#[doc = "Internal Memory ROM MBE Interrupt Redirect Selection"]
+pub mod int_rom_mbe;
+#[doc = "TXEV register accessor: an alias for `Reg<TXEV_SPEC>`"]
+pub type TXEV = crate::Reg<txev::TXEV_SPEC>;
+#[doc = "Processor TXEV Interrupt Redirect Selection"]
+pub mod txev;
+#[doc = "NMI register accessor: an alias for `Reg<NMI_SPEC>`"]
+pub type NMI = crate::Reg<nmi::NMI_SPEC>;
+#[doc = "NMI Status Register"]
+pub mod nmi;
+#[doc = "RXEV register accessor: an alias for `Reg<RXEV_SPEC>`"]
+pub type RXEV = crate::Reg<rxev::RXEV_SPEC>;
+#[doc = "RXEV Status Register"]
+pub mod rxev;
+#[doc = "WATCHDOG register accessor: an alias for `Reg<WATCHDOG_SPEC>`"]
+pub type WATCHDOG = crate::Reg<watchdog::WATCHDOG_SPEC>;
+#[doc = "WATCHDOG Status Register"]
+pub mod watchdog;
+#[doc = "MERESET register accessor: an alias for `Reg<MERESET_SPEC>`"]
+pub type MERESET = crate::Reg<mereset::MERESET_SPEC>;
+#[doc = "MERESET Status Register"]
+pub mod mereset;
+#[doc = "EDBGRQ register accessor: an alias for `Reg<EDBGRQ_SPEC>`"]
+pub type EDBGRQ = crate::Reg<edbgrq::EDBGRQ_SPEC>;
+#[doc = "EDBGRQ Status Register"]
+pub mod edbgrq;
+#[doc = "IRQS register accessor: an alias for `Reg<IRQS_SPEC>`"]
+pub type IRQS = crate::Reg<irqs::IRQS_SPEC>;
+#[doc = "Interrupt Status Register"]
+pub mod irqs;
+#[doc = "PERID register accessor: an alias for `Reg<PERID_SPEC>`"]
+pub type PERID = crate::Reg<perid::PERID_SPEC>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

src/irqsel/edbgrq.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `EDBGRQ` reader"]
+pub struct R(crate::R<EDBGRQ_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EDBGRQ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EDBGRQ_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EDBGRQ_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "EDBGRQ Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edbgrq](index.html) module"]
+pub struct EDBGRQ_SPEC;
+impl crate::RegisterSpec for EDBGRQ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [edbgrq::R](R) reader structure"]
+impl crate::Readable for EDBGRQ_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets EDBGRQ to value 0"]
+impl crate::Resettable for EDBGRQ_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/irqsel/i2c_ms.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `I2C_MS[%s]` reader"]
+pub struct R(crate::R<I2C_MS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<I2C_MS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<I2C_MS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<I2C_MS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `I2C_MS[%s]` writer"]
+pub struct W(crate::W<I2C_MS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<I2C_MS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<I2C_MS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<I2C_MS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Master I2C Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2c_ms](index.html) module"]
+pub struct I2C_MS_SPEC;
+impl crate::RegisterSpec for I2C_MS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [i2c_ms::R](R) reader structure"]
+impl crate::Readable for I2C_MS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [i2c_ms::W](W) writer structure"]
+impl crate::Writable for I2C_MS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets I2C_MS[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for I2C_MS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/i2c_sl.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `I2C_SL[%s]` reader"]
+pub struct R(crate::R<I2C_SL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<I2C_SL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<I2C_SL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<I2C_SL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `I2C_SL[%s]` writer"]
+pub struct W(crate::W<I2C_SL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<I2C_SL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<I2C_SL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<I2C_SL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Slave I2C Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2c_sl](index.html) module"]
+pub struct I2C_SL_SPEC;
+impl crate::RegisterSpec for I2C_SL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [i2c_sl::R](R) reader structure"]
+impl crate::Readable for I2C_SL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [i2c_sl::W](W) writer structure"]
+impl crate::Writable for I2C_SL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets I2C_SL[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for I2C_SL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/int_ram_mbe.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `INT_RAM_MBE` reader"]
+pub struct R(crate::R<INT_RAM_MBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INT_RAM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INT_RAM_MBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INT_RAM_MBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INT_RAM_MBE` writer"]
+pub struct W(crate::W<INT_RAM_MBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INT_RAM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INT_RAM_MBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INT_RAM_MBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Internal Memory RAM MBE Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_ram_mbe](index.html) module"]
+pub struct INT_RAM_MBE_SPEC;
+impl crate::RegisterSpec for INT_RAM_MBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [int_ram_mbe::R](R) reader structure"]
+impl crate::Readable for INT_RAM_MBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [int_ram_mbe::W](W) writer structure"]
+impl crate::Writable for INT_RAM_MBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INT_RAM_MBE to value 0xffff_ffff"]
+impl crate::Resettable for INT_RAM_MBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/int_ram_sbe.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `INT_RAM_SBE` reader"]
+pub struct R(crate::R<INT_RAM_SBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INT_RAM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INT_RAM_SBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INT_RAM_SBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INT_RAM_SBE` writer"]
+pub struct W(crate::W<INT_RAM_SBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INT_RAM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INT_RAM_SBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INT_RAM_SBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_ram_sbe](index.html) module"]
+pub struct INT_RAM_SBE_SPEC;
+impl crate::RegisterSpec for INT_RAM_SBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [int_ram_sbe::R](R) reader structure"]
+impl crate::Readable for INT_RAM_SBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [int_ram_sbe::W](W) writer structure"]
+impl crate::Writable for INT_RAM_SBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"]
+impl crate::Resettable for INT_RAM_SBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/int_rom_mbe.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `INT_ROM_MBE` reader"]
+pub struct R(crate::R<INT_ROM_MBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INT_ROM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INT_ROM_MBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INT_ROM_MBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INT_ROM_MBE` writer"]
+pub struct W(crate::W<INT_ROM_MBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INT_ROM_MBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INT_ROM_MBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INT_ROM_MBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Internal Memory ROM MBE Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_rom_mbe](index.html) module"]
+pub struct INT_ROM_MBE_SPEC;
+impl crate::RegisterSpec for INT_ROM_MBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [int_rom_mbe::R](R) reader structure"]
+impl crate::Readable for INT_ROM_MBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [int_rom_mbe::W](W) writer structure"]
+impl crate::Writable for INT_ROM_MBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INT_ROM_MBE to value 0xffff_ffff"]
+impl crate::Resettable for INT_ROM_MBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/int_rom_sbe.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `INT_ROM_SBE` reader"]
+pub struct R(crate::R<INT_ROM_SBE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INT_ROM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INT_ROM_SBE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INT_ROM_SBE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INT_ROM_SBE` writer"]
+pub struct W(crate::W<INT_ROM_SBE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INT_ROM_SBE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INT_ROM_SBE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INT_ROM_SBE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Internal Memory ROM SBE Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_rom_sbe](index.html) module"]
+pub struct INT_ROM_SBE_SPEC;
+impl crate::RegisterSpec for INT_ROM_SBE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [int_rom_sbe::R](R) reader structure"]
+impl crate::Readable for INT_ROM_SBE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [int_rom_sbe::W](W) writer structure"]
+impl crate::Writable for INT_ROM_SBE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INT_ROM_SBE to value 0xffff_ffff"]
+impl crate::Resettable for INT_ROM_SBE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/irqs.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `IRQS[%s]` reader"]
+pub struct R(crate::R<IRQS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqs](index.html) module"]
+pub struct IRQS_SPEC;
+impl crate::RegisterSpec for IRQS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irqs::R](R) reader structure"]
+impl crate::Readable for IRQS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQS[%s]
+to value 0"]
+impl crate::Resettable for IRQS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/irqsel/mereset.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `MERESET` reader"]
+pub struct R(crate::R<MERESET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MERESET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MERESET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MERESET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "MERESET Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mereset](index.html) module"]
+pub struct MERESET_SPEC;
+impl crate::RegisterSpec for MERESET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mereset::R](R) reader structure"]
+impl crate::Readable for MERESET_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets MERESET to value 0"]
+impl crate::Resettable for MERESET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/irqsel/nmi.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `NMI` reader"]
+pub struct R(crate::R<NMI_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NMI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NMI_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NMI_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "NMI Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmi](index.html) module"]
+pub struct NMI_SPEC;
+impl crate::RegisterSpec for NMI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [nmi::R](R) reader structure"]
+impl crate::Readable for NMI_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets NMI to value 0"]
+impl crate::Resettable for NMI_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/irqsel/perid.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `PERID` reader"]
+pub struct R(crate::R<PERID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
+pub struct PERID_SPEC;
+impl crate::RegisterSpec for PERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perid::R](R) reader structure"]
+impl crate::Readable for PERID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PERID to value 0x0080_07e1"]
+impl crate::Resettable for PERID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0080_07e1
+    }
+}

src/irqsel/porta.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `PORTA[%s]` reader"]
+pub struct R(crate::R<PORTA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PORTA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PORTA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PORTA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PORTA[%s]` writer"]
+pub struct W(crate::W<PORTA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PORTA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PORTA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PORTA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PORTA Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [porta](index.html) module"]
+pub struct PORTA_SPEC;
+impl crate::RegisterSpec for PORTA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [porta::R](R) reader structure"]
+impl crate::Readable for PORTA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [porta::W](W) writer structure"]
+impl crate::Writable for PORTA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PORTA[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for PORTA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/portb.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `PORTB[%s]` reader"]
+pub struct R(crate::R<PORTB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PORTB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PORTB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PORTB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PORTB[%s]` writer"]
+pub struct W(crate::W<PORTB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PORTB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PORTB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PORTB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "PORTB Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portb](index.html) module"]
+pub struct PORTB_SPEC;
+impl crate::RegisterSpec for PORTB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [portb::R](R) reader structure"]
+impl crate::Readable for PORTB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [portb::W](W) writer structure"]
+impl crate::Writable for PORTB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PORTB[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for PORTB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/rxev.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `RXEV` reader"]
+pub struct R(crate::R<RXEV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXEV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXEV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXEV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "RXEV Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxev](index.html) module"]
+pub struct RXEV_SPEC;
+impl crate::RegisterSpec for RXEV_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxev::R](R) reader structure"]
+impl crate::Readable for RXEV_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RXEV to value 0"]
+impl crate::Resettable for RXEV_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/irqsel/spi.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `SPI[%s]` reader"]
+pub struct R(crate::R<SPI_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SPI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SPI_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SPI_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SPI[%s]` writer"]
+pub struct W(crate::W<SPI_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SPI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SPI_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SPI_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi](index.html) module"]
+pub struct SPI_SPEC;
+impl crate::RegisterSpec for SPI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [spi::R](R) reader structure"]
+impl crate::Readable for SPI_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [spi::W](W) writer structure"]
+impl crate::Writable for SPI_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SPI[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for SPI_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/tim.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `TIM[%s]` reader"]
+pub struct R(crate::R<TIM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TIM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TIM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TIM[%s]` writer"]
+pub struct W(crate::W<TIM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TIM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TIM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TIM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "TIM Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim](index.html) module"]
+pub struct TIM_SPEC;
+impl crate::RegisterSpec for TIM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [tim::R](R) reader structure"]
+impl crate::Readable for TIM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [tim::W](W) writer structure"]
+impl crate::Writable for TIM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TIM[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for TIM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/txev.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `TXEV` reader"]
+pub struct R(crate::R<TXEV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXEV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXEV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXEV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TXEV` writer"]
+pub struct W(crate::W<TXEV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TXEV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TXEV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TXEV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Processor TXEV Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txev](index.html) module"]
+pub struct TXEV_SPEC;
+impl crate::RegisterSpec for TXEV_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txev::R](R) reader structure"]
+impl crate::Readable for TXEV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [txev::W](W) writer structure"]
+impl crate::Writable for TXEV_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TXEV to value 0xffff_ffff"]
+impl crate::Resettable for TXEV_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/uart.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `UART[%s]` reader"]
+pub struct R(crate::R<UART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<UART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<UART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<UART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `UART[%s]` writer"]
+pub struct W(crate::W<UART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<UART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<UART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<UART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "UART Interrupt Redirect Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart](index.html) module"]
+pub struct UART_SPEC;
+impl crate::RegisterSpec for UART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [uart::R](R) reader structure"]
+impl crate::Readable for UART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [uart::W](W) writer structure"]
+impl crate::Writable for UART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets UART[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for UART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

src/irqsel/watchdog.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `WATCHDOG` reader"]
+pub struct R(crate::R<WATCHDOG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<WATCHDOG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<WATCHDOG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<WATCHDOG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ACTIVE` reader - Active"]
+pub struct ACTIVE_R(crate::FieldReader<bool, bool>);
+impl ACTIVE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        ACTIVE_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for ACTIVE_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active"]
+    #[inline(always)]
+    pub fn active(&self) -> ACTIVE_R {
+        ACTIVE_R::new(self.bits != 0)
+    }
+}
+#[doc = "WATCHDOG Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [watchdog](index.html) module"]
+pub struct WATCHDOG_SPEC;
+impl crate::RegisterSpec for WATCHDOG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [watchdog::R](R) reader structure"]
+impl crate::Readable for WATCHDOG_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets WATCHDOG to value 0"]
+impl crate::Resettable for WATCHDOG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta.rs

@@ -0,0 +1,380 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved_0_datain: [u8; 0x04],
+    _reserved_1_datainraw: [u8; 0x04],
+    _reserved_2_dataout: [u8; 0x04],
+    _reserved_3_dataoutraw: [u8; 0x04],
+    _reserved_4_setout: [u8; 0x04],
+    _reserved_5_clrout: [u8; 0x04],
+    _reserved_6_togout: [u8; 0x04],
+    _reserved_7_datamask: [u8; 0x04],
+    _reserved_8_dir: [u8; 0x04],
+    _reserved_9_pulse: [u8; 0x04],
+    _reserved_10_pulsebase: [u8; 0x04],
+    _reserved_11_delay: [u8; 0x04],
+    _reserved_12_delay: [u8; 0x04],
+    #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
+    pub irq_sen: crate::Reg<irq_sen::IRQ_SEN_SPEC>,
+    #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
+    pub irq_edge: crate::Reg<irq_edge::IRQ_EDGE_SPEC>,
+    #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
+    pub irq_evt: crate::Reg<irq_evt::IRQ_EVT_SPEC>,
+    #[doc = "0x40 - Interrupt Enable Register"]
+    pub irq_enb: crate::Reg<irq_enb::IRQ_ENB_SPEC>,
+    #[doc = "0x44 - Raw Interrupt Status"]
+    pub irq_raw: crate::Reg<irq_raw::IRQ_RAW_SPEC>,
+    #[doc = "0x48 - Masked Interrupt Status"]
+    pub irq_end: crate::Reg<irq_end::IRQ_END_SPEC>,
+    #[doc = "0x4c - Edge Status Register"]
+    pub edge_status: crate::Reg<edge_status::EDGE_STATUS_SPEC>,
+    _reserved20: [u8; 0x0fac],
+    #[doc = "0xffc - Peripheral ID Register"]
+    pub perid: crate::Reg<perid::PERID_SPEC>,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Data In Register by Byte"]
+    #[inline(always)]
+    pub fn datainbyte(&self) -> &[crate::Reg<datainbyte::DATAINBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(0usize)
+                as *const [crate::Reg<datainbyte::DATAINBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x00 - Data In Register"]
+    #[inline(always)]
+    pub fn datain(&self) -> &crate::Reg<datain::DATAIN_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(0usize)
+                as *const crate::Reg<datain::DATAIN_SPEC>)
+        }
+    }
+    #[doc = "0x04 - Data In Raw Register by Byte"]
+    #[inline(always)]
+    pub fn datainrawbyte(&self) -> &[crate::Reg<datainrawbyte::DATAINRAWBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(4usize)
+                as *const [crate::Reg<datainrawbyte::DATAINRAWBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x04 - Data In Raw Register"]
+    #[inline(always)]
+    pub fn datainraw(&self) -> &crate::Reg<datainraw::DATAINRAW_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(4usize)
+                as *const crate::Reg<datainraw::DATAINRAW_SPEC>)
+        }
+    }
+    #[doc = "0x08 - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn dataoutbyte(&self) -> &[crate::Reg<dataoutbyte::DATAOUTBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(8usize)
+                as *const [crate::Reg<dataoutbyte::DATAOUTBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x08 - Data Out Register"]
+    #[inline(always)]
+    pub fn dataout(&self) -> &crate::Reg<dataout::DATAOUT_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(8usize)
+                as *const crate::Reg<dataout::DATAOUT_SPEC>)
+        }
+    }
+    #[doc = "0x0c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn dataoutrawbyte(&self) -> &[crate::Reg<dataoutrawbyte::DATAOUTRAWBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(12usize)
+                as *const [crate::Reg<dataoutrawbyte::DATAOUTRAWBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x0c - Data Out Register"]
+    #[inline(always)]
+    pub fn dataoutraw(&self) -> &crate::Reg<dataoutraw::DATAOUTRAW_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(12usize)
+                as *const crate::Reg<dataoutraw::DATAOUTRAW_SPEC>)
+        }
+    }
+    #[doc = "0x10 - Set Out Register by Byte"]
+    #[inline(always)]
+    pub fn setoutbyte(&self) -> &[crate::Reg<setoutbyte::SETOUTBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(16usize)
+                as *const [crate::Reg<setoutbyte::SETOUTBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x10 - Set Out Register"]
+    #[inline(always)]
+    pub fn setout(&self) -> &crate::Reg<setout::SETOUT_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(16usize)
+                as *const crate::Reg<setout::SETOUT_SPEC>)
+        }
+    }
+    #[doc = "0x14 - Clear Out Register by Byte"]
+    #[inline(always)]
+    pub fn clroutbyte(&self) -> &[crate::Reg<clroutbyte::CLROUTBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(20usize)
+                as *const [crate::Reg<clroutbyte::CLROUTBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x14 - Clear Out Register"]
+    #[inline(always)]
+    pub fn clrout(&self) -> &crate::Reg<clrout::CLROUT_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(20usize)
+                as *const crate::Reg<clrout::CLROUT_SPEC>)
+        }
+    }
+    #[doc = "0x18 - Toggle Out Register by Byte"]
+    #[inline(always)]
+    pub fn togoutbyte(&self) -> &[crate::Reg<togoutbyte::TOGOUTBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(24usize)
+                as *const [crate::Reg<togoutbyte::TOGOUTBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x18 - Toggle Out Register"]
+    #[inline(always)]
+    pub fn togout(&self) -> &crate::Reg<togout::TOGOUT_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(24usize)
+                as *const crate::Reg<togout::TOGOUT_SPEC>)
+        }
+    }
+    #[doc = "0x1c - Data Out Register by Byte"]
+    #[inline(always)]
+    pub fn datamaskbyte(&self) -> &[crate::Reg<datamaskbyte::DATAMASKBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(28usize)
+                as *const [crate::Reg<datamaskbyte::DATAMASKBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x1c - Data mask Register"]
+    #[inline(always)]
+    pub fn datamask(&self) -> &crate::Reg<datamask::DATAMASK_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(28usize)
+                as *const crate::Reg<datamask::DATAMASK_SPEC>)
+        }
+    }
+    #[doc = "0x20 - Direction Register by Byte"]
+    #[inline(always)]
+    pub fn dirbyte(&self) -> &[crate::Reg<dirbyte::DIRBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(32usize)
+                as *const [crate::Reg<dirbyte::DIRBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x20 - Direction Register (1:Output, 0:Input)"]
+    #[inline(always)]
+    pub fn dir(&self) -> &crate::Reg<dir::DIR_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(32usize)
+                as *const crate::Reg<dir::DIR_SPEC>)
+        }
+    }
+    #[doc = "0x24 - Pulse Mode Register by Byte"]
+    #[inline(always)]
+    pub fn pulsebyte(&self) -> &[crate::Reg<pulsebyte::PULSEBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(36usize)
+                as *const [crate::Reg<pulsebyte::PULSEBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x24 - Pulse Mode Register"]
+    #[inline(always)]
+    pub fn pulse(&self) -> &crate::Reg<pulse::PULSE_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(36usize)
+                as *const crate::Reg<pulse::PULSE_SPEC>)
+        }
+    }
+    #[doc = "0x28 - Pulse Base Mode Register by Byte"]
+    #[inline(always)]
+    pub fn pulsebasebyte(&self) -> &[crate::Reg<pulsebasebyte::PULSEBASEBYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(40usize)
+                as *const [crate::Reg<pulsebasebyte::PULSEBASEBYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x28 - Pulse Base Value Register"]
+    #[inline(always)]
+    pub fn pulsebase(&self) -> &crate::Reg<pulsebase::PULSEBASE_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(40usize)
+                as *const crate::Reg<pulsebase::PULSEBASE_SPEC>)
+        }
+    }
+    #[doc = "0x2c - Delay1 Register by Byte"]
+    #[inline(always)]
+    pub fn delay1byte(&self) -> &[crate::Reg<delay1byte::DELAY1BYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(44usize)
+                as *const [crate::Reg<delay1byte::DELAY1BYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x2c - Delay1 Register"]
+    #[inline(always)]
+    pub fn delay1(&self) -> &crate::Reg<delay1::DELAY1_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(44usize)
+                as *const crate::Reg<delay1::DELAY1_SPEC>)
+        }
+    }
+    #[doc = "0x30 - Delay2 Register by Byte"]
+    #[inline(always)]
+    pub fn delay2byte(&self) -> &[crate::Reg<delay2byte::DELAY2BYTE_SPEC>; 4] {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(48usize)
+                as *const [crate::Reg<delay2byte::DELAY2BYTE_SPEC>; 4])
+        }
+    }
+    #[doc = "0x30 - Delay2 Register"]
+    #[inline(always)]
+    pub fn delay2(&self) -> &crate::Reg<delay2::DELAY2_SPEC> {
+        unsafe {
+            &*(((self as *const Self) as *const u8).add(48usize)
+                as *const crate::Reg<delay2::DELAY2_SPEC>)
+        }
+    }
+}
+#[doc = "DATAIN register accessor: an alias for `Reg<DATAIN_SPEC>`"]
+pub type DATAIN = crate::Reg<datain::DATAIN_SPEC>;
+#[doc = "Data In Register"]
+pub mod datain;
+#[doc = "DATAINBYTE register accessor: an alias for `Reg<DATAINBYTE_SPEC>`"]
+pub type DATAINBYTE = crate::Reg<datainbyte::DATAINBYTE_SPEC>;
+#[doc = "Data In Register by Byte"]
+pub mod datainbyte;
+#[doc = "DATAINRAW register accessor: an alias for `Reg<DATAINRAW_SPEC>`"]
+pub type DATAINRAW = crate::Reg<datainraw::DATAINRAW_SPEC>;
+#[doc = "Data In Raw Register"]
+pub mod datainraw;
+#[doc = "DATAINRAWBYTE register accessor: an alias for `Reg<DATAINRAWBYTE_SPEC>`"]
+pub type DATAINRAWBYTE = crate::Reg<datainrawbyte::DATAINRAWBYTE_SPEC>;
+#[doc = "Data In Raw Register by Byte"]
+pub mod datainrawbyte;
+#[doc = "DATAOUT register accessor: an alias for `Reg<DATAOUT_SPEC>`"]
+pub type DATAOUT = crate::Reg<dataout::DATAOUT_SPEC>;
+#[doc = "Data Out Register"]
+pub mod dataout;
+#[doc = "DATAOUTBYTE register accessor: an alias for `Reg<DATAOUTBYTE_SPEC>`"]
+pub type DATAOUTBYTE = crate::Reg<dataoutbyte::DATAOUTBYTE_SPEC>;
+#[doc = "Data Out Register by Byte"]
+pub mod dataoutbyte;
+#[doc = "DATAOUTRAW register accessor: an alias for `Reg<DATAOUTRAW_SPEC>`"]
+pub type DATAOUTRAW = crate::Reg<dataoutraw::DATAOUTRAW_SPEC>;
+#[doc = "Data Out Register"]
+pub mod dataoutraw;
+#[doc = "DATAOUTRAWBYTE register accessor: an alias for `Reg<DATAOUTRAWBYTE_SPEC>`"]
+pub type DATAOUTRAWBYTE = crate::Reg<dataoutrawbyte::DATAOUTRAWBYTE_SPEC>;
+#[doc = "Data Out Register by Byte"]
+pub mod dataoutrawbyte;
+#[doc = "SETOUT register accessor: an alias for `Reg<SETOUT_SPEC>`"]
+pub type SETOUT = crate::Reg<setout::SETOUT_SPEC>;
+#[doc = "Set Out Register"]
+pub mod setout;
+#[doc = "SETOUTBYTE register accessor: an alias for `Reg<SETOUTBYTE_SPEC>`"]
+pub type SETOUTBYTE = crate::Reg<setoutbyte::SETOUTBYTE_SPEC>;
+#[doc = "Set Out Register by Byte"]
+pub mod setoutbyte;
+#[doc = "CLROUT register accessor: an alias for `Reg<CLROUT_SPEC>`"]
+pub type CLROUT = crate::Reg<clrout::CLROUT_SPEC>;
+#[doc = "Clear Out Register"]
+pub mod clrout;
+#[doc = "CLROUTBYTE register accessor: an alias for `Reg<CLROUTBYTE_SPEC>`"]
+pub type CLROUTBYTE = crate::Reg<clroutbyte::CLROUTBYTE_SPEC>;
+#[doc = "Clear Out Register by Byte"]
+pub mod clroutbyte;
+#[doc = "TOGOUT register accessor: an alias for `Reg<TOGOUT_SPEC>`"]
+pub type TOGOUT = crate::Reg<togout::TOGOUT_SPEC>;
+#[doc = "Toggle Out Register"]
+pub mod togout;
+#[doc = "TOGOUTBYTE register accessor: an alias for `Reg<TOGOUTBYTE_SPEC>`"]
+pub type TOGOUTBYTE = crate::Reg<togoutbyte::TOGOUTBYTE_SPEC>;
+#[doc = "Toggle Out Register by Byte"]
+pub mod togoutbyte;
+#[doc = "DATAMASK register accessor: an alias for `Reg<DATAMASK_SPEC>`"]
+pub type DATAMASK = crate::Reg<datamask::DATAMASK_SPEC>;
+#[doc = "Data mask Register"]
+pub mod datamask;
+#[doc = "DATAMASKBYTE register accessor: an alias for `Reg<DATAMASKBYTE_SPEC>`"]
+pub type DATAMASKBYTE = crate::Reg<datamaskbyte::DATAMASKBYTE_SPEC>;
+#[doc = "Data Out Register by Byte"]
+pub mod datamaskbyte;
+#[doc = "DIR register accessor: an alias for `Reg<DIR_SPEC>`"]
+pub type DIR = crate::Reg<dir::DIR_SPEC>;
+#[doc = "Direction Register (1:Output, 0:Input)"]
+pub mod dir;
+#[doc = "DIRBYTE register accessor: an alias for `Reg<DIRBYTE_SPEC>`"]
+pub type DIRBYTE = crate::Reg<dirbyte::DIRBYTE_SPEC>;
+#[doc = "Direction Register by Byte"]
+pub mod dirbyte;
+#[doc = "PULSE register accessor: an alias for `Reg<PULSE_SPEC>`"]
+pub type PULSE = crate::Reg<pulse::PULSE_SPEC>;
+#[doc = "Pulse Mode Register"]
+pub mod pulse;
+#[doc = "PULSEBYTE register accessor: an alias for `Reg<PULSEBYTE_SPEC>`"]
+pub type PULSEBYTE = crate::Reg<pulsebyte::PULSEBYTE_SPEC>;
+#[doc = "Pulse Mode Register by Byte"]
+pub mod pulsebyte;
+#[doc = "PULSEBASE register accessor: an alias for `Reg<PULSEBASE_SPEC>`"]
+pub type PULSEBASE = crate::Reg<pulsebase::PULSEBASE_SPEC>;
+#[doc = "Pulse Base Value Register"]
+pub mod pulsebase;
+#[doc = "PULSEBASEBYTE register accessor: an alias for `Reg<PULSEBASEBYTE_SPEC>`"]
+pub type PULSEBASEBYTE = crate::Reg<pulsebasebyte::PULSEBASEBYTE_SPEC>;
+#[doc = "Pulse Base Mode Register by Byte"]
+pub mod pulsebasebyte;
+#[doc = "DELAY1 register accessor: an alias for `Reg<DELAY1_SPEC>`"]
+pub type DELAY1 = crate::Reg<delay1::DELAY1_SPEC>;
+#[doc = "Delay1 Register"]
+pub mod delay1;
+#[doc = "DELAY1BYTE register accessor: an alias for `Reg<DELAY1BYTE_SPEC>`"]
+pub type DELAY1BYTE = crate::Reg<delay1byte::DELAY1BYTE_SPEC>;
+#[doc = "Delay1 Register by Byte"]
+pub mod delay1byte;
+#[doc = "DELAY2 register accessor: an alias for `Reg<DELAY2_SPEC>`"]
+pub type DELAY2 = crate::Reg<delay2::DELAY2_SPEC>;
+#[doc = "Delay2 Register"]
+pub mod delay2;
+#[doc = "DELAY2BYTE register accessor: an alias for `Reg<DELAY2BYTE_SPEC>`"]
+pub type DELAY2BYTE = crate::Reg<delay2byte::DELAY2BYTE_SPEC>;
+#[doc = "Delay2 Register by Byte"]
+pub mod delay2byte;
+#[doc = "IRQ_SEN register accessor: an alias for `Reg<IRQ_SEN_SPEC>`"]
+pub type IRQ_SEN = crate::Reg<irq_sen::IRQ_SEN_SPEC>;
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
+pub mod irq_sen;
+#[doc = "IRQ_EDGE register accessor: an alias for `Reg<IRQ_EDGE_SPEC>`"]
+pub type IRQ_EDGE = crate::Reg<irq_edge::IRQ_EDGE_SPEC>;
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
+pub mod irq_edge;
+#[doc = "IRQ_EVT register accessor: an alias for `Reg<IRQ_EVT_SPEC>`"]
+pub type IRQ_EVT = crate::Reg<irq_evt::IRQ_EVT_SPEC>;
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
+pub mod irq_evt;
+#[doc = "IRQ_ENB register accessor: an alias for `Reg<IRQ_ENB_SPEC>`"]
+pub type IRQ_ENB = crate::Reg<irq_enb::IRQ_ENB_SPEC>;
+#[doc = "Interrupt Enable Register"]
+pub mod irq_enb;
+#[doc = "IRQ_RAW register accessor: an alias for `Reg<IRQ_RAW_SPEC>`"]
+pub type IRQ_RAW = crate::Reg<irq_raw::IRQ_RAW_SPEC>;
+#[doc = "Raw Interrupt Status"]
+pub mod irq_raw;
+#[doc = "IRQ_END register accessor: an alias for `Reg<IRQ_END_SPEC>`"]
+pub type IRQ_END = crate::Reg<irq_end::IRQ_END_SPEC>;
+#[doc = "Masked Interrupt Status"]
+pub mod irq_end;
+#[doc = "EDGE_STATUS register accessor: an alias for `Reg<EDGE_STATUS_SPEC>`"]
+pub type EDGE_STATUS = crate::Reg<edge_status::EDGE_STATUS_SPEC>;
+#[doc = "Edge Status Register"]
+pub mod edge_status;
+#[doc = "PERID register accessor: an alias for `Reg<PERID_SPEC>`"]
+pub type PERID = crate::Reg<perid::PERID_SPEC>;
+#[doc = "Peripheral ID Register"]
+pub mod perid;

src/porta/clrout.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `CLROUT` writer"]
+pub struct W(crate::W<CLROUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLROUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLROUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLROUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clear Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clrout](index.html) module"]
+pub struct CLROUT_SPEC;
+impl crate::RegisterSpec for CLROUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [clrout::W](W) writer structure"]
+impl crate::Writable for CLROUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLROUT to value 0"]
+impl crate::Resettable for CLROUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/clroutbyte.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CLROUTBYTE[%s]` writer"]
+pub struct W(crate::W<CLROUTBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CLROUTBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CLROUTBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CLROUTBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clear Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clroutbyte](index.html) module"]
+pub struct CLROUTBYTE_SPEC;
+impl crate::RegisterSpec for CLROUTBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [clroutbyte::W](W) writer structure"]
+impl crate::Writable for CLROUTBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CLROUTBYTE[%s]
+to value 0"]
+impl crate::Resettable for CLROUTBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datain.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `DATAIN` reader"]
+pub struct R(crate::R<DATAIN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAIN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAIN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAIN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Data In Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datain](index.html) module"]
+pub struct DATAIN_SPEC;
+impl crate::RegisterSpec for DATAIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [datain::R](R) reader structure"]
+impl crate::Readable for DATAIN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DATAIN to value 0"]
+impl crate::Resettable for DATAIN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datainbyte.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DATAINBYTE[%s]` reader"]
+pub struct R(crate::R<DATAINBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAINBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAINBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAINBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Data In Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainbyte](index.html) module"]
+pub struct DATAINBYTE_SPEC;
+impl crate::RegisterSpec for DATAINBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [datainbyte::R](R) reader structure"]
+impl crate::Readable for DATAINBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DATAINBYTE[%s]
+to value 0"]
+impl crate::Resettable for DATAINBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datainraw.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `DATAINRAW` reader"]
+pub struct R(crate::R<DATAINRAW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAINRAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAINRAW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAINRAW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Data In Raw Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainraw](index.html) module"]
+pub struct DATAINRAW_SPEC;
+impl crate::RegisterSpec for DATAINRAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [datainraw::R](R) reader structure"]
+impl crate::Readable for DATAINRAW_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DATAINRAW to value 0"]
+impl crate::Resettable for DATAINRAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datainrawbyte.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DATAINRAWBYTE[%s]` reader"]
+pub struct R(crate::R<DATAINRAWBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAINRAWBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAINRAWBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAINRAWBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Data In Raw Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainrawbyte](index.html) module"]
+pub struct DATAINRAWBYTE_SPEC;
+impl crate::RegisterSpec for DATAINRAWBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [datainrawbyte::R](R) reader structure"]
+impl crate::Readable for DATAINRAWBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DATAINRAWBYTE[%s]
+to value 0"]
+impl crate::Resettable for DATAINRAWBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datamask.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `DATAMASK` reader"]
+pub struct R(crate::R<DATAMASK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAMASK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAMASK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAMASK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DATAMASK` writer"]
+pub struct W(crate::W<DATAMASK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAMASK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAMASK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAMASK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datamask](index.html) module"]
+pub struct DATAMASK_SPEC;
+impl crate::RegisterSpec for DATAMASK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [datamask::R](R) reader structure"]
+impl crate::Readable for DATAMASK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [datamask::W](W) writer structure"]
+impl crate::Writable for DATAMASK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAMASK to value 0"]
+impl crate::Resettable for DATAMASK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/datamaskbyte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `DATAMASKBYTE[%s]` reader"]
+pub struct R(crate::R<DATAMASKBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATAMASKBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATAMASKBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATAMASKBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DATAMASKBYTE[%s]` writer"]
+pub struct W(crate::W<DATAMASKBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAMASKBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAMASKBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAMASKBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Out Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datamaskbyte](index.html) module"]
+pub struct DATAMASKBYTE_SPEC;
+impl crate::RegisterSpec for DATAMASKBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [datamaskbyte::R](R) reader structure"]
+impl crate::Readable for DATAMASKBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [datamaskbyte::W](W) writer structure"]
+impl crate::Writable for DATAMASKBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAMASKBYTE[%s]
+to value 0"]
+impl crate::Resettable for DATAMASKBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dataout.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATAOUT` writer"]
+pub struct W(crate::W<DATAOUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAOUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAOUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAOUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataout](index.html) module"]
+pub struct DATAOUT_SPEC;
+impl crate::RegisterSpec for DATAOUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [dataout::W](W) writer structure"]
+impl crate::Writable for DATAOUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAOUT to value 0"]
+impl crate::Resettable for DATAOUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dataoutbyte.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `DATAOUTBYTE[%s]` writer"]
+pub struct W(crate::W<DATAOUTBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAOUTBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAOUTBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAOUTBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutbyte](index.html) module"]
+pub struct DATAOUTBYTE_SPEC;
+impl crate::RegisterSpec for DATAOUTBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [dataoutbyte::W](W) writer structure"]
+impl crate::Writable for DATAOUTBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAOUTBYTE[%s]
+to value 0"]
+impl crate::Resettable for DATAOUTBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dataoutraw.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATAOUTRAW` writer"]
+pub struct W(crate::W<DATAOUTRAW_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAOUTRAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAOUTRAW_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAOUTRAW_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutraw](index.html) module"]
+pub struct DATAOUTRAW_SPEC;
+impl crate::RegisterSpec for DATAOUTRAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [dataoutraw::W](W) writer structure"]
+impl crate::Writable for DATAOUTRAW_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAOUTRAW to value 0"]
+impl crate::Resettable for DATAOUTRAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dataoutrawbyte.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `DATAOUTRAWBYTE[%s]` writer"]
+pub struct W(crate::W<DATAOUTRAWBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DATAOUTRAWBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DATAOUTRAWBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DATAOUTRAWBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutrawbyte](index.html) module"]
+pub struct DATAOUTRAWBYTE_SPEC;
+impl crate::RegisterSpec for DATAOUTRAWBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [dataoutrawbyte::W](W) writer structure"]
+impl crate::Writable for DATAOUTRAWBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DATAOUTRAWBYTE[%s]
+to value 0"]
+impl crate::Resettable for DATAOUTRAWBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/delay1.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `DELAY1` reader"]
+pub struct R(crate::R<DELAY1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DELAY1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DELAY1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DELAY1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DELAY1` writer"]
+pub struct W(crate::W<DELAY1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DELAY1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DELAY1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DELAY1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Delay1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay1](index.html) module"]
+pub struct DELAY1_SPEC;
+impl crate::RegisterSpec for DELAY1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [delay1::R](R) reader structure"]
+impl crate::Readable for DELAY1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [delay1::W](W) writer structure"]
+impl crate::Writable for DELAY1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DELAY1 to value 0"]
+impl crate::Resettable for DELAY1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/delay1byte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `DELAY1BYTE[%s]` reader"]
+pub struct R(crate::R<DELAY1BYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DELAY1BYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DELAY1BYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DELAY1BYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DELAY1BYTE[%s]` writer"]
+pub struct W(crate::W<DELAY1BYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DELAY1BYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DELAY1BYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DELAY1BYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Delay1 Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay1byte](index.html) module"]
+pub struct DELAY1BYTE_SPEC;
+impl crate::RegisterSpec for DELAY1BYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [delay1byte::R](R) reader structure"]
+impl crate::Readable for DELAY1BYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [delay1byte::W](W) writer structure"]
+impl crate::Writable for DELAY1BYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DELAY1BYTE[%s]
+to value 0"]
+impl crate::Resettable for DELAY1BYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/delay2.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `DELAY2` reader"]
+pub struct R(crate::R<DELAY2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DELAY2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DELAY2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DELAY2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DELAY2` writer"]
+pub struct W(crate::W<DELAY2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DELAY2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DELAY2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DELAY2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Delay2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay2](index.html) module"]
+pub struct DELAY2_SPEC;
+impl crate::RegisterSpec for DELAY2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [delay2::R](R) reader structure"]
+impl crate::Readable for DELAY2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [delay2::W](W) writer structure"]
+impl crate::Writable for DELAY2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DELAY2 to value 0"]
+impl crate::Resettable for DELAY2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/delay2byte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `DELAY2BYTE[%s]` reader"]
+pub struct R(crate::R<DELAY2BYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DELAY2BYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DELAY2BYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DELAY2BYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DELAY2BYTE[%s]` writer"]
+pub struct W(crate::W<DELAY2BYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DELAY2BYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DELAY2BYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DELAY2BYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Delay2 Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay2byte](index.html) module"]
+pub struct DELAY2BYTE_SPEC;
+impl crate::RegisterSpec for DELAY2BYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [delay2byte::R](R) reader structure"]
+impl crate::Readable for DELAY2BYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [delay2byte::W](W) writer structure"]
+impl crate::Writable for DELAY2BYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DELAY2BYTE[%s]
+to value 0"]
+impl crate::Resettable for DELAY2BYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dir.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `DIR` reader"]
+pub struct R(crate::R<DIR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DIR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DIR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DIR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DIR` writer"]
+pub struct W(crate::W<DIR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DIR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DIR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DIR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Direction Register (1:Output, 0:Input)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"]
+pub struct DIR_SPEC;
+impl crate::RegisterSpec for DIR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dir::R](R) reader structure"]
+impl crate::Readable for DIR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"]
+impl crate::Writable for DIR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DIR to value 0"]
+impl crate::Resettable for DIR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/dirbyte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `DIRBYTE[%s]` reader"]
+pub struct R(crate::R<DIRBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DIRBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DIRBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DIRBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DIRBYTE[%s]` writer"]
+pub struct W(crate::W<DIRBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DIRBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DIRBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DIRBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Direction Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirbyte](index.html) module"]
+pub struct DIRBYTE_SPEC;
+impl crate::RegisterSpec for DIRBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [dirbyte::R](R) reader structure"]
+impl crate::Readable for DIRBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dirbyte::W](W) writer structure"]
+impl crate::Writable for DIRBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DIRBYTE[%s]
+to value 0"]
+impl crate::Resettable for DIRBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/edge_status.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EDGE_STATUS` reader"]
+pub struct R(crate::R<EDGE_STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EDGE_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EDGE_STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EDGE_STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EDGE_STATUS` writer"]
+pub struct W(crate::W<EDGE_STATUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EDGE_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EDGE_STATUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EDGE_STATUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Edge Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edge_status](index.html) module"]
+pub struct EDGE_STATUS_SPEC;
+impl crate::RegisterSpec for EDGE_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [edge_status::R](R) reader structure"]
+impl crate::Readable for EDGE_STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [edge_status::W](W) writer structure"]
+impl crate::Writable for EDGE_STATUS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EDGE_STATUS to value 0"]
+impl crate::Resettable for EDGE_STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_edge.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_EDGE` reader"]
+pub struct R(crate::R<IRQ_EDGE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_EDGE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_EDGE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_EDGE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_EDGE` writer"]
+pub struct W(crate::W<IRQ_EDGE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_EDGE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_EDGE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_EDGE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_edge](index.html) module"]
+pub struct IRQ_EDGE_SPEC;
+impl crate::RegisterSpec for IRQ_EDGE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_edge::R](R) reader structure"]
+impl crate::Readable for IRQ_EDGE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_edge::W](W) writer structure"]
+impl crate::Writable for IRQ_EDGE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_EDGE to value 0"]
+impl crate::Resettable for IRQ_EDGE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_enb.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub struct R(crate::R<IRQ_ENB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_ENB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_ENB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_ENB` writer"]
+pub struct W(crate::W<IRQ_ENB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_ENB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_ENB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_ENB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"]
+pub struct IRQ_ENB_SPEC;
+impl crate::RegisterSpec for IRQ_ENB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_enb::R](R) reader structure"]
+impl crate::Readable for IRQ_ENB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"]
+impl crate::Writable for IRQ_ENB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IRQ_ENB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_end.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `IRQ_END` reader"]
+pub struct R(crate::R<IRQ_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Masked Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"]
+pub struct IRQ_END_SPEC;
+impl crate::RegisterSpec for IRQ_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_end::R](R) reader structure"]
+impl crate::Readable for IRQ_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IRQ_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_evt.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_EVT` reader"]
+pub struct R(crate::R<IRQ_EVT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_EVT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_EVT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_EVT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_EVT` writer"]
+pub struct W(crate::W<IRQ_EVT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_EVT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_EVT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_EVT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_evt](index.html) module"]
+pub struct IRQ_EVT_SPEC;
+impl crate::RegisterSpec for IRQ_EVT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_evt::R](R) reader structure"]
+impl crate::Readable for IRQ_EVT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_evt::W](W) writer structure"]
+impl crate::Writable for IRQ_EVT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_EVT to value 0"]
+impl crate::Resettable for IRQ_EVT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_raw.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub struct R(crate::R<IRQ_RAW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_RAW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_RAW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_RAW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"]
+pub struct IRQ_RAW_SPEC;
+impl crate::RegisterSpec for IRQ_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_raw::R](R) reader structure"]
+impl crate::Readable for IRQ_RAW_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IRQ_RAW to value 0"]
+impl crate::Resettable for IRQ_RAW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/irq_sen.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_SEN` reader"]
+pub struct R(crate::R<IRQ_SEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRQ_SEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRQ_SEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRQ_SEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRQ_SEN` writer"]
+pub struct W(crate::W<IRQ_SEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRQ_SEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRQ_SEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRQ_SEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_sen](index.html) module"]
+pub struct IRQ_SEN_SPEC;
+impl crate::RegisterSpec for IRQ_SEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irq_sen::R](R) reader structure"]
+impl crate::Readable for IRQ_SEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irq_sen::W](W) writer structure"]
+impl crate::Writable for IRQ_SEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRQ_SEN to value 0"]
+impl crate::Resettable for IRQ_SEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/perid.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `PERID` reader"]
+pub struct R(crate::R<PERID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
+pub struct PERID_SPEC;
+impl crate::RegisterSpec for PERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perid::R](R) reader structure"]
+impl crate::Readable for PERID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PERID to value 0x0010_07e1"]
+impl crate::Resettable for PERID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0010_07e1
+    }
+}

src/porta/pulse.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `PULSE` reader"]
+pub struct R(crate::R<PULSE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PULSE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PULSE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PULSE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PULSE` writer"]
+pub struct W(crate::W<PULSE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PULSE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PULSE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PULSE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pulse Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulse](index.html) module"]
+pub struct PULSE_SPEC;
+impl crate::RegisterSpec for PULSE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [pulse::R](R) reader structure"]
+impl crate::Readable for PULSE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pulse::W](W) writer structure"]
+impl crate::Writable for PULSE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PULSE to value 0"]
+impl crate::Resettable for PULSE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/pulsebase.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `PULSEBASE` reader"]
+pub struct R(crate::R<PULSEBASE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PULSEBASE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PULSEBASE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PULSEBASE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PULSEBASE` writer"]
+pub struct W(crate::W<PULSEBASE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PULSEBASE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PULSEBASE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PULSEBASE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pulse Base Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebase](index.html) module"]
+pub struct PULSEBASE_SPEC;
+impl crate::RegisterSpec for PULSEBASE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [pulsebase::R](R) reader structure"]
+impl crate::Readable for PULSEBASE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pulsebase::W](W) writer structure"]
+impl crate::Writable for PULSEBASE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PULSEBASE to value 0"]
+impl crate::Resettable for PULSEBASE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/pulsebasebyte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `PULSEBASEBYTE[%s]` reader"]
+pub struct R(crate::R<PULSEBASEBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PULSEBASEBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PULSEBASEBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PULSEBASEBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PULSEBASEBYTE[%s]` writer"]
+pub struct W(crate::W<PULSEBASEBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PULSEBASEBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PULSEBASEBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PULSEBASEBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pulse Base Mode Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebasebyte](index.html) module"]
+pub struct PULSEBASEBYTE_SPEC;
+impl crate::RegisterSpec for PULSEBASEBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [pulsebasebyte::R](R) reader structure"]
+impl crate::Readable for PULSEBASEBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pulsebasebyte::W](W) writer structure"]
+impl crate::Writable for PULSEBASEBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PULSEBASEBYTE[%s]
+to value 0"]
+impl crate::Resettable for PULSEBASEBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/porta/pulsebyte.rs

@@ -0,0 +1,65 @@
+#[doc = "Register `PULSEBYTE[%s]` reader"]
+pub struct R(crate::R<PULSEBYTE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PULSEBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PULSEBYTE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PULSEBYTE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PULSEBYTE[%s]` writer"]
+pub struct W(crate::W<PULSEBYTE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PULSEBYTE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PULSEBYTE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PULSEBYTE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pulse Mode Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebyte](index.html) module"]
+pub struct PULSEBYTE_SPEC;
+impl crate::RegisterSpec for PULSEBYTE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [pulsebyte::R](R) reader structure"]
+impl crate::Readable for PULSEBYTE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pulsebyte::W](W) writer structure"]
+impl crate::Writable for PULSEBYTE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PULSEBYTE[%s]
+to value 0"]
+impl crate::Resettable for PULSEBYTE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}