cross-compile now in CI

9: Added PAC update for new fields r=robamu a=robamu

- Adds the PAC changes for the updated SVD file. Peripheral clock enable register now has named fields

Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>

.github/workflows/ci.yml

@@ -12,10 +12,13 @@ jobs:
         with:
           profile: minimal
           toolchain: stable
+          target: thumbv6m-none-eabi
           override: true
       - uses: actions-rs/cargo@v1
         with:
+          use-cross: true
           command: check
+          args: --target thumbv6m-none-eabi
 
   fmt:
     name: Rustfmt
@@ -42,12 +45,14 @@ jobs:
         with:
           profile: minimal
           toolchain: stable
+          target: thumbv6m-none-eabi
           override: true
       - run: rustup component add clippy
       - uses: actions-rs/cargo@v1
         with:
+          use-cross: true
           command: clippy
-          args: -- -D warnings
+          args: --target thumbv6m-none-eabi -- -D warnings
 
   ci:
       if: ${{ success() }}

.gitignore

@@ -0,0 +1,6 @@
+# Generated by Cargo
+# will have compiled files and executables
+/target/
+
+# These are backup files generated by rustfmt
+**/*.rs.bk

CHANGELOG.md

@@ -6,11 +6,25 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
-## [Unreleased]
+## [unreleased]
+
+## [v0.2.0]
+
+- Relicensed under dual Apache-2.0 / MIT license
+
+### Changed
+
+- SVD file handling improved and new fields added for the peripheral
+  clock enable register
+
+### Added
+
+- Helper script to automate all steps for PAC generation
+- Added badges for README
 
 ## [v0.1.0]
 
 ### Added
 
 - First version of the PAC which builds. Uses a patched version
-  of `svd2rust`: https://github.com/rust-embedded/svd2rust
+  of `svd2rust`: https://github.com/rust-embedded/svd2rust

Cargo.toml

@@ -1,13 +1,14 @@
 [package]
 name = "va108xx"
 version = "0.1.0"
+authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
 edition = "2018"
-description = "Peripheral access API for Vorago VA108XX microcontrollers"
-license = "0BSD"
+description = "PAC for the Vorago VA108xx family of microcontrollers"
 homepage = "https://github.com/robamu-org/va108xx-rs"
 repository = "https://github.com/robamu-org/va108xx-rs"
+license = "MIT OR Apache-2.0"
 keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
-authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
+categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-m = "0.7.3"

LICENSE-0BSD

@@ -1,10 +0,0 @@
-Permission to use, copy, modify, and/or distribute this software for
-any purpose with or without fee is hereby granted.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
-AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSE-APACHE

@@ -0,0 +1,201 @@
+                              Apache License
+                        Version 2.0, January 2004
+                     http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
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+
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+5. Submission of Contributions. Unless You explicitly state otherwise,
+   any Contribution intentionally submitted for inclusion in the Work
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+   Notwithstanding the above, nothing herein shall supersede or modify
+   the terms of any separate license agreement you may have executed
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+
+6. Trademarks. This License does not grant permission to use the trade
+   names, trademarks, service marks, or product names of the Licensor,
+   except as required for reasonable and customary use in describing the
+   origin of the Work and reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or
+   agreed to in writing, Licensor provides the Work (and each
+   Contributor provides its Contributions) on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+   implied, including, without limitation, any warranties or conditions
+   of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+   PARTICULAR PURPOSE. You are solely responsible for determining the
+   appropriateness of using or redistributing the Work and assume any
+   risks associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory,
+   whether in tort (including negligence), contract, or otherwise,
+   unless required by applicable law (such as deliberate and grossly
+   negligent acts) or agreed to in writing, shall any Contributor be
+   liable to You for damages, including any direct, indirect, special,
+   incidental, or consequential damages of any character arising as a
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+
+9. Accepting Warranty or Additional Liability. While redistributing
+   the Work or Derivative Works thereof, You may choose to offer,
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+   on Your own behalf and on Your sole responsibility, not on behalf
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+   defend, and hold each Contributor harmless for any liability
+   incurred by, or claims asserted against, such Contributor by reason
+   of your accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
+
+APPENDIX: How to apply the Apache License to your work.
+
+   To apply the Apache License to your work, attach the following
+   boilerplate notice, with the fields enclosed by brackets "[]"
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+   comment syntax for the file format. We also recommend that a
+   file or class name and description of purpose be included on the
+   same "printed page" as the copyright notice for easier
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+
+Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.

LICENSE-MIT

@@ -0,0 +1,25 @@
+Copyright (c) 2021 Robin Mueller
+
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

README.md

@@ -1,6 +1,38 @@
+[![Crates.io](https://img.shields.io/crates/v/va108xx)](https://crates.io/crates/va108xx)
+[![build](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml)
+[![docs.rs](https://img.shields.io/docsrs/va108xx)](https://docs.rs/va108xx)
+
 # PAC for the Vorago VA108xx microcontroller family
 
 This repository contains the Peripheral Access Crate (PAC) for
 Voragos VA108xx series of Cortex-M0 based microcontrollers.
 
 The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
+
+## Usage
+
+To use this crate, add this to your `Cargo.toml`
+
+```toml
+[dependencies.va108xx]
+version = "0.1.0"
+features = ["rt"]
+```
+
+The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
+
+For full details on the autgenerated API, please see the
+[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api).
+
+## Regenerating the PAC
+
+The base file used by `svd2rust` is generated using the `svdtools` package and a
+YAML patch file. You can create the patched file by running this command after installing
+the Python [`svdtools` package](https://github.com/stm32-rs/svdtools):
+
+```sh
+cd svd
+svd patch va108xx-patch.yml
+```
+
+After that, you can regenerate the PAC by running the `gen-helper.sh` helper script.

gen-helper.sh

@@ -0,0 +1,21 @@
+#!/bin/sh
+
+# Use installed tool by default
+svd2rust_bin="svd2rust"
+# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/
+if [ -f svd2rust ]; then
+	# If the local directory contains svd2rust, use that version instead
+	svd2rust_bin="./svd2rust"
+elif [ -f ../svd2rust ]; then
+	# Keeps the repository clean
+	svd2rust_bin="../svd2rust"
+fi
+if [ -x "$(${svd2rust_bin} --version)" ]; then
+	echo "No svd2rust found locally or installed." \
+		"Install it with cargo install svd2rust"
+	exit
+fi
+${svd2rust_bin} -i svd/va108xx-base.svd.patched
+rm -rf src
+form -i lib.rs -o src/ && rm lib.rs
+cargo fmt

src/lib.rs

@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (af91938 2021-11-01))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (58c0bb6 2021-11-02))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![deny(const_err)]
 #![deny(dead_code)]

src/sysconfig/peripheral_clk_enable.rs

@@ -34,7 +34,648 @@ impl From<crate::W<PERIPHERAL_CLK_ENABLE_SPEC>> for W {
         W(writer)
     }
 }
+#[doc = "Field `PORTA` reader - Enable PORTA clock"]
+pub struct PORTA_R(crate::FieldReader<bool, bool>);
+impl PORTA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTA` writer - Enable PORTA clock"]
+pub struct PORTA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = value as u32;
+        self.w
+    }
+}
+#[doc = "Field `PORTB` reader - Enable PORTB clock"]
+pub struct PORTB_R(crate::FieldReader<bool, bool>);
+impl PORTB_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTB_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTB_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTB` writer - Enable PORTB clock"]
+pub struct PORTB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTB_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\]
+clock"]
+pub struct SPI_0_R(crate::FieldReader<bool, bool>);
+impl SPI_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\]
+clock"]
+pub struct SPI_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\]
+clock"]
+pub struct SPI_1_R(crate::FieldReader<bool, bool>);
+impl SPI_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\]
+clock"]
+pub struct SPI_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\]
+clock"]
+pub struct SPI_2_R(crate::FieldReader<bool, bool>);
+impl SPI_2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\]
+clock"]
+pub struct SPI_2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `UART_0` reader - Enable UART\\[0\\]
+clock"]
+pub struct UART_0_R(crate::FieldReader<bool, bool>);
+impl UART_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_0` writer - Enable UART\\[0\\]
+clock"]
+pub struct UART_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `UART_1` reader - Enable UART\\[1\\]
+clock"]
+pub struct UART_1_R(crate::FieldReader<bool, bool>);
+impl UART_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_1` writer - Enable UART\\[1\\]
+clock"]
+pub struct UART_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\]
+clock"]
+pub struct I2C_0_R(crate::FieldReader<bool, bool>);
+impl I2C_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\]
+clock"]
+pub struct I2C_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\]
+clock"]
+pub struct I2C_1_R(crate::FieldReader<bool, bool>);
+impl I2C_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\]
+clock"]
+pub struct I2C_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"]
+pub struct IRQSEL_R(crate::FieldReader<bool, bool>);
+impl IRQSEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IRQSEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IRQSEL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IRQSEL` writer - Enable IRQ selector clock"]
+pub struct IRQSEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IRQSEL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
+        self.w
+    }
+}
+#[doc = "Field `IOCONFIG` reader - Enable IO Configuration block clock"]
+pub struct IOCONFIG_R(crate::FieldReader<bool, bool>);
+impl IOCONFIG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IOCONFIG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IOCONFIG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IOCONFIG` writer - Enable IO Configuration block clock"]
+pub struct IOCONFIG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IOCONFIG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
+        self.w
+    }
+}
+#[doc = "Field `UTILITY` reader - Enable utility clock"]
+pub struct UTILITY_R(crate::FieldReader<bool, bool>);
+impl UTILITY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UTILITY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UTILITY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UTILITY` writer - Enable utility clock"]
+pub struct UTILITY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UTILITY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
+        self.w
+    }
+}
+#[doc = "Field `GPIO` reader - Enable GPIO clock"]
+pub struct GPIO_R(crate::FieldReader<bool, bool>);
+impl GPIO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        GPIO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for GPIO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `GPIO` writer - Enable GPIO clock"]
+pub struct GPIO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> GPIO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    pub fn porta(&self) -> PORTA_R {
+        PORTA_R::new(self.bits != 0)
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    pub fn portb(&self) -> PORTB_R {
+        PORTB_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_0(&self) -> SPI_0_R {
+        SPI_0_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_1(&self) -> SPI_1_R {
+        SPI_1_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_2(&self) -> SPI_2_R {
+        SPI_2_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_0(&self) -> UART_0_R {
+        UART_0_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_1(&self) -> UART_1_R {
+        UART_1_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_0(&self) -> I2C_0_R {
+        I2C_0_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_1(&self) -> I2C_1_R {
+        I2C_1_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    pub fn irqsel(&self) -> IRQSEL_R {
+        IRQSEL_R::new(((self.bits >> 21) & 0x01) != 0)
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IOCONFIG_R {
+        IOCONFIG_R::new(((self.bits >> 22) & 0x01) != 0)
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    pub fn utility(&self) -> UTILITY_R {
+        UTILITY_R::new(((self.bits >> 23) & 0x01) != 0)
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    pub fn gpio(&self) -> GPIO_R {
+        GPIO_R::new(((self.bits >> 24) & 0x01) != 0)
+    }
+}
 impl W {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    pub fn porta(&mut self) -> PORTA_W {
+        PORTA_W { w: self }
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    pub fn portb(&mut self) -> PORTB_W {
+        PORTB_W { w: self }
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_0(&mut self) -> SPI_0_W {
+        SPI_0_W { w: self }
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_1(&mut self) -> SPI_1_W {
+        SPI_1_W { w: self }
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_2(&mut self) -> SPI_2_W {
+        SPI_2_W { w: self }
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_0(&mut self) -> UART_0_W {
+        UART_0_W { w: self }
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_1(&mut self) -> UART_1_W {
+        UART_1_W { w: self }
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_0(&mut self) -> I2C_0_W {
+        I2C_0_W { w: self }
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_1(&mut self) -> I2C_1_W {
+        I2C_1_W { w: self }
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    pub fn irqsel(&mut self) -> IRQSEL_W {
+        IRQSEL_W { w: self }
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    pub fn ioconfig(&mut self) -> IOCONFIG_W {
+        IOCONFIG_W { w: self }
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    pub fn utility(&mut self) -> UTILITY_W {
+        UTILITY_W { w: self }
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    pub fn gpio(&mut self) -> GPIO_W {
+        GPIO_W { w: self }
+    }
     #[doc = "Writes raw bits to the register."]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {

svd/va108xx-patch.yml

@@ -0,0 +1,59 @@
+_svd: va108xx-base.svd
+
+SYSCONFIG:
+  PERIPHERAL_CLK_ENABLE:
+    _add:
+        PORTA:
+          description: Enable PORTA clock
+          bitOffset: 0
+          bitWidth: 1
+        PORTB:
+          description: Enable PORTB clock
+          bitOffset: 1
+          bitWidth: 1
+        SPI_0:
+          description: Enable SPI[0] clock
+          bitOffset: 4
+          bitWidth: 1
+        SPI_1:
+          description: Enable SPI[1] clock
+          bitOffset: 5
+          bitWidth: 1
+        SPI_2:
+          description: Enable SPI[2] clock
+          bitOffset: 6
+          bitWidth: 1
+        UART_0:
+          description: Enable UART[0] clock
+          bitOffset: 8
+          bitWidth: 1
+        UART_1:
+          description: Enable UART[1] clock
+          bitOffset: 9
+          bitWidth: 1
+        I2C_0:
+          description: Enable I2C[0] clock
+          bitOffset: 16
+          bitWidth: 1
+        I2C_1:
+          description: Enable I2C[1] clock
+          bitOffset: 17
+          bitWidth: 1
+        IRQSEL:
+          description: Enable IRQ selector clock
+          bitOffset: 21
+          bitWidth: 1
+        IOCONFIG:
+          description: Enable IO Configuration block clock
+          bitOffset: 22
+          bitWidth: 1
+        UTILITY:
+          description: Enable utility clock
+          bitOffset: 23
+          bitWidth: 1
+        GPIO:
+          description: Enable GPIO clock
+          bitOffset: 24
+          bitWidth: 1
+
+