added missing cascade field #5
@ -404,6 +404,43 @@ impl<'a> CSDXXX2_W<'a> {
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self.w
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}
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}
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#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
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pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
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impl CSDTRG2_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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CSDTRG2_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for CSDTRG2_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
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pub struct CSDTRG2_W<'a> {
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w: &'a mut W,
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}
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impl<'a> CSDTRG2_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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#[inline(always)]
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@ -455,6 +492,11 @@ impl R {
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pub fn csdxxx2(&self) -> CSDXXX2_R {
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CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
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}
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#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg2(&self) -> CSDTRG2_R {
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CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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@ -507,6 +549,11 @@ impl W {
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pub fn csdxxx2(&mut self) -> CSDXXX2_W {
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CSDXXX2_W { w: self }
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}
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#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg2(&mut self) -> CSDTRG2_W {
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CSDTRG2_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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@ -1296,7 +1296,8 @@
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<description>Cascade 2 test mode</description>
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<bitRange>[11:11]</bitRange>
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</field>
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</fields>
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<field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
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</fields>
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</register>
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<register>
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<name>CASCADE0</name>
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@ -126,3 +126,12 @@ I2CA:
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description: Controller is Idle
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bitOffset: 1
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bitWidth: 1
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# All TIMs are derived from TIM0
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TIM0:
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CSD_CTRL:
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_add:
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CSDTRG2:
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description: Cascade 2 Enabled as Trigger
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bitOffset: 10
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bitWidth: 1
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