2026-04-29 - 2026-05-29

Overview

18 Active Pull Requests
0 Active Issues
Excluding merges, 1 author has pushed 1 commit to main and 23 commits to all branches. On main, 1 file has changed and there have been 4 additions and 20 deletions.

4 Releases published by 1 user

Published zynq7000-v0.4.0 zynq7000-v0.4.0 2026-05-15 19:32:05 +02:00

Published zynq7000-rt-v0.3.0 zynq7000-rt-v0.3.0 2026-05-08 17:21:00 +02:00

Published zynq7000-mmu-v0.2.0 zynq7000-mmu-v0.2.0 2026-05-08 17:19:29 +02:00

Published zynq7000-v0.3.0 zynq7000-v0.3.0 2026-05-08 17:09:50 +02:00

18 Pull requests merged by 1 user

Merged #85 continue SPI slave 2026-05-18 11:48:56 +02:00

Merged #84 prepare next zynq7000 version 2026-05-15 19:30:09 +02:00

Merged #83 UART improvements 2026-05-15 14:37:36 +02:00

Merged #82 zynq7000-rt and zynq7000-mmu release 2026-05-08 17:18:21 +02:00

Merged #81 prepare PAC release 2026-05-08 17:09:10 +02:00

Merged #80 add clock enable for SPI and UART 2026-05-08 17:00:50 +02:00

Merged #79 improve register names 2026-05-08 16:48:14 +02:00

Merged #78 introduce interrupt registry 2026-05-08 16:30:59 +02:00

Merged #77 Async OLED example 2026-05-08 14:43:50 +02:00

Merged #76 bump aarch32 deps 2026-05-08 12:55:37 +02:00

Merged #75 fix ping reply for net example 2026-05-08 12:50:43 +02:00

Merged #74 OLED example 2026-05-07 20:05:00 +02:00

Merged #70 update async SPI module 2026-05-07 18:02:28 +02:00

Merged #73 bugfix for SPI AMBA clock control 2026-05-05 18:41:00 +02:00

Merged #72 configure pull up properly 2026-05-05 15:46:32 +02:00

Merged #71 fix asynch uart TX 2026-05-04 19:32:26 +02:00

Merged #68 update asynch logger, simplify it 2026-05-04 18:01:30 +02:00

Merged #69 update BD and XDC 2026-05-04 16:57:47 +02:00