2025-05-25 - 2026-05-25

Overview

81 Active Pull Requests
0 Active Issues
Excluding merges, 3 authors have pushed 13 commits to main and 112 commits to all branches. On main, 38 files have changed and there have been 89 additions and 79 deletions.

18 Releases published by 1 user

Published zynq7000-v0.4.0 zynq7000-v0.4.0 2026-05-15 19:32:05 +02:00

Published zynq7000-rt-v0.3.0 zynq7000-rt-v0.3.0 2026-05-08 17:21:00 +02:00

Published zynq7000-mmu-v0.2.0 zynq7000-mmu-v0.2.0 2026-05-08 17:19:29 +02:00

Published zynq7000-v0.3.0 zynq7000-v0.3.0 2026-05-08 17:09:50 +02:00

Published zynq7000-v0.2.0 zynq7000-v0.2.0 2026-04-01 14:29:41 +02:00

Published zynq7000-embassy-v0.1.1 zynq7000-embassy-v0.1.1 2026-03-13 17:53:51 +01:00

Published zedboard-bsp-v0.1.0 zedboard-bsp-v0.1.0 2026-02-14 19:38:11 +01:00

Published zynq7000-embassy-v0.1.0 zynq7000-embassy-v0.1.0 2026-02-14 19:25:29 +01:00

Published zynq7000-rt-v0.2.0 zynq7000-rt-v0.2.0 2026-02-14 19:14:29 +01:00

Published zynq7000-mmu-v0.1.2 zynq7000-mmu-v0.1.2 2026-02-14 19:14:05 +01:00

Published zynq7000-hal-v0.1.1 zynq7000-hal-v0.1.1 2025-10-09 11:38:54 +02:00

Published zynq7000-rt-v0.1.1 zynq7000-rt-v0.1.1 2025-10-09 11:12:05 +02:00

Published zynq7000-mmu-v0.1.1 zynq7000-mmu-v0.1.1 2025-10-09 11:11:42 +02:00

Published zynq7000-hal-v0.1.0 zynq7000-hal-v0.1.0 2025-10-09 00:50:55 +02:00

Published zynq7000-mmu-v0.1.0 zynq7000-mmu-v0.1.0 2025-10-09 00:49:54 +02:00

Published zynq7000-rt-v0.1.0 zynq7000-rt-v0.1.0 2025-10-09 00:49:37 +02:00

Published zynq7000-v0.1.1 zynq7000-v0.1.1 2025-10-09 00:49:16 +02:00

Published zynq7000-v0.1.0 zynq7000-v0.1.0 2025-10-08 21:05:07 +02:00

81 Pull requests merged by 4 users

Merged #85 continue SPI slave 2026-05-18 11:48:56 +02:00

Merged #84 prepare next zynq7000 version 2026-05-15 19:30:09 +02:00

Merged #83 UART improvements 2026-05-15 14:37:36 +02:00

Merged #82 zynq7000-rt and zynq7000-mmu release 2026-05-08 17:18:21 +02:00

Merged #81 prepare PAC release 2026-05-08 17:09:10 +02:00

Merged #80 add clock enable for SPI and UART 2026-05-08 17:00:50 +02:00

Merged #79 improve register names 2026-05-08 16:48:14 +02:00

Merged #78 introduce interrupt registry 2026-05-08 16:30:59 +02:00

Merged #77 Async OLED example 2026-05-08 14:43:50 +02:00

Merged #76 bump aarch32 deps 2026-05-08 12:55:37 +02:00

Merged #75 fix ping reply for net example 2026-05-08 12:50:43 +02:00

Merged #74 OLED example 2026-05-07 20:05:00 +02:00

Merged #70 update async SPI module 2026-05-07 18:02:28 +02:00

Merged #73 bugfix for SPI AMBA clock control 2026-05-05 18:41:00 +02:00

Merged #72 configure pull up properly 2026-05-05 15:46:32 +02:00

Merged #71 fix asynch uart TX 2026-05-04 19:32:26 +02:00

Merged #68 update asynch logger, simplify it 2026-05-04 18:01:30 +02:00

Merged #69 update BD and XDC 2026-05-04 16:57:47 +02:00

Merged #67 Function to set FIFO Trigger of PS UART 2026-04-15 10:02:46 +02:00

Merged #66 use local path in README links 2026-04-01 14:25:31 +02:00

Merged #65 try this little readme tweak 2026-04-01 14:17:38 +02:00

Merged #64 prepare PAC v0.2.0 release 2026-04-01 14:14:56 +02:00

Merged #63 add defmt support for PAC 2026-04-01 14:01:42 +02:00

Merged #62 bugfix for DDR init 2026-04-01 11:01:18 +02:00

Merged #61 improve FSBL 2026-03-31 20:12:51 +02:00

Merged #60 Add PL reset de-assert in FSBL 2026-03-31 18:29:06 +02:00

Merged #59 smaller tweaks 2026-03-31 18:21:04 +02:00

Merged #21 Add SDIO support 2026-03-27 12:58:27 +01:00

Merged #58 readme tweak 2026-03-25 10:39:04 +01:00

Merged #57 bump dependencies and improve documentation 2026-03-25 10:37:37 +01:00

Merged #56 firmware/zynq7000-hal/Cargo.toml aktualisiert: Replace dependency 2026-03-25 10:26:23 +01:00

Merged #55 try-to-fix-embassy-docs 2026-03-13 17:52:17 +01:00

Merged #54 some CI fixes 2026-03-13 17:47:32 +01:00

Merged #53 some CI fixes 2026-03-13 17:35:12 +01:00

Merged #52 another tweak for the QSPI spansion driver 2026-03-10 19:46:25 +01:00

Merged #51 QSPI Spansion Remove Page Alignement Constraint 2026-03-10 13:28:43 +01:00

Merged #50 Fixed Bit Positions of QSPI Reset Register 2026-03-06 13:34:48 +01:00

Merged #49 fmt 2026-02-28 12:49:37 +01:00

Merged #48 minor-qspi-improvements-and-tweaks 2026-02-28 12:47:32 +01:00

Merged #45 use div-ceil for QSPI clock calc 2026-02-26 17:20:41 +01:00

Merged #47 chunked read 2026-02-26 17:19:40 +01:00

Merged #46 Add slow read for Spansion QSPI 2026-02-25 17:32:00 +01:00

Merged #44 prepare zedboard BSP release 2026-02-14 19:37:32 +01:00

Merged #43 prepare zynq7000-embassy release 2026-02-14 19:23:53 +01:00

Merged #42 prepare zynq-mmu v0.1.2 2026-02-14 19:11:00 +01:00

Merged #41 try allowing hw server ip 2026-02-14 17:49:09 +01:00

Merged #40 improve SPI implemenetation 2026-02-14 17:45:36 +01:00

Merged #39 division by zero check to avoid panic 2026-02-14 17:45:20 +01:00

Merged #38 bugfix for PL programming routine 2026-02-07 01:36:05 +01:00

Merged #37 bumped aarch32 dependencies 2026-02-02 15:40:03 +01:00

Merged #35 defmt tests 2026-01-20 22:06:01 +01:00

Merged #36 improve repository structure 2026-01-20 14:07:44 +01:00

Merged #34 update README 2026-01-16 15:27:05 +01:00

Merged #33 use stable in CI 2026-01-16 15:23:47 +01:00

Merged #32 start using stable toolchain 2026-01-12 11:57:06 +01:00

Merged #31 improve GIC modules 2025-12-06 14:39:00 +01:00

Merged #30 move to default aarch32-rt kmain method instead of boot_core 2025-12-02 23:33:04 +01:00

Merged #28 update to vivado 2025.2 2025-11-28 17:39:17 +01:00

Merged #27 docs and changelog 2025-11-28 16:00:58 +01:00

Merged #26 zynq7000-rt: small bugs in startup code 2025-11-28 14:52:04 +01:00

Merged #25 UART and docs update 2025-11-28 13:09:17 +01:00

Merged #24 docs and clippy 2025-11-27 20:29:55 +01:00

Merged #23 README updated after switch to aarch32 dependency 2025-11-24 22:12:04 +01:00

Merged #22 replaced cortex-ar and cortex-a-rt by aarch32-rt and aarch32-cpu 2025-11-02 19:37:58 +01:00

Merged #20 imrpoved ethernet mio typing check 2025-10-27 23:15:43 +01:00

Merged #19 rename register blocks 2025-10-27 23:12:43 +01:00

Merged #18 improve HAL docs 2025-10-09 11:38:02 +02:00

Merged #17 only compile arch specific code for cortex-a 2025-10-09 11:01:47 +02:00

Merged #16 smaller tweaks and docs API unification 2025-10-09 10:58:18 +02:00

Merged #15 add various changelogs 2025-10-09 00:43:22 +02:00

Merged #14 prepare first releases 2025-10-08 21:02:24 +02:00

Merged #13 prepare first releases 2025-10-08 20:56:00 +02:00

Merged #9 FSBL-rs 2025-10-08 20:24:06 +02:00

Merged #12 renamed MIO pin trait 2025-09-03 12:22:18 +02:00

Merged #11 after some further deliberation, readability is more important 2025-08-13 09:56:14 +02:00

Merged #10 consistency-and-renaming 2025-07-31 18:48:00 +02:00

Merged #8 minor docs improvements 2025-07-28 11:07:59 +02:00

Merged #7 l2 cache init now done in user app 2025-07-28 11:02:17 +02:00

Merged #4 Start adding ethernet support 2025-07-28 10:18:42 +02:00

Merged #6 small docs improvements 2025-06-26 20:32:21 +02:00

Merged #5 add basic CI 2025-06-26 20:27:15 +02:00