rust/zynq7000-rs
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use div-ceil for QSPI clock calc
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This commit is contained in:
Robin Müller
2026-02-19 13:20:48 +01:00
parent a58d398d82
commit 4590dfbc88
1 changed files with 1 additions and 1 deletions
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firmware/zynq7000-hal/src/qspi/mod.rs
+1 -1
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@@ -261,7 +261,7 @@ impl ClockConfig {
if qspi_ref_clk < clocks.arm_clocks().cpu_1x_clk() {
return Err(ClockCalculationError::RefClockSmallerThanCpu1xClock);
}
let qspi_baud_rate_div = qspi_ref_clk / target_qspi_interface_clock;
let qspi_baud_rate_div = qspi_ref_clk.raw().div_ceil(target_qspi_interface_clock.raw());
let baud_rate_div = match qspi_baud_rate_div {
0..=2 => BaudRateDivisor::_2,
3..=4 => BaudRateDivisor::_4,