start derive_mmio experiments

zynq7000-rt/Cargo.toml

@@ -11,8 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true, features = ["vfp-dp"] }
-cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" }
+cortex-a-rt = { path = "../../cortex-ar/cortex-a-rt", optional = true, features = ["vfp-dp"] }
+cortex-ar = { path = "../../cortex-ar/cortex-ar" }
 
 [features]
 default = ["rt"]

zynq7000-rt/regen-table.sh

@@ -0,0 +1,2 @@
+#!/bin/bash
+cargo +stable run --target $(rustc -vV | grep host | cut -d ' ' -f2) --bin table-gen --no-default-features --features tools

zynq7000-rt/src/bin/table-gen.rs

@@ -38,10 +38,10 @@ fn main() {
     let mut buf_writer = std::io::BufWriter::new(file);
     writeln!(
         buf_writer,
-        "//! This file is auto-generated by table-gen.rs. Do not edit it!"
+        "//! This file was auto-generated by table-gen.rs"
     )
     .unwrap();
-    writeln!(buf_writer, "use cortex_r_a::mmu::L1Section;").unwrap();
+    writeln!(buf_writer, "use cortex_ar::mmu::L1Section;").unwrap();
     writeln!(buf_writer, "use crate::mmu::{{section_attrs, L1Table}};").unwrap();
     writeln!(buf_writer, "").unwrap();
 
@@ -63,12 +63,12 @@ fn main() {
         "// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
     )
     .unwrap();
-    writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap();
+    writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
 
     offset += ONE_MB;
     writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
     for _ in 0..DDR_FULL_ACCESSIBLE {
-        writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap();
+        writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
         offset += ONE_MB;
     }
 
@@ -76,7 +76,7 @@ fn main() {
     for _ in 0..FPGA_SLAVE {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_fpga_slaves
         )
         .unwrap();
@@ -87,7 +87,7 @@ fn main() {
     for _ in 0..FPGA_SLAVE {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_fpga_slaves
         )
         .unwrap();
@@ -102,7 +102,7 @@ fn main() {
     for _ in 0..UNASSIGNED_0 {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_unassigned
         )
         .unwrap();
@@ -117,7 +117,7 @@ fn main() {
     for _ in 0..IO_PERIPHS {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_shared_dev
         )
         .unwrap();
@@ -132,7 +132,7 @@ fn main() {
     for _ in 0..UNASSIGNED_1 {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_unassigned
         )
         .unwrap();
@@ -143,7 +143,7 @@ fn main() {
     for _ in 0..NAND {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_shared_dev
         )
         .unwrap();
@@ -154,7 +154,7 @@ fn main() {
     for _ in 0..NOR {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_shared_dev
         )
         .unwrap();
@@ -175,7 +175,7 @@ fn main() {
     for _ in 0..SEGMENTS_UNASSIGNED_2 {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_unassigned
         )
         .unwrap();
@@ -190,7 +190,7 @@ fn main() {
     for _ in 0..AMBA_APB {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_shared_dev
         )
         .unwrap();
@@ -205,7 +205,7 @@ fn main() {
     for _ in 0..UNASSIGNED_3 {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_unassigned
         )
         .unwrap();
@@ -214,7 +214,7 @@ fn main() {
 
     writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
     for _ in 0..QSPI_XIP {
-        writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_qspi).unwrap();
+        writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_qspi).unwrap();
         offset += ONE_MB;
     }
 
@@ -226,7 +226,7 @@ fn main() {
     for _ in 0..UNASSIGNED_4 {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_unassigned
         )
         .unwrap();
@@ -238,7 +238,7 @@ fn main() {
     for _ in 0..OCM_MAPPED_HIGH {
         writeln!(
             buf_writer,
-            "L1Section::new({}, {}).0,",
+            "L1Section::new({}, {}).raw_value(),",
             offset, attr_ocm_high
         )
         .unwrap();

zynq7000-rt/src/mmu.rs

@@ -84,7 +84,7 @@ pub mod segments {
 }
 
 pub mod section_attrs {
-    use cortex_r_a::mmu::{
+    use cortex_ar::mmu::{
         AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
     };