continue, update MMU handling
This commit is contained in:
parent
d0d0d48780
commit
b8bb7e23c7
@ -7,6 +7,6 @@ members = [
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"zynq7000-embassy",
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"examples/simple",
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"examples/embassy",
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"examples/zedboard",
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"examples/zedboard", "zynq-mmu",
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]
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exclude = ["experiments"]
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19
memory.x
19
memory.x
@ -1,8 +1,23 @@
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MEMORY
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{
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/* Zedboard: 512 MB DDR3. Only use 256 MB for now, should be plenty for a bare-metal app. */
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CODE(rx) : ORIGIN = 0x00100000, LENGTH = 256M
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/* Zedboard: 512 MB DDR3. Only use 63 MB for now, should be plenty for a bare-metal app.
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Leave 1 MB of memory which will be configured as uncached device memory by the MPU. This is
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recommended for something like DMA descriptors. */
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CODE(rx) : ORIGIN = 0x00100000, LENGTH = 63MB
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UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1MB
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}
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REGION_ALIAS("DATA", CODE);
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SECTIONS
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{
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.uncached: ALIGN(4)
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{
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. = ALIGN(4);
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_start_uncached = .;
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*(.uncached .uncached.*);
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. = ALIGN(4);
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_end_uncached = .;
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} > UNCACHED;
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}
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7
zynq-mmu/Cargo.toml
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7
zynq-mmu/Cargo.toml
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@ -0,0 +1,7 @@
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[package]
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name = "zynq-mmu"
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description = "Zynq MMU structures"
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version = "0.1.0"
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edition = "2024"
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[dependencies]
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20
zynq-mmu/src/lib.rs
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20
zynq-mmu/src/lib.rs
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@ -0,0 +1,20 @@
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//! The MMU structures live inside a dedicated shared crate so it can be used by both the Zynq
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//! runtime crate and teh HAL crate.
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#![no_std]
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pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
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#[repr(C, align(16384))]
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pub struct L1Table(pub [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
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impl L1Table {
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#[inline(always)]
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pub const fn as_ptr(&self) -> *const u32 {
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self.0.as_ptr()
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}
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#[inline(always)]
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pub const fn as_mut_ptr(&mut self) -> *mut u32 {
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self.0.as_mut_ptr()
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}
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}
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@ -13,6 +13,7 @@ categories = ["embedded", "no-std", "hardware-support"]
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[dependencies]
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cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
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zynq7000 = { path = "../zynq7000" }
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zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
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bitbybit = "1.3"
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arbitrary-int = "1.3"
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@ -169,8 +169,11 @@ impl EthernetLowLevel {
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}
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#[inline]
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pub fn configure_mdc_clk_div() {
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// TODO:
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pub fn set_promiscous_mode(&mut self, enable: bool) {
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self.regs.modify_net_cfg(|mut val| {
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val.set_copy_all_frames(enable);
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val
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});
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}
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/// Performs initialization according to TRM p.541.
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@ -1,6 +1,9 @@
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use arbitrary_int::u3;
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use arbitrary_int::{u2, u3};
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pub use zynq7000::eth::MdcClkDiv;
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use zynq7000::eth::{MmioEthernet, SpeedMode, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR};
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use zynq7000::eth::{
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BurstLength, DmaRxBufSize, MmioEthernet, NetworkConfig, SpeedMode, GEM_0_BASE_ADDR,
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GEM_1_BASE_ADDR,
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};
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pub use ll::{ClkConfig, EthernetLowLevel};
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@ -9,6 +12,8 @@ pub mod mdio;
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pub mod rx_descr;
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pub mod tx_descr;
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const MTU: usize = 1536;
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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use crate::gpio::mio::{
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Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
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@ -198,6 +203,23 @@ impl RxData3 for Pin<Mio38> {
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const ETH_ID: EthernetId = EthernetId::Eth1;
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}
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#[derive(Debug, Clone, Copy)]
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pub struct EthernetConfig {
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pub clk_config: ClkConfig,
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pub mdc_clk_div: MdcClkDiv,
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pub mac_address: [u8; 6],
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}
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impl EthernetConfig {
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pub fn new(clk_config: ClkConfig, mdc_clk_div: MdcClkDiv, mac_address: [u8; 6]) -> Self {
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Self {
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clk_config,
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mdc_clk_div,
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mac_address,
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}
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}
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}
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pub struct Ethernet {
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ll: ll::EthernetLowLevel,
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mdio: mdio::Mdio,
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@ -222,8 +244,7 @@ impl Ethernet {
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MdIoPin: MdIo,
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>(
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mut ll: ll::EthernetLowLevel,
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clk_config: ll::ClkConfig,
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mdc_clk_div: MdcClkDiv,
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config: EthernetConfig,
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tx_clk: TxClkPin,
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tx_ctrl: TxCtrlPin,
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tx_data: (TxData0Pin, TxData1Pin, TxData2Pin, TxData3Pin),
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@ -232,7 +253,7 @@ impl Ethernet {
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rx_data: (RxData0Pin, RxData1Pin, RxData2Pin, RxData3Pin),
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md_pins: Option<(MdClkPin, MdIoPin)>,
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) -> Self {
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Self::common_init(&mut ll);
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Self::common_init(&mut ll, config.mac_address);
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let tx_mio_config = zynq7000::slcr::mio::Config::builder()
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.with_disable_hstl_rcvr(true)
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.with_pullup(true)
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@ -348,30 +369,53 @@ impl Ethernet {
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});
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});
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}
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ll.configure_clock(clk_config);
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ll.configure_clock(config.clk_config);
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let mut mdio = mdio::Mdio::new(&ll, true);
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mdio.configure_clock_div(mdc_clk_div);
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mdio.configure_clock_div(config.mdc_clk_div);
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Ethernet { ll, mdio }
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}
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pub fn new(mut ll: EthernetLowLevel, clk_config: ClkConfig, mdc_clk_div: MdcClkDiv) -> Self {
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Self::common_init(&mut ll);
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ll.configure_clock(clk_config);
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pub fn new(mut ll: EthernetLowLevel, config: EthernetConfig) -> Self {
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Self::common_init(&mut ll, config.mac_address);
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ll.configure_clock(config.clk_config);
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let mut mdio = mdio::Mdio::new(&ll, true);
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mdio.configure_clock_div(mdc_clk_div);
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mdio.configure_clock_div(config.mdc_clk_div);
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Ethernet { ll, mdio }
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}
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fn common_init(ll: &mut EthernetLowLevel) {
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fn common_init(ll: &mut EthernetLowLevel, mac_address: [u8; 6]) {
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ll.enable_peripheral_clock();
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ll.reset(3);
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ll.initialize();
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// By default, only modify critical network control bits to retain user configuration
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// like the MDC clock divisor.
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ll.regs.modify_net_cfg(|mut net_cfg| {
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net_cfg.set_full_duplex(true);
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net_cfg.set_gigabit_enable(true);
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net_cfg.set_speed_mode(SpeedMode::High100Mbps);
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net_cfg
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});
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let macaddr_msbs = (u32::from(mac_address[5]) << 8) | u32::from(mac_address[4]);
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let macaddr_lsbs = (u32::from(mac_address[3]) << 24)
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| (u32::from(mac_address[2]) << 16)
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| (u32::from(mac_address[1]) << 8)
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| u32::from(mac_address[0]);
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// Writing to the lower address portion disables the address match, writing to the higher
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// portion enables it again. Address matching is disabled on reset, so we do not need
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// to disable the other addresses here.
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ll.regs.write_addr1_low(macaddr_lsbs);
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ll.regs.write_addr1_high(macaddr_msbs);
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// TODO
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ll.regs.modify_dma_cfg(|mut val| {
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val.set_rx_packet_buf_size_sel(u2::new(0b11));
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val.set_tx_packet_buf_size_sel(true);
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val.set_burst_length(BurstLength::Incr16.reg_value());
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// Configure 1536 bytes receive buffer size. This is sufficient for regular Ethernet
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// frames.
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val.set_dma_rx_ahb_buf_size_sel(DmaRxBufSize::new((MTU >> 6) as u8).unwrap());
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val.set_endian_swap_mgmt_descriptor(zynq7000::eth::AhbEndianess::Little);
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val
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});
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}
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#[inline]
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@ -2,7 +2,7 @@ use arbitrary_int::u14;
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pub use super::shared::Ownership;
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/// RX buffer descriptor.
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/// TX buffer descriptor.
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///
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/// The user should declare an array of this structure inside uncached memory.
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///
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@ -29,7 +29,7 @@ pub enum TransmitChecksumGenerationStatus {
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PrematureEndOfFrame = 0b111,
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}
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#[bitbybit::bitfield(u32)]
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug, PartialEq, Eq)]
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pub struct Word1 {
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#[bit(31, rw)]
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@ -51,3 +51,28 @@ pub struct Word1 {
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#[bits(0..=13, rw)]
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tx_len: u14,
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}
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impl Descriptor {
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#[inline]
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pub fn set_ownership(&mut self, ownership: Ownership) {
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self.word1.set_ownership(ownership);
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}
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/// Set the wrap bit, which should be done for the last descriptor in the descriptor list.
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#[inline]
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pub fn set_wrap_bit(&mut self) {
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self.word1.set_wrap(true);
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}
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/// Set the information for a transfer.
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pub fn set_tx_transfer_info(
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&mut self,
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tx_len: u14,
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last_buffer: bool,
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no_crc_generation: bool,
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) {
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self.word1.set_tx_len(tx_len);
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self.word1.set_last_buffer(last_buffer);
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self.word1.set_no_crc_generation(no_crc_generation);
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}
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}
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@ -13,6 +13,7 @@ use slcr::Slcr;
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use zynq7000::slcr::LevelShifterReg;
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pub mod clocks;
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pub mod mmu;
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pub mod eth;
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pub mod gic;
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pub mod gpio;
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16
zynq7000-hal/src/mmu.rs
Normal file
16
zynq7000-hal/src/mmu.rs
Normal file
@ -0,0 +1,16 @@
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use zynq_mmu::L1Table;
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pub struct Mmu(&'static mut L1Table);
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impl Mmu {
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#[inline]
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pub const fn new(table: &'static mut L1Table) -> Self {
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Mmu(table)
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}
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pub fn update_l1_table(&mut self, f: impl FnOnce(&mut L1Table)) {
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// TODO: Disable MMU
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f(self.0);
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// DSB, ISB? enable MMU again.
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}
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}
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@ -11,8 +11,9 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
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categories = ["embedded", "no-std", "hardware-support"]
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[dependencies]
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cortex-a-rt = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", optional = true, features = ["vfp-dp"] }
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cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
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cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
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cortex-ar = "0.2"
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zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
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[features]
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default = ["rt"]
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@ -1,8 +1,14 @@
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use std::fs::File;
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use std::io::Write;
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use std::process::Command;
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use zynq7000_rt::mmu::ONE_MB;
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pub use zynq7000_rt::mmu::segments::*;
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use zynq7000_rt::mmu::ONE_MB;
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macro_rules! write_l1_section {
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($writer:expr, $offset:expr, $attr:expr) => {
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writeln!($writer, "L1Section::new({:#010x}, {}).raw_value(),", $offset, $attr).unwrap();
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};
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}
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fn main() {
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let file_path = "src/mmu_table.rs";
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@ -35,6 +41,7 @@ fn main() {
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+ OCM_MAPPED_HIGH,
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4096
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);
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let mut buf_writer = std::io::BufWriter::new(file);
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writeln!(
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buf_writer,
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@ -63,44 +70,24 @@ fn main() {
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"// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
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)
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.unwrap();
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_ddr
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_ddr);
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offset += ONE_MB;
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writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
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for _ in 0..DDR_FULL_ACCESSIBLE {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_ddr
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_ddr);
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offset += ONE_MB;
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}
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writeln!(buf_writer, "// FPGA slave 0 (0x4000_0000 - 0x8000_0000)").unwrap();
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for _ in 0..FPGA_SLAVE {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_fpga_slaves
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_fpga_slaves);
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offset += ONE_MB;
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}
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writeln!(buf_writer, "// FPGA slave 1 (0x8000_0000 - 0xC000_0000)").unwrap();
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for _ in 0..FPGA_SLAVE {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_fpga_slaves
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_fpga_slaves);
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offset += ONE_MB;
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}
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@ -110,12 +97,7 @@ fn main() {
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)
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.unwrap();
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for _ in 0..UNASSIGNED_0 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_unassigned);
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offset += ONE_MB;
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}
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@ -125,12 +107,7 @@ fn main() {
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)
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.unwrap();
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for _ in 0..IO_PERIPHS {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
|
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_shared_dev);
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offset += ONE_MB;
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}
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@ -140,45 +117,25 @@ fn main() {
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)
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.unwrap();
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for _ in 0..UNASSIGNED_1 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
|
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_unassigned);
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offset += ONE_MB;
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}
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writeln!(buf_writer, "// NAND (0xE100_0000 - 0xE200_0000)").unwrap();
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for _ in 0..NAND {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
|
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)
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_shared_dev);
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offset += ONE_MB;
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}
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|
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writeln!(buf_writer, "// NOR (0xE200_0000 - 0xE400_0000)").unwrap();
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for _ in 0..NOR {
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writeln!(
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buf_writer,
|
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"L1Section::new({}, {}).raw_value(),",
|
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offset, attr_shared_dev
|
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)
|
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_shared_dev);
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offset += ONE_MB;
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}
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writeln!(buf_writer, "// SRAM (0xE400_0000 - 0xE600_0000)").unwrap();
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for _ in 0..SRAM {
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writeln!(
|
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buf_writer,
|
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_sram
|
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)
|
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.unwrap();
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write_l1_section!(buf_writer, offset, attr_sram);
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offset += ONE_MB;
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}
|
||||
|
||||
@ -188,12 +145,7 @@ fn main() {
|
||||
)
|
||||
.unwrap();
|
||||
for _ in 0..SEGMENTS_UNASSIGNED_2 {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_unassigned
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_unassigned);
|
||||
offset += ONE_MB;
|
||||
}
|
||||
|
||||
@ -203,12 +155,7 @@ fn main() {
|
||||
)
|
||||
.unwrap();
|
||||
for _ in 0..AMBA_APB {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_shared_dev
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_shared_dev);
|
||||
offset += ONE_MB;
|
||||
}
|
||||
|
||||
@ -218,23 +165,13 @@ fn main() {
|
||||
)
|
||||
.unwrap();
|
||||
for _ in 0..UNASSIGNED_3 {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_unassigned
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_unassigned);
|
||||
offset += ONE_MB;
|
||||
}
|
||||
|
||||
writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
|
||||
for _ in 0..QSPI_XIP {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_qspi
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_qspi);
|
||||
offset += ONE_MB;
|
||||
}
|
||||
|
||||
@ -244,24 +181,14 @@ fn main() {
|
||||
)
|
||||
.unwrap();
|
||||
for _ in 0..UNASSIGNED_4 {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_unassigned
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_unassigned);
|
||||
offset += ONE_MB;
|
||||
}
|
||||
|
||||
writeln!(buf_writer, "// OCM High (0xFFF0_0000 - 0xFFFF_FFFF)").unwrap();
|
||||
let mut offset_u64 = offset as u64;
|
||||
for _ in 0..OCM_MAPPED_HIGH {
|
||||
writeln!(
|
||||
buf_writer,
|
||||
"L1Section::new({}, {}).raw_value(),",
|
||||
offset, attr_ocm_high
|
||||
)
|
||||
.unwrap();
|
||||
write_l1_section!(buf_writer, offset, attr_ocm_high);
|
||||
|
||||
offset_u64 += ONE_MB as u64;
|
||||
}
|
||||
|
@ -162,12 +162,6 @@ pub mod section_attrs {
|
||||
};
|
||||
}
|
||||
|
||||
pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
|
||||
|
||||
#[repr(C, align(16384))]
|
||||
#[cfg(feature = "rt")]
|
||||
pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
|
||||
|
||||
/// Load the MMU translation table base address into the MMU.
|
||||
///
|
||||
/// # Safety
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -80,7 +80,7 @@ impl MdcClkDiv {
|
||||
}
|
||||
}
|
||||
|
||||
#[bitbybit::bitfield(u32)]
|
||||
#[bitbybit::bitfield(u32, default = 0x0)]
|
||||
#[derive(Debug)]
|
||||
pub struct NetworkConfig {
|
||||
#[bit(30, rw)]
|
||||
@ -234,6 +234,7 @@ pub struct DmaConfig {
|
||||
/// Default value is 0x1 (big endian)
|
||||
#[bit(7, rw)]
|
||||
endian_swap_packet_data: AhbEndianess,
|
||||
// Default value is 0x0 (little endian)
|
||||
#[bit(6, rw)]
|
||||
endian_swap_mgmt_descriptor: AhbEndianess,
|
||||
#[bits(0..=4, rw)]
|
||||
|
Loading…
x
Reference in New Issue
Block a user