continue, update MMU handling

2025-05-30 11:46:13 +02:00
parent d0d0d48780
commit b8bb7e23c7
15 changed files with 4278 additions and 4222 deletions
--- a/zynq7000/src/eth.rs
+++ b/zynq7000/src/eth.rs
@ -80,7 +80,7 @@ impl MdcClkDiv {
    }
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
 pub struct NetworkConfig {
    #[bit(30, rw)]
@ -234,6 +234,7 @@ pub struct DmaConfig {
    /// Default value is 0x1 (big endian)
    #[bit(7, rw)]
    endian_swap_packet_data: AhbEndianess,
+    // Default value is 0x0 (little endian)
    #[bit(6, rw)]
    endian_swap_mgmt_descriptor: AhbEndianess,
    #[bits(0..=4, rw)]