continue, update MMU handling

zynq7000-hal/src/eth/tx_descr.rs

@@ -2,7 +2,7 @@ use arbitrary_int::u14;
 
 pub use super::shared::Ownership;
 
-/// RX buffer descriptor.
+/// TX buffer descriptor.
 ///
 /// The user should declare an array of this structure inside uncached memory.
 ///
@@ -29,7 +29,7 @@ pub enum TransmitChecksumGenerationStatus {
     PrematureEndOfFrame = 0b111,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug, PartialEq, Eq)]
 pub struct Word1 {
     #[bit(31, rw)]
@@ -51,3 +51,28 @@ pub struct Word1 {
     #[bits(0..=13, rw)]
     tx_len: u14,
 }
+
+impl Descriptor {
+    #[inline]
+    pub fn set_ownership(&mut self, ownership: Ownership) {
+        self.word1.set_ownership(ownership);
+    }
+
+    /// Set the wrap bit, which should be done for the last descriptor in the descriptor list.
+    #[inline]
+    pub fn set_wrap_bit(&mut self) {
+        self.word1.set_wrap(true);
+    }
+
+    /// Set the information for a transfer.
+    pub fn set_tx_transfer_info(
+        &mut self,
+        tx_len: u14,
+        last_buffer: bool,
+        no_crc_generation: bool,
+    ) {
+        self.word1.set_tx_len(tx_len);
+        self.word1.set_last_buffer(last_buffer);
+        self.word1.set_no_crc_generation(no_crc_generation);
+    }
+}