prepare run-time patch release

Reviewed-on: #28

.cargo/config.toml.template

@@ -2,7 +2,7 @@
 # The following two env variables need to be set for the supplied runner.sh script to work.
 
 # Absolute path to the Vitis install directory.
-# AMD_TOOLS = "/tools/Xilinx/Vitis/2024.1"
+# AMD_TOOLS = "/tools/2025.2/Vitis"
 # Absolute path to the PS7 initialization TCL script.
 # TCL_INIT_SCRIPT = "/home/$user/$project/$sdt_dir/ps7_init.tcl"
 

tools/Cargo.lock

@@ -725,7 +725,7 @@ dependencies = [
 
 [[package]]
 name = "zynq7000-rt"
-version = "0.1.1"
+version = "0.1.2"
 dependencies = [
  "aarch32-cpu",
  "arbitrary-int 2.0.0",

zedboard-fpga-design/README.md

@@ -10,9 +10,9 @@ hardware design to other boards with modifications.
 
 - [Vivado installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html)
   or [Vitis installation](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html)
-  which includes Vivado. This example design was created with/for Vivado 2024.1, but also might work
+  which includes Vivado. This example design was created with/for Vivado 2025.2, but also might work
+  for newer versions. You might have to manually adjust some variables in `src/zedboard-bd.tcl`
   for newer versions.
-- [Zedboard board files](https://github.com/Digilent/vivado-boards) added to the Vivado installation.
 
 # Loading the project and the block design with the GUI
 
@@ -54,7 +54,7 @@ named `sdt_out` for a hardware description files `zedboard-rust/zedboard-rust.xs
 assuming that the Vitis tool suite is installed at `/tools/Xilinx/Vitis/2024.1`:
 
 ```sh
-export AMD_TOOLS="/tools/Xilinx/Vitis/2024.1"
+export AMD_TOOLS="/tools/2025.2/Vitis"
 ./sdtgen.py -x ./zedboard-rust/zedboard-rust.xsa
 ```
 

zedboard-fpga-design/src/zedboard-bd.tcl

@@ -20,7 +20,7 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2024.1
+set scripts_vivado_version 2025.2
 set current_vivado_version [version -short]
 
 if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
@@ -57,7 +57,6 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
    create_project project_1 myproj -part xc7z020clg484-1
-   set_property BOARD_PART digilentinc.com:zedboard:part0:1.1 [current_project]
 }
 
 

zedboard-fpga-design/zedboard-rust.tcl

@@ -131,7 +131,6 @@ set proj_dir [get_property directory [current_project]]
 
 # Set project properties
 set obj [current_project]
-set_property -name "board_part" -value "digilentinc.com:zedboard:part0:1.1" -objects $obj
 set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
 set_property -name "enable_resource_estimation" -value "0" -objects $obj
 set_property -name "enable_vhdl_2008" -value "1" -objects $obj
@@ -221,10 +220,10 @@ catch {
 
 # Create 'synth_1' run (if not found)
 if {[string equal [get_runs -quiet synth_1] ""]} {
-    create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+    create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2025} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
 } else {
   set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
-  set_property flow "Vivado Synthesis 2024" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2025" [get_runs synth_1]
 }
 set obj [get_runs synth_1]
 set_property set_report_strategy_name 1 $obj
@@ -248,10 +247,10 @@ current_run -synthesis [get_runs synth_1]
 
 # Create 'impl_1' run (if not found)
 if {[string equal [get_runs -quiet impl_1] ""]} {
-    create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+    create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2025} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
 } else {
   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
-  set_property flow "Vivado Implementation 2024" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2025" [get_runs impl_1]
 }
 set obj [get_runs impl_1]
 set_property set_report_strategy_name 1 $obj

zynq/zynq7000-rt/CHANGELOG.md

@@ -8,6 +8,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
+# [v0.1.2] 2025-11-28
+
+Bugfixes in startup assembler code.
+
+## Changed
+
+- `.data` initialization is skipped if it is already in place, which is usually the default
+  case because it is flashed to RAM.
+
+## Fixed
+
+- Stack initialization was bugged and stack was not properly initialized for some of the
+  processor modes (all modes except system mode and IRQ mode).
+- MMU is enabled after the MMU table was copied (which is done in the `.data` coping step).
+
 # [v0.1.1] 2025-10-10
 
 Documentation fixes.
@@ -16,6 +31,7 @@ Documentation fixes.
 
 Initial release
 
-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.0...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.2...HEAD
+[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.1...zynq7000-rt-v0.1.2
 [v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.0...zynq7000-rt-v0.1.1
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tag/zynq7000-rt-v0.1.0

zynq/zynq7000-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "zynq7000-rt"
-version = "0.1.1"
+version = "0.1.2"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2024"
 description = "Run-time support for the Zynq7000 family of SoCs for running bare-metal applications"

zynq/zynq7000-rt/src/mmu.rs

@@ -183,7 +183,8 @@ pub mod section_attrs {
 #[unsafe(no_mangle)]
 #[cfg(feature = "rt")]
 unsafe extern "C" fn load_mmu_table() {
-    let table_base = crate::mmu_table::MMU_L1_PAGE_TABLE.0.get() as u32;
+    // if usize != u32 we are on the wrong platform...
+    let table_base = crate::mmu_table::MMU_L1_PAGE_TABLE.0.get().addr() as u32;
 
     unsafe {
         core::arch::asm!(

zynq/zynq7000-rt/src/rt.rs

@@ -96,64 +96,43 @@ initialize:
     // Set up stacks first.
     ldr     r3, =_stack_top
 
-    // get the current PSR
-    mrs	r0, cpsr
-    // mask for mode bits
-    mvn	r1, #0x1f
-    and	r2, r1, r0
-    // IRQ mode
-    orr	r2, r2, {irq_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for IRQ mode (Mode 0x12)
+    msr cpsr_c, {irq_mode}
     // IRQ stack pointer
     mov	sp, r3
     ldr r1, =_irq_stack_size
     sub r3, r3, r1
 
-    mrs	r0, cpsr
-    and	r2, r1, r0
-    // Supervisor mode
-    orr	r2, r2, {svc_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for Supervisor/SVC mode (Mode 0x13)
+    msr cpsr_c, {svc_mode}
     // Supervisor stack pointer
     mov	sp, r3
     ldr r1, =_svc_stack_size
     sub r3, r3, r1
 
-    mrs	r0, cpsr
-    and	r2, r1, r0
-    // Abort mode
-    orr	r2, r2, {abt_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for Abort/ABT mode (Mode 0x17)
+    msr cpsr_c, {abt_mode}
     // Abort stack pointer
     mov	sp, r3
     ldr r1, =_abt_stack_size
     sub r3, r3, r1
 
-    mrs	r0, cpsr
-    and	r2, r1, r0
-    // FIQ mode
-    orr	r2, r2, {fiq_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for FIQ mode (Mode 0x11)
+    msr cpsr_c, {fiq_mode}
     // FIQ stack pointer
     mov	sp, r3
     ldr r1, =_fiq_stack_size
     sub r3, r3, r1
 
-    mrs	r0, cpsr
-    and	r2, r1, r0
-    // Undefined mode
-    orr	r2, r2, {und_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for Undefined/UND mode (Mode 0x1B)
+    msr cpsr_c, {und_mode}
     // Undefined stack pointer
     mov	sp, r3
     ldr r1, =_und_stack_size
     sub r3, r3, r1
 
-    mrs	r0, cpsr
-    and	r2, r1, r0
-    // System mode
-    orr	r2, r2, {sys_mode}
-    msr	cpsr, r2
+    // Set stack pointer (right after) and mask interrupts for System/SYS mode (Mode 0x1F)
+    msr cpsr_c, {sys_mode}
     // System stack pointer (main stack)
     mov	sp, r3
 
@@ -163,18 +142,6 @@ initialize:
     orr	r0, r0, #0x1
     str	r0, [r7]
 
-    /* enable MMU and cache */
-    bl load_mmu_table
-
-    mvn	r0,#0				/* Load MMU domains -- all ones=manager */
-    mcr	p15,0,r0,c3,c0,0
-
-    /* Enable mmu, icahce and dcache */
-    ldr	r0,=CRValMmuCac
-    mcr	p15,0,r0,c1,c0,0		/* Enable cache and MMU */
-    dsb					/* dsb	allow the MMU to start up */
-    isb					/* isb	flush prefetch buffer */
-
     /* Write to ACTLR */
     mrc	p15, 0, r0, c1, c0, 1		/* Read ACTLR*/
     orr	r0, r0, #(0x01 << 6)		/* set SMP bit */
@@ -220,13 +187,29 @@ initialize:
     ldr     r0, =__sdata
     ldr     r1, =__edata
     ldr     r2, =__sidata
+    cmp     r0, r2          /* Shortcut if code is run from RAM and .data is there already */
+    beq     data_init_done
 0:
     cmp     r1, r0
-    beq     1f
+    beq     data_init_done
     ldm     r2!, {{r3}}
     stm     r0!, {{r3}}
     b       0b
-1:
+data_init_done:
+    /* enable MMU and cache */
+    /* MMU Table is in .data, so this needs to be performed after .data is relocated */
+    /* (Even if in most cases, .data is already in RAM and relocation is a no-op) */
+    bl load_mmu_table
+
+    mvn	r0,#0				/* Load MMU domains -- all ones=manager */
+    mcr	p15,0,r0,c3,c0,0
+
+    /* Enable mmu, icache and dcache */
+    ldr	r0,=CRValMmuCac
+    mcr	p15,0,r0,c1,c0,0		/* Enable cache and MMU */
+    dsb					/* dsb	allow the MMU to start up */
+    isb					/* isb	flush prefetch buffer */
+
     // Jump to application
     // Load CPU ID 0, which will be used as a function argument to the boot_core function.
     mov      r0, #0x0