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merge into: rust:main
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rust:main rust:add-smoltcp-support
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pull from: rust:add-smoltcp-support
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rust:main rust:add-smoltcp-support

2 Commits

Author SHA1 Message Date
Robin Mueller
ecdb01ca7d one zero too much, delete obsolete module 2025-06-26 19:24:57 +02:00
Robin Mueller
807d9df0c2 start adding ethernet support 2025-06-26 19:20:27 +02:00
37 changed files with 7862 additions and 4241 deletions
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2
Cargo.toml
View File

@ -7,6 +7,6 @@ members = [
"zynq7000-embassy",
"examples/simple",
"examples/embassy",
"examples/zedboard",
"examples/zedboard", "zynq-mmu",
]
exclude = ["experiments"]

14
examples/embassy/Cargo.toml
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@ -11,7 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }
@ -25,12 +26,17 @@ embedded-hal = "1"
fugit = "0.3"
log = "0.4"
embassy-executor = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", features = [
# embassy-executor = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", features = [
# "arch-cortex-ar",
# "executor-thread",
# "task-arena-size-65536"
# ]}
embassy-executor = { path = "../../../../Rust/embassy/embassy-executor", features = [
"arch-cortex-ar",
"executor-thread",
"task-arena-size-65536"
]}
embassy-time = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.4", features = ["tick-hz-1_000_000"] }
# embassy-time = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.4", features = ["tick-hz-1_000_000"] }
embassy-time = { path = "../../../../Rust/embassy/embassy-time", version = "0.4", features = ["tick-hz-1_000_000"] }
[profile.release]
codegen-units = 1

4
examples/embassy/src/bin/dht22-open-drain-pins.rs
View File

@ -10,13 +10,13 @@ use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
use embedded_io::Write;
use log::{error, info, warn};
use zynq7000_hal::{
BootMode,
clocks::Clocks,
gic::{GicConfigurator, GicInterruptHelper, Interrupt},
gpio::{mio, Flex, Output, PinState},
gpio::{Flex, Output, PinState, mio},
gtc::Gtc,
time::Hertz,
uart::{ClkConfigRaw, Uart, UartConfig},
BootMode,
};
use zynq7000::PsPeripherals;

3
examples/simple/Cargo.toml
View File

@ -9,7 +9,8 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
license = "MIT OR Apache-2.0"
[dependencies]
cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }

13
examples/zedboard/Cargo.toml
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@ -11,7 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
# cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", features = ["critical-section-single-core"] }
cortex-ar = { version = "0.2", path = "../../../../Rust/cortex-ar/cortex-ar", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }
@ -28,12 +29,16 @@ embedded-hal-async = "1"
fugit = "0.3"
log = "0.4"
embassy-executor = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", features = [
# embassy-executor = { git = "https://github.com/us-irs/embassy", path = "../embassy/embassy-executor", branch = "local-cortex-ar", features = [
# "arch-cortex-ar",
# "executor-thread",
# ]}
embassy-executor = { path = "../../../../Rust/embassy/embassy-executor", features = [
"arch-cortex-ar",
"executor-thread",
"task-arena-size-65536"
]}
embassy-time = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.4", features = ["tick-hz-1_000_000"] }
# embassy-time = { git = "https://github.com/us-irs/embassy", branch = "local-cortex-ar", version = "0.4", features = ["tick-hz-1_000_000"] }
embassy-time = { path = "../../../../Rust/embassy/embassy-time", version = "0.4", features = ["tick-hz-1_000_000"] }
heapless = "0.8"
axi-uartlite = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uartlite.git" }
axi-uart16550 = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uart16550.git" }

198
examples/zedboard/src/bin/ethernet.rs Normal file
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@ -0,0 +1,198 @@
#![no_std]
#![no_main]
use core::{mem::MaybeUninit, panic::PanicInfo};
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;
use embedded_io::Write;
use log::{error, info};
use zedboard::PS_CLOCK_FREQUENCY;
use zynq7000_hal::{
BootMode,
clocks::Clocks,
configure_level_shifter,
gic::{GicConfigurator, GicInterruptHelper, Interrupt},
gpio::{GpioPins, Output, PinState},
gtc::Gtc,
uart::{ClkConfigRaw, Uart, UartConfig},
};
use zynq7000::{PsPeripherals, slcr::LevelShifterConfig};
use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut};
const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
#[unsafe(link_section = ".uncached")]
static RX_DESCRIPTORS: static_cell::ConstStaticCell<
MaybeUninit<[zynq7000_hal::eth::rx_descr::Descriptor; 32]>,
> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
#[unsafe(link_section = ".uncached")]
static TX_DESCRIPTORS: static_cell::ConstStaticCell<
MaybeUninit<[zynq7000_hal::eth::tx_descr::Descriptor; 32]>,
> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
#[repr(align(32))]
#[derive(Debug, Clone, Copy)]
pub struct AlignedBuffer(pub [u8; zynq7000_hal::eth::MTU]);
const NUM_RX_BUFS: usize = 32;
const NUM_TX_BUFS: usize = 32;
static ETH_RX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_RX_BUFS]> =
static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_RX_BUFS]);
static ETH_TX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_TX_BUFS]> =
static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_TX_BUFS]);
/// See memory.x file. 1 MB starting at this address will be configured as uncached memory using the
/// MMU.
const UNCACHED_ADDR: u32 = 0x4000000;
/// Entry point (not called like a normal main function)
#[unsafe(no_mangle)]
pub extern "C" fn boot_core(cpu_id: u32) -> ! {
if cpu_id != 0 {
panic!("unexpected CPU ID {}", cpu_id);
}
main();
}
#[embassy_executor::main]
#[unsafe(export_name = "main")]
async fn main(_spawner: Spawner) -> ! {
// Configure the uncached memory region using the MMU.
mmu_l1_table_mut().update(UNCACHED_ADDR, SHAREABLE_DEVICE);
// Enable PS-PL level shifters.
configure_level_shifter(LevelShifterConfig::EnableAll);
let dp = PsPeripherals::take().unwrap();
// Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
// Set up the global interrupt controller.
let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
gic.enable_all_interrupts();
gic.set_all_spi_interrupt_targets_cpu0();
gic.enable();
unsafe {
gic.enable_interrupts();
}
let mut gpio_pins = GpioPins::new(dp.gpio);
// Set up global timer counter and embassy time driver.
let gtc = Gtc::new(dp.gtc, clocks.arm_clocks());
zynq7000_embassy::init(clocks.arm_clocks(), gtc);
// Set up the UART, we are logging with it.
let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
.unwrap()
.0;
let mut uart = Uart::new_with_mio(
dp.uart_1,
UartConfig::new_with_clk_config(uart_clk_config),
(gpio_pins.mio.mio48, gpio_pins.mio.mio49),
)
.unwrap();
uart.write_all(INIT_STRING.as_bytes()).unwrap();
// Safety: We are not multi-threaded yet.
unsafe {
zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
uart,
log::LevelFilter::Trace,
false,
)
};
let boot_mode = BootMode::new();
let rx_bufs = ETH_RX_BUFS.take();
let rx_descr = RX_DESCRIPTORS.take();
let tx_descr = TX_DESCRIPTORS.take();
rx_descr.write([const { zynq7000_hal::eth::rx_descr::Descriptor::new() }; 32]);
tx_descr.write([const { zynq7000_hal::eth::tx_descr::Descriptor::new() }; 32]);
let mut rx_descr_ref =
zynq7000_hal::eth::rx_descr::DescriptorListRef::new(unsafe { &mut *rx_descr.as_mut_ptr() });
let mut tx_descr_ref =
zynq7000_hal::eth::tx_descr::DescriptorListRef::new(unsafe { &mut *tx_descr.as_mut_ptr() });
rx_descr_ref.init();
tx_descr_ref.init();
for (index, rx_buf) in rx_bufs.iter().enumerate() {
rx_descr_ref.set_rx_buf_address(index, rx_buf.0.as_ptr() as u32);
}
info!("Boot mode: {:?}", boot_mode);
let mut ticker = Ticker::every(Duration::from_millis(200));
let mut mio_led = Output::new_for_mio(gpio_pins.mio.mio7, PinState::Low);
let mut emio_leds: [Output; 8] = [
Output::new_for_emio(gpio_pins.emio.take(0).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(1).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(2).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(3).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(4).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(5).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(6).unwrap(), PinState::Low),
Output::new_for_emio(gpio_pins.emio.take(7).unwrap(), PinState::Low),
];
loop {
mio_led.toggle().unwrap();
// Create a wave pattern for emio_leds
for led in emio_leds.iter_mut() {
led.toggle().unwrap();
ticker.next().await; // Wait for the next ticker for each toggle
}
ticker.next().await; // Wait for the next cycle of the ticker
}
}
#[unsafe(no_mangle)]
pub extern "C" fn _irq_handler() {
let mut gic_helper = GicInterruptHelper::new();
let irq_info = gic_helper.acknowledge_interrupt();
match irq_info.interrupt() {
Interrupt::Sgi(_) => (),
Interrupt::Ppi(ppi_interrupt) => {
if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
unsafe {
zynq7000_embassy::on_interrupt();
}
}
}
Interrupt::Spi(_spi_interrupt) => (),
Interrupt::Invalid(_) => (),
Interrupt::Spurious => (),
}
gic_helper.end_of_interrupt(irq_info);
}
#[unsafe(no_mangle)]
pub extern "C" fn _abort_handler() {
loop {
nop();
}
}
#[unsafe(no_mangle)]
pub extern "C" fn _undefined_handler() {
loop {
nop();
}
}
#[unsafe(no_mangle)]
pub extern "C" fn _prefetch_handler() {
loop {
nop();
}
}
/// Panic handler
#[panic_handler]
fn panic(info: &PanicInfo) -> ! {
error!("Panic: {:?}", info);
loop {}
}

19
memory.x
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@ -1,8 +1,23 @@
MEMORY
{
/* Zedboard: 512 MB DDR3. Only use 256 MB for now, should be plenty for a bare-metal app. */
CODE(rx) : ORIGIN = 0x00100000, LENGTH = 256M
/* Zedboard: 512 MB DDR3. Only use 63 MB for now, should be plenty for a bare-metal app.
Leave 1 MB of memory which will be configured as uncached device memory by the MPU. This is
recommended for something like DMA descriptors. */
CODE(rx) : ORIGIN = 0x00100000, LENGTH = 63M
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("DATA", CODE);
SECTIONS
{
/* Uncached memory */
.uncached (NOLOAD) : ALIGN(4) {
. = ALIGN(4);
_sbss_uncached = .;
*(.uncached .uncached.*);
. = ALIGN(4);
_ebss_uncached = .;
} > UNCACHED
}

9
zynq-mmu/Cargo.toml Normal file
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@ -0,0 +1,9 @@
[package]
name = "zynq-mmu"
description = "Zynq MMU structures"
version = "0.1.0"
edition = "2024"
[dependencies]
cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
thiserror = { version = "2", default-features = false }

73
zynq-mmu/src/lib.rs Normal file
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@ -0,0 +1,73 @@
//! The MMU structures live inside a dedicated shared crate so it can be used by both the Zynq
//! runtime crate and teh HAL crate.
#![no_std]
use cortex_ar::{
asm::{dsb, isb},
cache::clean_and_invalidate_l1_data_cache,
mmu::SectionAttributes,
register::{BpIAll, TlbIAll},
};
pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
#[derive(Debug, PartialEq, Eq, thiserror::Error)]
#[error("address is not aligned to 1MB boundary")]
pub struct AddrNotAlignedToOneMb;
#[repr(C, align(16384))]
pub struct L1Table(pub [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
impl L1Table {
#[inline(always)]
pub const fn as_ptr(&self) -> *const u32 {
self.0.as_ptr()
}
#[inline(always)]
pub const fn as_mut_ptr(&mut self) -> *mut u32 {
self.0.as_mut_ptr()
}
pub fn update(
&mut self,
addr: u32,
section_attrs: SectionAttributes,
) -> Result<(), AddrNotAlignedToOneMb> {
if addr & 0x000F_FFFF != 0 {
return Err(AddrNotAlignedToOneMb);
}
let index = addr as usize / 0x10_0000;
self.0[index] = (self.0[index] & 0xFFF0_0000) | section_attrs.raw();
// The Zynq 7000 has a 32 kB 4-way associative cache with a line length of 32 bytes.
// 4-way associative cache: A == 2
// 32 bytes line length: N == 5
// 256 (32kB / (32 * 4)) sets: S == 8
clean_and_invalidate_l1_data_cache::<2, 5, 8>();
TlbIAll::write();
BpIAll::write();
dsb();
isb();
Ok(())
}
}
pub struct L1TableRef<'a>(pub &'a mut L1Table);
impl<'a> L1TableRef<'a> {
pub fn new(l1_table: &'a mut L1Table) -> L1TableRef<'a> {
L1TableRef(l1_table)
}
}
impl L1TableRef<'_> {
pub fn update(
&mut self,
addr: u32,
section_attrs: SectionAttributes,
) -> Result<(), AddrNotAlignedToOneMb> {
self.0.update(addr, section_attrs)
}
}

485
zynq-mmu/target/rust-analyzer/metadata/sysroot/Cargo.lock generated Normal file
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@ -0,0 +1,485 @@
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6
zynq7000-embassy/Cargo.toml
View File

@ -15,5 +15,7 @@ critical-section = "1"
once_cell = { version = "1", default-features = false, features = ["critical-section"] }
zynq7000-hal = { path = "../zynq7000-hal" }
embassy-time-driver = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.2" }
embassy-time-queue-utils = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.1" }
# embassy-time-driver = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.2" }
# embassy-time-queue-utils = { git = "https://github.com/us-irs/embassy", branch = "add-cortex-ar-support", version = "0.2" }
embassy-time-driver = { path = "../../../Rust/embassy/embassy-time-driver", version = "0.2" }
embassy-time-queue-utils = { path = "../../../Rust/embassy/embassy-time-queue-utils", version = "0.1" }

4
zynq7000-hal/Cargo.toml
View File

@ -11,9 +11,11 @@ keywords = ["no-std", "hal", "amd", "zynq7000", "xilinx", "bare-metal"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
zynq7000 = { path = "../zynq7000" }
zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
bitbybit = "1.3"
arbitrary-int = "1.3"
thiserror = { version = "2", default-features = false }
num_enum = { version = "0.7", default-features = false }

92
zynq7000-hal/src/cache.rs Normal file
View File

@ -0,0 +1,92 @@
use cortex_ar::{
asm::dsb,
cache::{
clean_and_invalidate_data_cache_line_to_poc, clean_data_cache_line_to_poc,
invalidate_data_cache_line_to_poc,
},
};
use zynq7000::l2_cache::{L2Cache, MmioL2Cache};
#[derive(Debug, Clone, Copy, PartialEq, Eq, thiserror::Error)]
#[error("alignment error, addresses and lengths must be aligned to 32 byte cache line length")]
pub struct AlignmentError;
pub fn clean_and_invalidate_l2c_line(l2c: &mut MmioL2Cache<'static>, addr: u32) {
l2c.write_clean_by_pa(addr);
l2c.write_invalidate_by_pa(addr);
}
/// Invalidate an address range.
///
/// This function invalidates both the L1 and L2 cache. The L2C must be enabled and set up
/// correctly for this function to work correctly.
///
/// The provided address and the range to invalidate must both be aligned to the 32 byte cache line
/// length.
pub fn invalidate_data_cache_range(addr: u32, len: usize) -> Result<(), AlignmentError> {
if addr % 32 != 0 || len % 32 != 0 {
return Err(AlignmentError);
}
let mut l2c = unsafe { L2Cache::new_mmio_fixed() };
let mut current_addr = addr;
// Invalidate outer caches lines first, see chapter 3.3.10 of the L2C technical reference manual.
while current_addr < addr + len as u32 {
l2c.write_clean_by_pa(current_addr);
current_addr += 32;
}
while l2c.read_cache_sync().busy() {}
// Invalidate inner cache lines.
current_addr = addr;
while current_addr < addr + len as u32 {
invalidate_data_cache_line_to_poc(addr);
current_addr += 32;
}
// Synchronize the cache maintenance.
dsb();
Ok(())
}
/// Clean and then invalidate an address range.
///
/// This is commonly also called cache flushing. This function cleans and invalidates both L1
/// and L2 cache. The L2C must be enabled and set up correctly for this function to work correctly.
pub fn clean_and_invalidate_data_cache_range(addr: u32, len: usize) -> Result<(), AlignmentError> {
if addr % 32 != 0 || len % 32 != 0 {
return Err(AlignmentError);
}
// For details on the following section, see chapter 3.3.10 of the L2C technical reference
// manual.
// Clean inner cache lines first.
let mut current_addr = addr;
while current_addr < addr + len as u32 {
clean_data_cache_line_to_poc(current_addr);
current_addr += 32;
}
dsb();
// Clean and invalidates outer cache.
let mut l2c = unsafe { L2Cache::new_mmio_fixed() };
current_addr = addr;
while current_addr < addr + len as u32 {
// ARM errate 588369 specifies that clean and invalidate need to be separate, but the
// current revision of the L2C on the Zynq7000 seems to be revision 8 (r3p2), and the
// errata was fixed in r2p0. Both Xilinx and zynq-rs use the clean and invalidate operation,
// so it should be fine. Considering the debug control in Xilinx code which disable
// linefills and write-backs, zynq-rs does not appear to do that and it should not be
// necessary.. I think this was related to the errata.
l2c.write_clean_invalidate_by_pa(current_addr);
current_addr += 32;
}
while l2c.read_cache_sync().busy() {}
// Now clean and invalidate inner cache.
current_addr = addr;
while current_addr < addr + len as u32 {
clean_and_invalidate_data_cache_line_to_poc(current_addr);
current_addr += 32;
}
dsb();
Ok(())
}

210
zynq7000-hal/src/eth/ll.rs Normal file
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use arbitrary_int::{Number, u6};
use zynq7000::{
eth::{InterruptControl, NetworkControl, RxStatus, TxStatus},
slcr::reset::EthernetReset,
};
use crate::{enable_amba_peripheral_clock, slcr::Slcr, time::Hertz};
use super::{EthernetId, PsEthernet as _};
pub struct EthernetLowLevel {
id: EthernetId,
pub regs: zynq7000::eth::MmioEthernet<'static>,
}
#[derive(Debug, Clone, Copy)]
pub struct ClkConfig {
pub src_sel: zynq7000::slcr::clocks::SrcSelIo,
pub use_emio_tx_clk: bool,
pub divisor_0: u6,
pub divisor_1: u6,
/// Enable the clock.
pub enable: bool,
}
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Speed {
Mbps10,
Mbps100,
Mbps1000,
}
impl Speed {
pub const fn rgmii_clk_rate(&self) -> Hertz {
match self {
Speed::Mbps10 => Hertz::from_raw(2_500_000),
Speed::Mbps100 => Hertz::from_raw(25_000_000),
Speed::Mbps1000 => Hertz::from_raw(125_000_000),
}
}
}
impl ClkConfig {
pub const fn new(divisor_0: u6, divisor_1: u6) -> Self {
Self {
src_sel: zynq7000::slcr::clocks::SrcSelIo::IoPll,
use_emio_tx_clk: false,
divisor_0,
divisor_1,
enable: true,
}
}
/// Calculate the best clock configuration (divisors) for the given reference clock
/// and desired target speed when using a RGMII interface.
///
/// Usually, the reference clock will be the IO clock.
///
/// Returns a tuple where the first entry is the calcualted clock configuration
/// and the second entry is the difference between calculated clock speed for the divisors
/// and the target speed. Ideally, this difference should be 0.
pub fn calculate_for_rgmii(ref_clk: Hertz, target_speed: Speed) -> (Self, u32) {
let mut smallest_diff = u32::MAX;
let target_speed = target_speed.rgmii_clk_rate();
let mut best_div_0 = u6::new(0);
let mut best_div_1 = u6::new(0);
for div_0 in 0..=u6::MAX.as_usize() {
for div_1 in 0..=u6::MAX.as_usize() {
let clk_rate = ref_clk.raw() / div_0 as u32 / div_1 as u32;
let diff = (target_speed.raw() as i64 - clk_rate as i64).unsigned_abs() as u32;
if diff < smallest_diff {
smallest_diff = diff;
best_div_0 = u6::new(div_0 as u8);
best_div_1 = u6::new(div_1 as u8);
}
// We found a perfect match. No need to continue.
if diff == 0 {
break;
}
}
}
(Self::new(best_div_0, best_div_1), smallest_diff)
}
}
/// Ethernet low-level interface.
impl EthernetLowLevel {
/// Creates a new instance of the Ethernet low-level interface.
#[inline]
pub fn new(regs: zynq7000::eth::MmioEthernet<'static>) -> Option<Self> {
regs.id()?;
Some(EthernetLowLevel {
id: regs.id().unwrap(),
regs,
})
}
/// Create a low-level instance for the given [EthernetId].
///
/// # Safety
///
/// Circumvents ownership and safety guarantees of the HAL.
#[inline]
pub const unsafe fn steal(id: EthernetId) -> Self {
Self {
id,
regs: unsafe {
match id {
EthernetId::Eth0 => zynq7000::eth::Ethernet::new_mmio_fixed_0(),
EthernetId::Eth1 => zynq7000::eth::Ethernet::new_mmio_fixed_1(),
}
},
}
}
pub fn reset(&mut self, cycles: usize) {
let assert_reset = match self.id {
EthernetId::Eth0 => EthernetReset::builder()
.with_gem1_ref_rst(false)
.with_gem0_ref_rst(true)
.with_gem1_rx_rst(false)
.with_gem0_rx_rst(true)
.with_gem1_cpu1x_rst(false)
.with_gem0_cpu1x_rst(true)
.build(),
EthernetId::Eth1 => EthernetReset::builder()
.with_gem1_ref_rst(true)
.with_gem0_ref_rst(false)
.with_gem1_rx_rst(true)
.with_gem0_rx_rst(false)
.with_gem1_cpu1x_rst(true)
.with_gem0_cpu1x_rst(false)
.build(),
};
unsafe {
Slcr::with(|regs| {
regs.reset_ctrl().write_eth(assert_reset);
for _ in 0..cycles {
cortex_ar::asm::nop();
}
regs.reset_ctrl().write_eth(EthernetReset::DEFAULT);
});
}
}
#[inline]
pub fn enable_peripheral_clock(&mut self) {
let periph_sel = match self.id {
EthernetId::Eth0 => crate::PeripheralSelect::Gem0,
EthernetId::Eth1 => crate::PeripheralSelect::Gem1,
};
enable_amba_peripheral_clock(periph_sel);
}
#[inline]
pub fn configure_clock(&mut self, cfg: ClkConfig) {
unsafe {
Slcr::with(|regs| {
regs.clk_ctrl().modify_gem_0_clk_ctrl(|mut val| {
val.set_srcsel(cfg.src_sel);
val.set_divisor_0(cfg.divisor_0);
val.set_divisor_1(cfg.divisor_1);
val.set_use_emio_tx_clk(cfg.use_emio_tx_clk);
val.set_clk_act(cfg.enable);
val
});
})
}
}
#[inline]
pub fn set_promiscous_mode(&mut self, enable: bool) {
self.regs.modify_net_cfg(|mut val| {
val.set_copy_all_frames(enable);
val
});
}
#[inline]
pub fn set_rx_buf_descriptor_base_address(&mut self, addr: u32) {
self.regs.write_rx_buf_queue_base_addr(addr);
}
#[inline]
pub fn set_tx_buf_descriptor_base_address(&mut self, addr: u32) {
self.regs.write_tx_buf_queue_base_addr(addr);
}
/// Performs initialization according to TRM p.541.
///
/// These steps do not include any resets or clock configuration.
pub fn initialize(&mut self) {
let mut ctrl_val = NetworkControl::new_with_raw_value(0);
self.regs.write_net_ctrl(ctrl_val);
// Now clear statistics.
ctrl_val.set_clear_statistics(true);
self.regs.write_net_ctrl(ctrl_val);
self.regs.write_tx_status(TxStatus::new_clear_all());
self.regs.write_rx_status(RxStatus::new_clear_all());
self.regs
.write_interrupt_disable(InterruptControl::new_clear_all());
self.regs.write_rx_buf_queue_base_addr(0);
self.regs.write_tx_buf_queue_base_addr(0);
}
#[inline]
pub const fn id(&self) -> EthernetId {
self.id
}
}

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zynq7000-hal/src/eth/mdio.rs Normal file
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use arbitrary_int::{u2, u5};
use zynq7000::eth::{MdcClkDiv, PhyMaintenance};
use super::{EthernetId, ll::EthernetLowLevel};
pub struct Mdio {
regs: zynq7000::eth::MmioEthernet<'static>,
clause22: bool,
}
impl Mdio {
pub fn new(ll: &EthernetLowLevel, clause22: bool) -> Self {
Self {
regs: unsafe { ll.regs.clone() },
clause22,
}
}
/// # Safety
///
/// Circumvents ownership and safety guarantees of the HAL.
pub unsafe fn steal(eth_id: EthernetId, clause22: bool) -> Self {
Self {
regs: unsafe { eth_id.steal_regs() },
clause22,
}
}
#[inline]
pub fn configure_clock_div(&mut self, clk_div: MdcClkDiv) {
self.regs.modify_net_cfg(|mut val| {
val.set_mdc_clk_div(clk_div);
val
});
}
pub fn read_blocking(&mut self, phy_addr: u5, reg_addr: u5) -> u16 {
self.regs.write_phy_maintenance(
PhyMaintenance::builder()
.with_clause_22(self.clause22)
.with_op(zynq7000::eth::PhyOperation::Read)
.with_phy_addr(phy_addr)
.with_reg_addr(reg_addr)
.with_must_be_0b10(u2::new(0b10))
.with_data(0x0000)
.build(),
);
while !self.regs.read_net_status().phy_mgmt_idle() {}
self.regs.read_phy_maintenance().data()
}
pub fn write_blocking(&mut self, phy_addr: u5, reg_addr: u5, data: u16) {
self.regs.write_phy_maintenance(
PhyMaintenance::builder()
.with_clause_22(self.clause22)
.with_op(zynq7000::eth::PhyOperation::Write)
.with_phy_addr(phy_addr)
.with_reg_addr(reg_addr)
.with_must_be_0b10(u2::new(0b10))
.with_data(data)
.build(),
);
while !self.regs.read_net_status().phy_mgmt_idle() {}
}
}

444
zynq7000-hal/src/eth/mod.rs Normal file
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use arbitrary_int::{u2, u3};
pub use zynq7000::eth::MdcClkDiv;
use zynq7000::eth::{
BurstLength, DmaRxBufSize, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, MmioEthernet, NetworkConfig,
SpeedMode,
};
pub use ll::{ClkConfig, EthernetLowLevel};
pub mod ll;
pub mod mdio;
pub mod rx_descr;
pub mod tx_descr;
pub const MTU: usize = 1536;
#[cfg(not(feature = "7z010-7z007s-clg225"))]
use crate::gpio::mio::{
Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
};
use crate::gpio::{
IoPeriphPin,
mio::{
Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio52,
Mio53, MioPinMarker, MuxConf, Pin,
},
};
pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0();
pub const MUX_CONF_MDIO: MuxConf = MuxConf::new_with_l3(u3::new(0b100));
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum EthernetId {
Eth0 = 0,
Eth1 = 1,
}
impl EthernetId {
/// Steal the ethernet register block for the given ethernet ID.
///
/// # Safety
///
/// Circumvents ownership and safety guarantees of the HAL.
pub const unsafe fn steal_regs(&self) -> zynq7000::eth::MmioEthernet<'static> {
unsafe {
match self {
EthernetId::Eth0 => zynq7000::eth::Ethernet::new_mmio_fixed_0(),
EthernetId::Eth1 => zynq7000::eth::Ethernet::new_mmio_fixed_1(),
}
}
}
}
pub trait PsEthernet {
fn reg_block(&self) -> MmioEthernet<'static>;
fn id(&self) -> Option<EthernetId>;
}
impl PsEthernet for MmioEthernet<'static> {
#[inline]
fn reg_block(&self) -> MmioEthernet<'static> {
unsafe { self.clone() }
}
#[inline]
fn id(&self) -> Option<EthernetId> {
let base_addr = unsafe { self.ptr() } as usize;
if base_addr == GEM_0_BASE_ADDR {
return Some(EthernetId::Eth0);
} else if base_addr == GEM_1_BASE_ADDR {
return Some(EthernetId::Eth1);
}
None
}
}
pub trait TxClk: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait TxCtrl: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait TxData0: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait TxData1: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait TxData2: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait TxData3: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxClk: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxCtrl: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxData0: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxData1: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxData2: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait RxData3: MioPinMarker {
const ETH_ID: EthernetId;
}
pub trait MdClk: MioPinMarker {}
pub trait MdIo: MioPinMarker {}
impl MdClk for Pin<Mio52> {}
impl MdIo for Pin<Mio53> {}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxClk for Pin<Mio16> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxCtrl for Pin<Mio21> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxData0 for Pin<Mio17> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxData1 for Pin<Mio18> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxData2 for Pin<Mio19> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl TxData3 for Pin<Mio20> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxClk for Pin<Mio22> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxCtrl for Pin<Mio27> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxData0 for Pin<Mio23> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxData1 for Pin<Mio24> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxData2 for Pin<Mio25> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
#[cfg(not(feature = "7z010-7z007s-clg225"))]
impl RxData3 for Pin<Mio26> {
const ETH_ID: EthernetId = EthernetId::Eth0;
}
impl TxClk for Pin<Mio28> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl TxCtrl for Pin<Mio33> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl TxData0 for Pin<Mio29> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl TxData1 for Pin<Mio30> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl TxData2 for Pin<Mio31> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl TxData3 for Pin<Mio32> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxClk for Pin<Mio34> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxCtrl for Pin<Mio39> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxData0 for Pin<Mio35> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxData1 for Pin<Mio36> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxData2 for Pin<Mio37> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
impl RxData3 for Pin<Mio38> {
const ETH_ID: EthernetId = EthernetId::Eth1;
}
#[derive(Debug, Clone, Copy)]
pub struct EthernetConfig {
pub clk_config: ClkConfig,
pub mdc_clk_div: MdcClkDiv,
pub mac_address: [u8; 6],
}
impl EthernetConfig {
pub fn new(clk_config: ClkConfig, mdc_clk_div: MdcClkDiv, mac_address: [u8; 6]) -> Self {
Self {
clk_config,
mdc_clk_div,
mac_address,
}
}
}
pub struct Ethernet {
ll: ll::EthernetLowLevel,
mdio: mdio::Mdio,
}
impl Ethernet {
#[allow(clippy::too_many_arguments)]
pub fn new_with_mio<
TxClkPin: TxClk,
TxCtrlPin: TxCtrl,
TxData0Pin: TxData0,
TxData1Pin: TxData1,
TxData2Pin: TxData2,
TxData3Pin: TxData3,
RxClkPin: RxClk,
RxCtrlPin: RxCtrl,
RxData0Pin: RxData0,
RxData1Pin: RxData1,
RxData2Pin: RxData2,
RxData3Pin: RxData3,
MdClkPin: MdClk,
MdIoPin: MdIo,
>(
mut ll: ll::EthernetLowLevel,
config: EthernetConfig,
tx_clk: TxClkPin,
tx_ctrl: TxCtrlPin,
tx_data: (TxData0Pin, TxData1Pin, TxData2Pin, TxData3Pin),
rx_clk: RxClkPin,
rx_ctrl: RxCtrlPin,
rx_data: (RxData0Pin, RxData1Pin, RxData2Pin, RxData3Pin),
md_pins: Option<(MdClkPin, MdIoPin)>,
) -> Self {
Self::common_init(&mut ll, config.mac_address);
let tx_mio_config = zynq7000::slcr::mio::Config::builder()
.with_disable_hstl_rcvr(true)
.with_pullup(true)
.with_io_type(zynq7000::slcr::mio::IoType::Hstl)
.with_speed(zynq7000::slcr::mio::Speed::FastCmosEdge)
.with_l3_sel(MUX_CONF_PHY.l3_sel())
.with_l2_sel(MUX_CONF_PHY.l2_sel())
.with_l1_sel(MUX_CONF_PHY.l1_sel())
.with_l0_sel(MUX_CONF_PHY.l0_sel())
.with_tri_enable(false)
.build();
let rx_mio_config = zynq7000::slcr::mio::Config::builder()
.with_disable_hstl_rcvr(false)
.with_pullup(true)
.with_io_type(zynq7000::slcr::mio::IoType::Hstl)
.with_speed(zynq7000::slcr::mio::Speed::FastCmosEdge)
.with_l3_sel(MUX_CONF_PHY.l3_sel())
.with_l2_sel(MUX_CONF_PHY.l2_sel())
.with_l1_sel(MUX_CONF_PHY.l1_sel())
.with_l0_sel(MUX_CONF_PHY.l0_sel())
// Disable output driver.
.with_tri_enable(true)
.build();
unsafe {
crate::slcr::Slcr::with(|slcr_mut| {
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_clk,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_ctrl,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_data.0,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_data.1,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_data.2,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
tx_data.3,
slcr_mut,
tx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_clk,
slcr_mut,
rx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_ctrl,
slcr_mut,
rx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_data.0,
slcr_mut,
rx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_data.1,
slcr_mut,
rx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_data.2,
slcr_mut,
rx_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
rx_data.3,
slcr_mut,
rx_mio_config,
);
if let Some((md_clk, md_io)) = md_pins {
let md_mio_config = zynq7000::slcr::mio::Config::builder()
.with_disable_hstl_rcvr(false)
.with_pullup(true)
.with_io_type(zynq7000::slcr::mio::IoType::LvCmos18)
.with_speed(zynq7000::slcr::mio::Speed::SlowCmosEdge)
.with_l3_sel(MUX_CONF_MDIO.l3_sel())
.with_l2_sel(MUX_CONF_MDIO.l2_sel())
.with_l1_sel(MUX_CONF_MDIO.l1_sel())
.with_l0_sel(MUX_CONF_MDIO.l0_sel())
.with_tri_enable(false)
.build();
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
md_clk,
slcr_mut,
md_mio_config,
);
IoPeriphPin::new_with_full_config_and_unlocked_slcr(
md_io,
slcr_mut,
md_mio_config,
);
}
// Enable VREF internal generator, which is required for HSTL pin mode.
slcr_mut.gpiob().modify_ctrl(|mut ctrl| {
ctrl.set_vref_en(true);
ctrl
});
});
}
ll.configure_clock(config.clk_config);
let mut mdio = mdio::Mdio::new(&ll, true);
mdio.configure_clock_div(config.mdc_clk_div);
Ethernet { ll, mdio }
}
pub fn new(mut ll: EthernetLowLevel, config: EthernetConfig) -> Self {
Self::common_init(&mut ll, config.mac_address);
ll.configure_clock(config.clk_config);
let mut mdio = mdio::Mdio::new(&ll, true);
mdio.configure_clock_div(config.mdc_clk_div);
Ethernet { ll, mdio }
}
fn common_init(ll: &mut EthernetLowLevel, mac_address: [u8; 6]) {
ll.enable_peripheral_clock();
ll.reset(3);
ll.initialize();
// By default, only modify critical network control bits to retain user configuration
// like the MDC clock divisor.
ll.regs.modify_net_cfg(|mut net_cfg| {
net_cfg.set_full_duplex(true);
net_cfg.set_gigabit_enable(true);
net_cfg.set_speed_mode(SpeedMode::High100Mbps);
net_cfg
});
let macaddr_msbs = (u32::from(mac_address[5]) << 8) | u32::from(mac_address[4]);
let macaddr_lsbs = (u32::from(mac_address[3]) << 24)
| (u32::from(mac_address[2]) << 16)
| (u32::from(mac_address[1]) << 8)
| u32::from(mac_address[0]);
// Writing to the lower address portion disables the address match, writing to the higher
// portion enables it again. Address matching is disabled on reset, so we do not need
// to disable the other addresses here.
ll.regs.write_addr1_low(macaddr_lsbs);
ll.regs.write_addr1_high(macaddr_msbs);
// TODO
ll.regs.modify_dma_cfg(|mut val| {
val.set_rx_packet_buf_size_sel(u2::new(0b11));
val.set_tx_packet_buf_size_sel(true);
val.set_burst_length(BurstLength::Incr16.reg_value());
// Configure 1536 bytes receive buffer size. This is sufficient for regular Ethernet
// frames.
val.set_dma_rx_ahb_buf_size_sel(DmaRxBufSize::new((MTU >> 6) as u8).unwrap());
val.set_endian_swap_mgmt_descriptor(zynq7000::eth::AhbEndianess::Little);
val
});
}
#[inline]
pub fn ll(&mut self) -> &mut EthernetLowLevel {
&mut self.ll
}
#[inline]
pub fn regs(&mut self) -> &MmioEthernet<'static> {
&self.ll.regs
}
#[inline]
pub fn regs_mut(&mut self) -> &mut MmioEthernet<'static> {
&mut self.ll.regs
}
}
mod shared {
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum Ownership {
Hardware = 0,
Software = 1,
}
}

137
zynq7000-hal/src/eth/rx_descr.rs Normal file
View File

@ -0,0 +1,137 @@
//! RX buffer descriptor module.
pub use super::shared::Ownership;
use arbitrary_int::{u2, u3, u13, u30};
/// RX buffer descriptor.
///
/// The user should declare an array of this structure inside uncached memory.
///
/// These descriptors are shared between software and hardware and contain information
/// related to frame reception.
#[repr(C)]
pub struct Descriptor {
/// The first word of the descriptor.
pub word0: Word0,
/// The second word of the descriptor.
pub word1: Word1,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug, PartialEq, Eq)]
pub struct Word0 {
/// The full reception address with the last two bits cleared.
#[bits(2..=31, rw)]
addr_upper_30_bits: u30,
#[bit(1, rw)]
wrap: bool,
#[bit(0, rw)]
ownership: Ownership,
}
/// This control word contains the status bits.
///
/// If the end of frame bit (15) is not set, the only valid status information is the start of
/// frame bit.
#[bitbybit::bitfield(u32)]
#[derive(Debug, PartialEq, Eq)]
pub struct Word1 {
#[bit(31, r)]
broadcast_detect: bool,
#[bit(30, r)]
multicast_hash: bool,
#[bit(29, r)]
unicast_hash: bool,
#[bit(27, r)]
specific_addr_match: bool,
/// Specifies which of the 4 specific address registers was matched.
#[bits(25..=26, r)]
specific_addr_match_info: u2,
#[bit(24, r)]
type_id_match_or_snap_info: bool,
#[bits(22..=23, r)]
type_id_match_info_or_chksum_status: u2,
#[bit(21, r)]
vlan_tag_detected: bool,
#[bit(20, r)]
priority_tag_detected: bool,
#[bits(17..=19, r)]
vlan_prio: u3,
#[bit(16, r)]
cfi_bit: bool,
/// If this bit is not set, the only other valid status bit is the start of frame bit.
#[bit(15, r)]
end_of_frame: bool,
#[bit(14, r)]
start_of_frame: bool,
/// Relevant when FCS errors are not ignored.
/// 0: Frame has good FCS, 1: Frame has bad FCS, but was copied to memory as the ignore FCS
/// functionality was enabled.
#[bit(13, r)]
fcs_status: bool,
#[bits(0..=12, r)]
rx_len: u13,
}
impl Descriptor {
#[inline]
pub const fn new() -> Self {
Self {
word0: Word0::new_with_raw_value(0),
word1: Word1::new_with_raw_value(0),
}
}
#[inline]
pub fn set_ownership(&mut self, ownership: Ownership) {
self.word0.set_ownership(ownership);
}
#[inline]
pub fn set_wrap_bit(&mut self) {
self.word0.set_wrap(true);
}
#[inline]
pub fn write_rx_addr(&mut self, addr: u32) {
self.word0.set_addr_upper_30_bits(u30::new(addr >> 2));
}
}
impl Default for Descriptor {
#[inline]
fn default() -> Self {
Self::new()
}
}
pub struct DescriptorListRef<'a>(&'a mut [Descriptor]);
impl<'a> DescriptorListRef<'a> {
#[inline]
pub fn new(descriptor: &'a mut [Descriptor]) -> Self {
Self(descriptor)
}
}
impl DescriptorListRef<'_> {
#[inline]
pub fn base_ptr(&self) -> *const Descriptor {
self.0.as_ptr()
}
#[inline]
pub fn base_addr(&self) -> u32 {
self.base_ptr() as u32
}
pub fn init(&mut self) {
for desc in self.0.iter_mut() {
desc.set_ownership(Ownership::Hardware);
}
self.0.last_mut().unwrap().set_wrap_bit();
}
pub fn set_rx_buf_address(&mut self, index: usize, addr: u32) {
self.0[index].write_rx_addr(addr);
}
}

121
zynq7000-hal/src/eth/tx_descr.rs Normal file
View File

@ -0,0 +1,121 @@
use arbitrary_int::u14;
pub use super::shared::Ownership;
/// TX buffer descriptor.
///
/// The user should declare an array of this structure inside uncached memory.
///
/// These descriptors are shared between software and hardware and contain information
/// related to frame reception.
#[repr(C)]
pub struct Descriptor {
/// The first word of the descriptor which is the byte address of the buffer.
pub word0: u32,
/// The second word of the descriptor.
pub word1: Word1,
}
#[bitbybit::bitenum(u3, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum TransmitChecksumGenerationStatus {
NoError = 0b000,
VlanError = 0b001,
SnapError = 0b010,
IpError = 0b011,
NotVlanOrSnapOrIp = 0b100,
NonSupportedPacketFragmentation = 0b101,
PacketNotTcpUdp = 0b110,
PrematureEndOfFrame = 0b111,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug, PartialEq, Eq)]
pub struct Word1 {
#[bit(31, rw)]
ownership: Ownership,
#[bit(30, rw)]
wrap: bool,
#[bit(29, rw)]
retry_limit_exceeded: bool,
#[bit(27, rw)]
transmit_frame_corruption_ahb_error: bool,
#[bit(26, rw)]
late_collision: bool,
#[bits(20..=22, rw)]
checksum_status: TransmitChecksumGenerationStatus,
#[bit(16, rw)]
no_crc_generation: bool,
#[bit(15, rw)]
last_buffer: bool,
#[bits(0..=13, rw)]
tx_len: u14,
}
impl Descriptor {
#[inline]
pub const fn new() -> Self {
Self {
word0: 0,
word1: Word1::new_with_raw_value(0),
}
}
#[inline]
pub fn set_ownership(&mut self, ownership: Ownership) {
self.word1.set_ownership(ownership);
}
/// Set the wrap bit, which should be done for the last descriptor in the descriptor list.
#[inline]
pub fn set_wrap_bit(&mut self) {
self.word1.set_wrap(true);
}
/// Set the information for a transfer.
pub fn set_tx_transfer_info(
&mut self,
tx_len: u14,
last_buffer: bool,
no_crc_generation: bool,
) {
self.word1.set_tx_len(tx_len);
self.word1.set_last_buffer(last_buffer);
self.word1.set_no_crc_generation(no_crc_generation);
}
}
impl Default for Descriptor {
#[inline]
fn default() -> Self {
Self::new()
}
}
pub struct DescriptorListRef<'a>(&'a mut [Descriptor]);
impl<'a> DescriptorListRef<'a> {
#[inline]
pub fn new(descriptor: &'a mut [Descriptor]) -> Self {
Self(descriptor)
}
}
impl DescriptorListRef<'_> {
#[inline]
pub fn base_ptr(&self) -> *const Descriptor {
self.0.as_ptr()
}
#[inline]
pub fn base_addr(&self) -> u32 {
self.base_ptr() as u32
}
pub fn init(&mut self) {
for desc in self.0.iter_mut() {
desc.set_ownership(Ownership::Hardware);
}
self.0.last_mut().unwrap().set_wrap_bit();
}
}

19
zynq7000-hal/src/gpio/ll.rs
View File

@ -4,7 +4,7 @@ use zynq7000::gpio::{Gpio, MaskedOutput, MmioGpio};
use crate::slcr::Slcr;
use super::{mio::MuxConf, PinIsOutputOnly};
use super::{PinIsOutputOnly, mio::MuxConf};
#[derive(Debug, Clone, Copy)]
pub enum PinOffset {
@ -148,6 +148,23 @@ impl LowLevelGpio {
self.reconfigure_slcr_mio_cfg(false, pullup, Some(mux_conf));
}
pub fn set_mio_pin_config(&mut self, config: zynq7000::slcr::mio::Config) {
let raw_offset = self.offset.offset();
// Safety: We only modify the MIO config of the pin.
let mut slcr_wrapper = unsafe { Slcr::steal() };
slcr_wrapper.modify(|mut_slcr| mut_slcr.write_mio_pins(raw_offset, config).unwrap());
}
/// Set the MIO pin configuration with an unlocked SLCR.
pub fn set_mio_pin_config_with_unlocked_slcr(
&mut self,
slcr: &mut zynq7000::slcr::MmioSlcr<'static>,
config: zynq7000::slcr::mio::Config,
) {
let raw_offset = self.offset.offset();
slcr.write_mio_pins(raw_offset, config).unwrap();
}
#[inline]
pub fn is_low(&self) -> bool {
let (offset, in_reg) = self.get_data_in_reg_and_local_offset();

4
zynq7000-hal/src/gpio/mio.rs
View File

@ -31,6 +31,10 @@ impl MuxConf {
Self { l3, l2, l1, l0 }
}
pub const fn new_with_l0() -> Self {
Self::new(true, false, u2::new(0b00), u3::new(0b000))
}
pub const fn new_with_l3(l3: u3) -> Self {
Self::new(false, false, u2::new(0b00), l3)
}

42
zynq7000-hal/src/gpio/mod.rs
View File

@ -172,7 +172,8 @@ impl Flex {
pub fn configure_as_output_open_drain(&mut self, level: PinState, with_internal_pullup: bool) {
self.mode = PinMode::OutputOpenDrain;
self.ll.configure_as_output_open_drain(level, with_internal_pullup);
self.ll
.configure_as_output_open_drain(level, with_internal_pullup);
}
/// If the pin is configured as an input pin, this function does nothing.
@ -383,6 +384,8 @@ pub struct IoPeriphPin {
}
impl IoPeriphPin {
/// Constructor for IO peripheral pins where only the multiplexer and pullup configuration
/// need to be changed.
pub fn new(pin: impl MioPinMarker, mux_conf: MuxConf, pullup: Option<bool>) -> Self {
let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
low_level.configure_as_io_periph_pin(mux_conf, pullup);
@ -391,6 +394,43 @@ impl IoPeriphPin {
mux_conf,
}
}
/// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
pub fn new_with_full_config(
pin: impl MioPinMarker,
config: zynq7000::slcr::mio::Config,
) -> Self {
let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
low_level.set_mio_pin_config(config);
Self {
pin: low_level,
mux_conf: MuxConf::new(
config.l0_sel(),
config.l1_sel(),
config.l2_sel(),
config.l3_sel(),
),
}
}
/// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
pub fn new_with_full_config_and_unlocked_slcr(
pin: impl MioPinMarker,
slcr: &mut zynq7000::slcr::MmioSlcr<'static>,
config: zynq7000::slcr::mio::Config,
) -> Self {
let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
low_level.set_mio_pin_config_with_unlocked_slcr(slcr, config);
Self {
pin: low_level,
mux_conf: MuxConf::new(
config.l0_sel(),
config.l1_sel(),
config.l2_sel(),
config.l3_sel(),
),
}
}
}
impl IoPinProvider for IoPeriphPin {

2
zynq7000-hal/src/lib.rs
View File

@ -12,7 +12,9 @@
use slcr::Slcr;
use zynq7000::slcr::LevelShifterReg;
pub mod cache;
pub mod clocks;
pub mod eth;
pub mod gic;
pub mod gpio;
pub mod gtc;

2
zynq7000-hal/src/slcr.rs
View File

@ -14,7 +14,7 @@ impl Slcr {
/// This method unsafely steals the SLCR MMIO block and then calls a user provided function
/// with the [SLCR MMIO][MmioSlcr] block as an input argument. It is the user's responsibility
/// that the SLCR is not used concurrently in a way which leads to data races.
pub unsafe fn with<F: FnMut(&mut MmioSlcr)>(mut f: F) {
pub unsafe fn with<F: FnOnce(&mut MmioSlcr<'static>)>(f: F) {
let mut slcr = unsafe { zynq7000::slcr::Slcr::new_mmio_fixed() };
slcr.write_unlock(UNLOCK_KEY);
f(&mut slcr);

7
zynq7000-rt/Cargo.toml
View File

@ -11,8 +11,11 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-a-rt = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", optional = true, features = ["vfp-dp"] }
cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
# cortex-ar = "0.2"
cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
arbitrary-int = "1.3"
zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
[features]
default = ["rt"]

124
zynq7000-rt/src/bin/table-gen.rs
View File

@ -4,6 +4,17 @@ use std::process::Command;
use zynq7000_rt::mmu::ONE_MB;
pub use zynq7000_rt::mmu::segments::*;
macro_rules! write_l1_section {
($writer:expr, $offset:expr, $attr:expr) => {
writeln!(
$writer,
"L1Section::new({:#010x}, {}).raw_value(),",
$offset, $attr
)
.unwrap();
};
}
fn main() {
let file_path = "src/mmu_table.rs";
let file = File::create(file_path).expect("Failed to create file");
@ -35,6 +46,7 @@ fn main() {
+ OCM_MAPPED_HIGH,
4096
);
let mut buf_writer = std::io::BufWriter::new(file);
writeln!(
buf_writer,
@ -63,44 +75,24 @@ fn main() {
"// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
)
.unwrap();
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_ddr
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_ddr);
offset += ONE_MB;
writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
for _ in 0..DDR_FULL_ACCESSIBLE {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_ddr
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_ddr);
offset += ONE_MB;
}
writeln!(buf_writer, "// FPGA slave 0 (0x4000_0000 - 0x8000_0000)").unwrap();
for _ in 0..FPGA_SLAVE {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_fpga_slaves
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_fpga_slaves);
offset += ONE_MB;
}
writeln!(buf_writer, "// FPGA slave 1 (0x8000_0000 - 0xC000_0000)").unwrap();
for _ in 0..FPGA_SLAVE {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_fpga_slaves
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_fpga_slaves);
offset += ONE_MB;
}
@ -110,12 +102,7 @@ fn main() {
)
.unwrap();
for _ in 0..UNASSIGNED_0 {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_unassigned
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_unassigned);
offset += ONE_MB;
}
@ -125,12 +112,7 @@ fn main() {
)
.unwrap();
for _ in 0..IO_PERIPHS {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_shared_dev
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_shared_dev);
offset += ONE_MB;
}
@ -140,45 +122,25 @@ fn main() {
)
.unwrap();
for _ in 0..UNASSIGNED_1 {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_unassigned
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_unassigned);
offset += ONE_MB;
}
writeln!(buf_writer, "// NAND (0xE100_0000 - 0xE200_0000)").unwrap();
for _ in 0..NAND {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_shared_dev
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_shared_dev);
offset += ONE_MB;
}
writeln!(buf_writer, "// NOR (0xE200_0000 - 0xE400_0000)").unwrap();
for _ in 0..NOR {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_shared_dev
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_shared_dev);
offset += ONE_MB;
}
writeln!(buf_writer, "// SRAM (0xE400_0000 - 0xE600_0000)").unwrap();
for _ in 0..SRAM {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_sram
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_sram);
offset += ONE_MB;
}
@ -188,12 +150,7 @@ fn main() {
)
.unwrap();
for _ in 0..SEGMENTS_UNASSIGNED_2 {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_unassigned
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_unassigned);
offset += ONE_MB;
}
@ -203,12 +160,7 @@ fn main() {
)
.unwrap();
for _ in 0..AMBA_APB {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_shared_dev
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_shared_dev);
offset += ONE_MB;
}
@ -218,23 +170,13 @@ fn main() {
)
.unwrap();
for _ in 0..UNASSIGNED_3 {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_unassigned
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_unassigned);
offset += ONE_MB;
}
writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
for _ in 0..QSPI_XIP {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_qspi
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_qspi);
offset += ONE_MB;
}
@ -244,24 +186,14 @@ fn main() {
)
.unwrap();
for _ in 0..UNASSIGNED_4 {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_unassigned
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_unassigned);
offset += ONE_MB;
}
writeln!(buf_writer, "// OCM High (0xFFF0_0000 - 0xFFFF_FFFF)").unwrap();
let mut offset_u64 = offset as u64;
for _ in 0..OCM_MAPPED_HIGH {
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_ocm_high
)
.unwrap();
write_l1_section!(buf_writer, offset, attr_ocm_high);
offset_u64 += ONE_MB as u64;
}

8
zynq7000-rt/src/lib.rs
View File

@ -4,8 +4,16 @@
//! [provided by Xilinx](https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/cortexa9/gcc).
#![no_std]
use zynq_mmu::L1TableRef;
pub mod mmu;
#[cfg(feature = "rt")]
mod mmu_table;
#[cfg(feature = "rt")]
pub mod rt;
/// Retrieves a mutable reference to the MMU L1 page table.
pub fn mmu_l1_table_mut() -> L1TableRef<'static> {
// Safety: We retrieve a reference to the MMU page table singleton.
L1TableRef::new(unsafe { &mut *mmu_table::MMU_L1_PAGE_TABLE.get() })
}

28
zynq7000-rt/src/mmu.rs
View File

@ -84,17 +84,23 @@ pub mod segments {
}
pub mod section_attrs {
use arbitrary_int::u4;
use cortex_ar::mmu::{
AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
};
pub const DEFAULT_DOMAIN: u4 = u4::new(0b0000);
// DDR is in different domain, but all domains are set as manager domains during run-time
// initialization.
pub const DDR_DOMAIN: u4 = u4::new(0b1111);
pub const DDR: SectionAttributes = SectionAttributes {
non_global: false,
p_bit: false,
shareable: true,
access: AccessPermissions::FullAccess,
// Manager domain
domain: 0b1111,
domain: DDR_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::CacheableMemory {
inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
@ -107,7 +113,7 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::FullAccess,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
};
@ -116,7 +122,7 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::FullAccess,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::ShareableDevice.as_raw(),
};
@ -125,7 +131,7 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::FullAccess,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::OuterAndInnerWriteBackNoWriteAlloc.as_raw(),
};
@ -134,7 +140,7 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::FullAccess,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::OuterAndInnerWriteThroughNoWriteAlloc.as_raw(),
};
@ -143,7 +149,7 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::FullAccess,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::CacheableMemory {
inner: CacheableMemoryAttribute::WriteThroughNoWriteAlloc,
@ -156,18 +162,12 @@ pub mod section_attrs {
p_bit: false,
shareable: false,
access: AccessPermissions::PermissionFault,
domain: 0b0000,
domain: DEFAULT_DOMAIN,
execute_never: false,
memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
};
}
pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
#[repr(C, align(16384))]
#[cfg(feature = "rt")]
pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
/// Load the MMU translation table base address into the MMU.
///
/// # Safety
@ -178,7 +178,7 @@ pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
#[unsafe(no_mangle)]
#[cfg(feature = "rt")]
unsafe extern "C" fn load_mmu_table() {
let table_base = &crate::mmu_table::MMU_L1_PAGE_TABLE.0 as *const _ as u32;
let table_base = crate::mmu_table::MMU_L1_PAGE_TABLE.get() as u32;
unsafe {
core::arch::asm!(

8201
zynq7000-rt/src/mmu_table.rs
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File diff suppressed because it is too large Load Diff

2
zynq7000/Cargo.toml
View File

@ -12,7 +12,7 @@ categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
static_assertions = "1.1"
derive-mmio = { git = "https://github.com/us-irs/derive-mmio", branch = "inner-mmio-by-shared-ref", default-features = false }
derive-mmio = { git = "https://github.com/us-irs/derive-mmio", branch = "main", default-features = false }
bitbybit = "1.3"
arbitrary-int = "1.3"
rustversion = "1"

599
zynq7000/src/eth.rs Normal file
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@ -0,0 +1,599 @@
use arbitrary_int::{u2, u5};
pub const GEM_0_BASE_ADDR: usize = 0xE000_B000;
pub const GEM_1_BASE_ADDR: usize = 0xE000_C000;
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct NetworkControl {
#[bit(18, w)]
flush_next_rx_dpram_pkt: bool,
#[bit(17, w)]
tx_pfc_pri_pause_frame: bool,
#[bit(16, w)]
enable_pfc_pri_pause_rx: bool,
#[bit(12, w)]
zero_pause_tx: bool,
#[bit(11, w)]
pause_tx: bool,
#[bit(10, w)]
stop_tx: bool,
#[bit(9, w)]
start_tx: bool,
#[bit(8, rw)]
back_pressure: bool,
#[bit(7, rw)]
statistics_write_enable: bool,
#[bit(6, w)]
increment_statistics: bool,
#[bit(5, w)]
clear_statistics: bool,
#[bit(4, rw)]
management_port_enable: bool,
#[bit(3, rw)]
tx_enable: bool,
#[bit(2, rw)]
rx_enable: bool,
#[bit(1, rw)]
loopback_local: bool,
}
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum SpeedMode {
Low10Mbps = 0,
High100Mbps = 1,
}
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum PcsSelect {
GmiiMii = 0,
Tbi = 1,
}
#[bitbybit::bitenum(u3, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum MdcClkDiv {
Div8 = 0,
Div16 = 1,
Div32 = 2,
Div48 = 3,
Div64 = 4,
Div96 = 5,
Div128 = 6,
Div224 = 7,
}
impl MdcClkDiv {
pub fn divisor(&self) -> usize {
match self {
MdcClkDiv::Div8 => 8,
MdcClkDiv::Div16 => 16,
MdcClkDiv::Div32 => 32,
MdcClkDiv::Div48 => 48,
MdcClkDiv::Div64 => 64,
MdcClkDiv::Div96 => 96,
MdcClkDiv::Div128 => 128,
MdcClkDiv::Div224 => 224,
}
}
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
pub struct NetworkConfig {
#[bit(30, rw)]
ignore_ipg_rx_error: bool,
#[bit(29, rw)]
allow_bad_preamble: bool,
#[bit(28, rw)]
ipg_stretch_enable: bool,
#[bit(27, rw)]
sgmii_enable: bool,
#[bit(26, rw)]
ignore_rx_fcs: bool,
#[bit(25, rw)]
half_duplex_rx_enable: bool,
#[bit(24, rw)]
rx_checksum_enable: bool,
#[bit(23, rw)]
disable_copy_pause_frames: bool,
/// Zynq defines this as 0b00 for 32-bit AMBA AHB data bus width.
#[bits(21..=22, r)]
dbus_width: u2,
#[bits(18..=20, rw)]
mdc_clk_div: MdcClkDiv,
#[bit(17, rw)]
fcs_removal: bool,
#[bit(16, rw)]
length_field_error_discard: bool,
#[bits(14..=15, rw)]
rx_buf_offset: u2,
#[bit(13, rw)]
pause_enable: bool,
#[bit(12, rw)]
retry_test_enable: bool,
#[bit(11, rw)]
pcs_select: PcsSelect,
#[bit(10, rw)]
gigabit_enable: bool,
#[bit(9, rw)]
ext_addr_match_enable: bool,
#[bit(8, rw)]
rx_enable_1536: bool,
#[bit(7, rw)]
unicast_hash_enable: bool,
#[bit(6, rw)]
multicast_hash_enable: bool,
#[bit(5, rw)]
no_broadcast: bool,
#[bit(4, rw)]
copy_all_frames: bool,
#[bit(2, rw)]
discard_non_vlan: bool,
#[bit(1, rw)]
full_duplex: bool,
#[bit(0, rw)]
speed_mode: SpeedMode,
}
/// PHY management status information.
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct NetworkStatus {
#[bit(6, r)]
pfc_pri_pause_neg: bool,
#[bit(5, r)]
pcs_autoneg_pause_tx_res: bool,
#[bit(4, r)]
pcs_autoneg_pause_rx_res: bool,
#[bit(3, r)]
pcs_autoneg_dup_res: bool,
#[bit(2, r)]
phy_mgmt_idle: bool,
#[bit(1, r)]
mdio_in: bool,
#[bit(0, r)]
pcs_link_state: bool,
}
#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)]
pub enum BurstLength {
Single,
#[default]
Incr4,
Incr8,
Incr16,
}
impl BurstLength {
pub const fn reg_value(&self) -> u5 {
u5::new(match self {
BurstLength::Single => 0b1,
BurstLength::Incr4 => 0b100,
BurstLength::Incr8 => 0b1000,
BurstLength::Incr16 => 0b10000,
})
}
}
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug, PartialEq, Eq)]
pub enum AhbEndianess {
Little = 0,
Big = 1,
}
#[derive(Debug, PartialEq, Eq)]
pub struct DmaRxBufSize(u8);
impl DmaRxBufSize {
pub const fn new_with_raw_value(size: u8) -> Self {
Self(size)
}
pub const fn new(size: u8) -> Option<Self> {
if size == 0 {
return None;
}
Some(Self(size))
}
pub const fn raw_value(&self) -> u8 {
self.0
}
pub const fn size_in_bytes(&self) -> usize {
self.0 as usize * 64
}
pub const fn reg_value(&self) -> u8 {
self.0
}
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct DmaConfig {
#[bit(24, rw)]
discard_when_ahb_full: bool,
/// DMA receive buffer size in AHB system memory.
#[bits(16..=23, rw)]
dma_rx_ahb_buf_size_sel: DmaRxBufSize,
#[bit(11, rw)]
chksum_offload_enable: bool,
/// Select size for packet buffer SRAM. Should be set to 1 to use the full configurable address
/// space of 4 kB for the packet buffer.
#[bit(10, rw)]
tx_packet_buf_size_sel: bool,
/// Select size for packet buffer SRAM. Should be set to 0b11 to use the full configurable
/// address space of 8 kB for the packet buffer.
#[bits(8..=9, rw)]
rx_packet_buf_size_sel: u2,
/// Default value is 0x1 (big endian)
#[bit(7, rw)]
endian_swap_packet_data: AhbEndianess,
// Default value is 0x0 (little endian)
#[bit(6, rw)]
endian_swap_mgmt_descriptor: AhbEndianess,
#[bits(0..=4, rw)]
burst_length: u5,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct TxStatus {
#[bit(8, rw)]
hresp_not_ok: bool,
#[bit(7, rw)]
late_collision: bool,
#[bit(6, rw)]
tx_underrun: bool,
#[bit(5, rw)]
tx_complete: bool,
#[bit(4, rw)]
tx_frame_corruption_ahb_error: bool,
#[bit(3, r)]
tx_go: bool,
#[bit(2, rw)]
retry_limit_reached: bool,
#[bit(1, rw)]
collision: bool,
#[bit(0, rw)]
read_when_used: bool,
}
impl TxStatus {
pub fn new_clear_all() -> Self {
Self::new_with_raw_value(0xFF)
}
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct RxStatus {
#[bit(3, rw)]
hresp_not_ok: bool,
#[bit(2, rw)]
rx_overrun: bool,
#[bit(1, rw)]
frame_received: bool,
#[bit(0, rw)]
buf_not_available: bool,
}
impl RxStatus {
pub fn new_clear_all() -> Self {
Self::new_with_raw_value(0xF)
}
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct InterruptStatus {
#[bit(26, rw)]
tsu_sec_incr: bool,
/// Marked N/A in datasheet.
#[bit(17, rw)]
partner_pg_rx: bool,
/// Marked N/A in datasheet.
#[bit(16, rw)]
auto_negotiation_complete: bool,
#[bit(15, rw)]
external_interrupt: bool,
#[bit(14, rw)]
pause_transmitted: bool,
#[bit(13, rw)]
pause_time_zero: bool,
#[bit(12, rw)]
pause_with_non_zero_quantum: bool,
#[bit(11, rw)]
hresp_not_ok: bool,
#[bit(10, rw)]
rx_overrun: bool,
/// Marked N/A in datasheet.
#[bit(9, rw)]
link_changed: bool,
#[bit(7, r)]
tx_complete: bool,
/// Cleared on read.
#[bit(6, r)]
tx_frame_corruption_ahb_error: bool,
#[bit(5, rw)]
retry_limit_reached: bool,
#[bit(3, rw)]
tx_descr_read_when_used: bool,
#[bit(2, rw)]
rx_descr_read_when_used: bool,
#[bit(1, rw)]
frame_received: bool,
#[bit(0, rw)]
mgmt_frame_sent: bool,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct InterruptControl {
#[bit(26, w)]
tsu_sec_incr: bool,
/// Marked N/A in datasheet.
#[bit(17, w)]
partner_pg_rx: bool,
/// Marked N/A in datasheet.
#[bit(16, w)]
auto_negotiation_complete: bool,
#[bit(15, w)]
external_interrupt: bool,
#[bit(14, w)]
pause_transmitted: bool,
#[bit(13, w)]
pause_time_zero: bool,
#[bit(12, w)]
pause_with_non_zero_quantum: bool,
#[bit(11, w)]
hresp_not_ok: bool,
#[bit(10, w)]
rx_overrun: bool,
/// Marked N/A in datasheet.
#[bit(9, w)]
link_changed: bool,
#[bit(7, w)]
tx_complete: bool,
/// Cleared on read.
#[bit(6, w)]
tx_frame_corruption_ahb_error: bool,
#[bit(5, w)]
retry_limit_reached: bool,
#[bit(3, w)]
tx_descr_read_when_used: bool,
#[bit(2, w)]
rx_descr_read_when_used: bool,
#[bit(1, w)]
frame_received: bool,
#[bit(0, w)]
mgmt_frame_sent: bool,
}
impl InterruptControl {
pub fn new_clear_all() -> Self {
Self::new_with_raw_value(0xFFFF_FFFF)
}
}
#[bitbybit::bitenum(u2, exhaustive = false)]
pub enum PhyOperation {
Read = 0b10,
Write = 0b01,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
pub struct PhyMaintenance {
/// Must be 1 for Clause 22 operations.
#[bit(30, rw)]
clause_22: bool,
#[bits(28..=29, rw)]
op: Option<PhyOperation>,
#[bits(23..=27, rw)]
phy_addr: u5,
#[bits(18..=22, rw)]
reg_addr: u5,
#[bits(16..=17, rw)]
must_be_0b10: u2,
#[bits(0..=15, rw)]
data: u16,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct PauseQuantum {
#[bits(0..=15, rw)]
value: u16,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct MatchRegister {
#[bit(31, rw)]
copy_enable: bool,
#[bits(0..=15, rw)]
type_id: u16,
}
/// Gigabit Ethernet Controller (GEM) registers for Zynq-7000
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct Ethernet {
net_ctrl: NetworkControl,
net_cfg: NetworkConfig,
#[mmio(PureRead)]
net_status: NetworkStatus,
_reserved0: u32,
dma_cfg: DmaConfig,
tx_status: TxStatus,
rx_buf_queue_base_addr: u32,
tx_buf_queue_base_addr: u32,
rx_status: RxStatus,
interrupt_status: InterruptStatus,
interrupt_enable: InterruptControl,
interrupt_disable: InterruptControl,
interrupt_mask: InterruptStatus,
phy_maintenance: PhyMaintenance,
#[mmio(PureRead)]
rx_pause_quantum: PauseQuantum,
tx_pause_quantum: PauseQuantum,
_reserved1: [u32; 0x10],
hash_low: u32,
hash_high: u32,
addr1_low: u32,
addr1_high: u32,
addr2_low: u32,
addr2_high: u32,
addr3_low: u32,
addr3_high: u32,
addr4_low: u32,
addr4_high: u32,
match_reg: [MatchRegister; 4],
wake_on_lan: u32,
ipg_stretch: u32,
stacked_vlan: u32,
tx_pfc: u32,
addr1_mask_low: u32,
addr1_mask_high: u32,
_reserved2: [u32; 0x0B],
/// Should be 0x20118.
#[mmio(PureRead)]
module_id: u32,
#[mmio(inner)]
statistics: Statistics,
_reserved3: [u32; 0x34],
#[mmio(PureRead)]
design_cfg_2: u32,
#[mmio(PureRead)]
design_cfg_3: u32,
#[mmio(PureRead)]
design_cfg_4: u32,
#[mmio(PureRead)]
design_cfg_5: u32,
}
static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
/// GEM statistics registers
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct Statistics {
#[mmio(PureRead)]
tx_octets_low: u32,
#[mmio(PureRead)]
tx_octets_high: u32,
#[mmio(PureRead)]
tx_count: u32,
#[mmio(PureRead)]
tx_broadcast: u32,
#[mmio(PureRead)]
tx_multicast: u32,
#[mmio(PureRead)]
tx_pause: u32,
#[mmio(PureRead)]
tx_64_bits: u32,
#[mmio(PureRead)]
tx_65_to_127_bits: u32,
#[mmio(PureRead)]
tx_128_to_255_bits: u32,
#[mmio(PureRead)]
tx_256_to_511_bits: u32,
#[mmio(PureRead)]
tx_512_to_1023_bits: u32,
#[mmio(PureRead)]
tx_1024_to_1518_bits: u32,
_reserved0: u32,
#[mmio(PureRead)]
tx_underruns: u32,
#[mmio(PureRead)]
single_collision_frames: u32,
#[mmio(PureRead)]
multi_collision_frames: u32,
#[mmio(PureRead)]
excessive_collisions: u32,
#[mmio(PureRead)]
late_collisions: u32,
#[mmio(PureRead)]
deferred_tx: u32,
#[mmio(PureRead)]
carrier_sense_errors: u32,
#[mmio(PureRead)]
rx_octets_low: u32,
#[mmio(PureRead)]
rx_octets_high: u32,
#[mmio(PureRead)]
rx_count: u32,
#[mmio(PureRead)]
rx_broadcast: u32,
#[mmio(PureRead)]
rx_multicast: u32,
#[mmio(PureRead)]
rx_pause: u32,
#[mmio(PureRead)]
rx_64_bits: u32,
#[mmio(PureRead)]
rx_65_to_127_bits: u32,
#[mmio(PureRead)]
rx_128_to_255_bits: u32,
#[mmio(PureRead)]
rx_256_to_511_bits: u32,
#[mmio(PureRead)]
rx_512_to_1023_bits: u32,
#[mmio(PureRead)]
rx_1024_to_1518_bits: u32,
_reserved1: u32,
#[mmio(PureRead)]
rx_undersize: u32,
#[mmio(PureRead)]
rx_oversize: u32,
#[mmio(PureRead)]
rx_jabber: u32,
#[mmio(PureRead)]
rx_frame_check_sequence_errors: u32,
#[mmio(PureRead)]
rx_length_field_errors: u32,
#[mmio(PureRead)]
rx_symbol_errors: u32,
#[mmio(PureRead)]
rx_alignment_errors: u32,
#[mmio(PureRead)]
rx_resource_errors: u32,
#[mmio(PureRead)]
rx_overrun_errors: u32,
#[mmio(PureRead)]
rx_ip_header_checksum_errors: u32,
#[mmio(PureRead)]
rx_tcp_checksum_errors: u32,
#[mmio(PureRead)]
rx_udp_checksum_errors: u32,
}
impl Ethernet {
/// Create a new Gigabit Ethernet MMIO instance for GEM 0 at address [GEM_0_BASE_ADDR].
///
/// # Safety
///
/// This API can be used to potentially create a driver to the same peripheral structure
/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
/// interfere with each other.
pub const unsafe fn new_mmio_fixed_0() -> MmioEthernet<'static> {
unsafe { Self::new_mmio_at(GEM_0_BASE_ADDR) }
}
/// Create a new Gigabit Ethernet MMIO instance for GEM 1 at address [GEM_1_BASE_ADDR].
///
/// # Safety
///
/// This API can be used to potentially create a driver to the same peripheral structure
/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
/// interfere with each other.
pub const unsafe fn new_mmio_fixed_1() -> MmioEthernet<'static> {
unsafe { Self::new_mmio_at(GEM_1_BASE_ADDR) }
}
}

2
zynq7000/src/i2c.rs
View File

@ -178,6 +178,8 @@ pub struct I2c {
idr: InterruptControl,
}
static_assertions::const_assert_eq!(core::mem::size_of::<I2c>(), 0x2C);
impl I2c {
/// Create a new I2C MMIO instance for I2C0 at address [I2C_0_BASE_ADDR].
///

144
zynq7000/src/l2_cache.rs Normal file
View File

@ -0,0 +1,144 @@
use arbitrary_int::{u4, u6};
pub const L2C_BASE_ADDR: usize = 0xF8F0_2000;
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct LockdownRegisters {
data: u32,
instruction: u32,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct CacheSync {
#[bit(0, r)]
busy: bool,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
pub struct DebugControl {
#[bit(2, rw)]
spniden: bool,
#[bit(1, rw)]
disable_write_back: bool,
#[bit(0, rw)]
disable_cache_linefill: bool,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct CacheId {
#[bits(24..=31, r)]
implementer: u8,
#[bits(10..=15, r)]
cache_id: u6,
#[bits(6..=9, r)]
part_number: u4,
#[bits(0..=5, r)]
rtl_release: u6,
}
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct L2Cache {
#[mmio(PureRead)]
cache_id: CacheId,
#[mmio(PureRead)]
cache_type: u32,
_reserved: [u32; 0x3E],
control: u32,
aux_control: u32,
tag_ram_control: u32,
data_ram_control: u32,
_reserved2: [u32; 0x3C],
event_counter_control: u32,
event_counter_1_config: u32,
event_counter_0_config: u32,
event_counter_1: u32,
event_counter_0: u32,
interrupt_mask: u32,
#[mmio(PureRead)]
interrupt_mask_status: u32,
#[mmio(PureRead)]
interrupt_raw_status: u32,
#[mmio(Write)]
interrupt_clear: u32,
_reserved3: [u32; 0x143],
cache_sync: CacheSync,
_reserved4: [u32; 0xF],
invalidate_by_pa: u32,
_reserved5: [u32; 0x2],
invalidate_by_way: u32,
_reserved6: [u32; 0xC],
clean_by_pa: u32,
_reserved7: u32,
clean_by_index: u32,
clean_by_way: u32,
_reserved8: [u32; 0xC],
clean_invalidate_by_pa: u32,
_reserved9: u32,
clean_invalidate_by_index: u32,
clean_invalidate_by_way: u32,
_reserved10: [u32; 0x40],
#[mmio(inner)]
lockdown_regs: [LockdownRegisters; 8],
_reserved11: [u32; 0x4],
lockdown_by_line_enable: u32,
unlock_way: u32,
_reserved12: [u32; 0xAA],
addr_filtering_start: u32,
addr_filtering_end: u32,
_reserved13: [u32; 0xCE],
debug_control: DebugControl,
_reserved14: [u32; 0x7],
prefetch_control: u32,
_reserved15: [u32; 0x7],
power_control: u32,
}
static_assertions::const_assert_eq!(core::mem::size_of::<L2Cache>(), 0xF84);
impl L2Cache {
/// Create a new L2C MMIO instance for for L2 Cache at address [I2C_0_BASE_ADDR].
///
/// # Safety
///
/// This API can be used to potentially create a driver to the same peripheral structure
/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
/// interfere with each other.
pub const unsafe fn new_mmio_fixed() -> MmioL2Cache<'static> {
unsafe { Self::new_mmio_at(L2C_BASE_ADDR) }
}
}

2
zynq7000/src/lib.rs
View File

@ -15,10 +15,12 @@ extern crate std;
pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
pub mod eth;
pub mod gic;
pub mod gpio;
pub mod gtc;
pub mod i2c;
pub mod l2_cache;
pub mod mpcore;
pub mod slcr;
pub mod spi;

2
zynq7000/src/slcr/mio.rs
View File

@ -17,7 +17,7 @@ pub enum IoType {
Hstl = 0b100,
}
#[bitbybit::bitfield(u32)]
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
pub struct Config {
#[bit(13, rw)]

33
zynq7000/src/slcr/mod.rs
View File

@ -1,7 +1,7 @@
//! System Level Control Registers (slcr)
//!
//! Writing any of these registers required unlocking the SLCR first.
use arbitrary_int::u4;
use arbitrary_int::{u3, u4};
pub use clocks::{ClockControl, MmioClockControl};
pub use reset::{MmioResetControl, ResetControl};
@ -50,10 +50,27 @@ impl DdrIoB {
static_assertions::const_assert_eq!(core::mem::size_of::<DdrIoB>(), 0x38);
#[bitbybit::bitenum(u3, exhaustive = false)]
pub enum VrefSel {
Disabled = 0b000,
Vref0_9V = 0b001,
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct GpiobControl {
#[bit(11, rw)]
vref_sw_en: bool,
#[bits(4..=6, rw)]
vref_sel: Option<VrefSel>,
#[bit(0, rw)]
vref_en: bool,
}
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct GpiobCtrl {
ctrl: u32,
pub struct GpiobRegisters {
ctrl: GpiobControl,
cfg_cmos18: u32,
cfg_cmos25: u32,
cfg_cmos33: u32,
@ -62,7 +79,7 @@ pub struct GpiobCtrl {
drvr_bias_ctrl: u32,
}
impl GpiobCtrl {
impl GpiobRegisters {
/// Create a new handle to this peripheral.
///
/// Writing to this register requires unlocking the SLCR registers first.
@ -71,12 +88,13 @@ impl GpiobCtrl {
///
/// If you create multiple instances of this handle at the same time, you are responsible for
/// ensuring that there are no read-modify-write races on any of the registers.
pub unsafe fn new_mmio_fixed() -> MmioGpiobCtrl<'static> {
pub unsafe fn new_mmio_fixed() -> MmioGpiobRegisters<'static> {
unsafe { Self::new_mmio_at(SLCR_BASE_ADDR + GPIOB_OFFSET) }
}
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
pub struct BootModeRegister {
#[bit(4, r)]
pll_bypass: bool,
@ -176,14 +194,15 @@ pub struct Slcr {
_gap15: [u32; 0x42],
reserved: u32,
/// Xilinx marks this as reserved but writes to it in their low-level L2 cache configuration.
magic_l2c_register: u32,
_gap16: [u32; 0x38],
_gap18: [u32; 0x09],
#[mmio(inner)]
gpiob: GpiobCtrl,
gpiob: GpiobRegisters,
#[mmio(inner)]
ddriob: DdrIoB,

19
zynq7000/src/slcr/reset.rs
View File

@ -35,6 +35,23 @@ pub struct GpioClockReset {
gpio_cpu1x_rst: bool,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
pub struct EthernetReset {
#[bit(5, rw)]
gem1_ref_rst: bool,
#[bit(4, rw)]
gem0_ref_rst: bool,
#[bit(3, rw)]
gem1_rx_rst: bool,
#[bit(2, rw)]
gem0_rx_rst: bool,
#[bit(1, rw)]
gem1_cpu1x_rst: bool,
#[bit(0, rw)]
gem0_cpu1x_rst: bool,
}
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct ResetControl {
@ -45,7 +62,7 @@ pub struct ResetControl {
topsw: u32,
dmac: u32,
usb: u32,
gem: u32,
eth: EthernetReset,
sdio: DualRefAndClockReset,
spi: DualRefAndClockReset,
can: DualClockReset,