README.md

@@ -111,7 +111,8 @@ target = "armv7a-none-eabihf"
 You can build the blinky example app using
 
 ```sh
-cargo build --example simple
+cd zynq
+cargo build --bin blinky
 ```
 
 

zynq/zynq7000-mmu/src/lib.rs

@@ -1,4 +1,4 @@
-//! # Zynq7000 Memory Management Unit (MMU) 
+//! # Zynq7000 Memory Management Unit (MMU)
 //!
 //! Dedicated shared crate for Zynq7000 MMU abstractions which can be used by Zynq
 //! runtime crates, PACs and HALs.

zynq/zynq7000/src/ddrc.rs

@@ -725,6 +725,7 @@ pub mod regs {
 
 use regs::*;
 
+/// DDR controller register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DdrController {

zynq/zynq7000/src/devcfg.rs

@@ -257,6 +257,7 @@ pub struct Status {
     efuse_jtag_disabled: bool,
 }
 
+/// Device configuration register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DevCfg {

zynq/zynq7000/src/eth.rs

@@ -418,7 +418,7 @@ pub struct MatchRegister {
     type_id: u16,
 }
 
-/// Gigabit Ethernet Controller (GEM) registers for Zynq-7000
+/// Gigabit Ethernet Controller (GEM) register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ethernet {
@@ -477,7 +477,7 @@ pub struct Ethernet {
 
 static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
 
-/// GEM statistics registers
+/// Ethernet statistics registers
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Statistics {

zynq/zynq7000/src/gpio.rs

@@ -35,6 +35,7 @@ pub struct BankControl {
     int_any: u32,
 }
 
+/// GPIO register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Gpio {

zynq/zynq7000/src/gtc.rs

@@ -22,7 +22,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
-/// Global timer counter.
+/// Global timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct GlobalTimerCounter {

zynq/zynq7000/src/i2c.rs

@@ -156,6 +156,7 @@ pub struct TransferSize {
     size: u8,
 }
 
+/// I2C register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct I2c {

zynq/zynq7000/src/l2_cache.rs

@@ -184,6 +184,7 @@ pub struct InterruptControl {
     event_counter_overflow_increment: bool,
 }
 
+/// L2 Cache register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct L2Cache {

zynq/zynq7000/src/mpcore.rs

@@ -44,6 +44,7 @@ impl SnoopControlUnit {
 
 const_assert_eq!(core::mem::size_of::<SnoopControlUnit>(), 0x58);
 
+/// MP Core register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct MpCore {

zynq/zynq7000/src/priv_tim.rs

@@ -21,6 +21,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
+/// CPU private timer register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct CpuPrivateTimer {

zynq/zynq7000/src/qspi.rs

@@ -220,6 +220,7 @@ pub struct LinearQspiStatus {
     axi_write_command_received: bool,
 }
 
+/// QSPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Qspi {

zynq/zynq7000/src/slcr/mod.rs

@@ -91,7 +91,7 @@ pub struct LevelShifterRegister {
     user_lvl_shftr_en: Option<LevelShifterConfig>,
 }
 
-/// System Level Control Registers
+/// System Level Control Registers access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Slcr {

zynq/zynq7000/src/spi.rs

@@ -178,7 +178,7 @@ pub struct DelayControl {
     cs_to_first_bit: u8,
 }
 
-/// Register block specification for both PS SPIs.
+/// SPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Spi {

zynq/zynq7000/src/ttc.rs

@@ -142,7 +142,7 @@ pub struct EventCount {
     count: u16,
 }
 
-/// Triple-timer counter
+/// Triple-timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ttc {

zynq/zynq7000/src/uart.rs

@@ -278,6 +278,7 @@ impl InterruptStatus {
     }
 }
 
+/// UART register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Uart {

zynq/zynq7000/src/xadc.rs

@@ -1,5 +1,6 @@
 pub const XADC_BASE_ADDR: usize = 0xF8007100;
 
+/// XADC register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct XAdc {