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improve HAL docs #18

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muellerr merged 1 commits from improve-hal-docs into main 2025-10-09 11:38:02 +02:00
Conversation 0 Commits 1 Files Changed 19 +72 -17
19 changed files with 72 additions and 17 deletions
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4
zynq/zynq7000-hal/src/cache.rs
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@@ -1,3 +1,7 @@
//! # Cache management module
//!
//! A lot of cache maintenance operations for this SoC have to be performed on both the L1 and the
//! L2 cache in the correct order. This module provides commonly required operations.
use core::sync::atomic::compiler_fence;
use cortex_ar::{

6
zynq/zynq7000-hal/src/clocks/mod.rs
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@@ -1,4 +1,8 @@
//! Clock module.
//! # Clock module
//!
//! ## Examples
//!
//! - PLL initialization in [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
use arbitrary_int::{prelude::*, u6};
pub mod pll;

5
zynq/zynq7000-hal/src/ddr/mod.rs
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@@ -1,3 +1,8 @@
//! # DDR module
//!
//! ## Examples
//!
//! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
use arbitrary_int::u6;
use zynq7000::ddrc::MmioDdrController;

1
zynq/zynq7000-hal/src/devcfg.rs
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@@ -1,3 +1,4 @@
//! # Device Configuration Module
#[derive(Debug, thiserror::Error)]
#[error("unaligned address: {0}")]
pub struct UnalignedAddrError(usize);

5
zynq/zynq7000-hal/src/eth/mod.rs
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@@ -1,3 +1,8 @@
//! # Ethernet module
//!
//! ## Examples
//!
//! - [Zedboard Ethernet](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/ethernet.rs)
use arbitrary_int::{u2, u3};
pub use zynq7000::eth::MdcClockDivisor;
use zynq7000::eth::{

6
zynq/zynq7000-hal/src/gic.rs
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@@ -1,4 +1,4 @@
//! Global Interrupt Controller (GIC) module.
//! # Global Interrupt Controller (GIC) module
//!
//! The primary interface to configure and allow handling the interrupts are the
//! [GicConfigurator] and the [GicInterruptHelper] structures.
@@ -191,9 +191,9 @@ pub struct InvalidSgiInterruptId(pub usize);
///
/// The flow of using this controller is as follows:
///
/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::PsPeripherals]
/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::Peripherals]
/// structure or the [zynq7000::gic::GicCpuInterface::new_mmio] and [zynq7000::gic::GicDistributor::new_mmio]
/// functions to create the MMIO instances. The constructor configures all PL interrupts
/// functions to retrieve the MMIO instances. The constructor configures all PL interrupts
/// sensivities to high-level sensitivity and configures all sensitivities which are expected
/// to have a certain value. It also sets the priority mask to 0xff by calling
/// [Self::set_priority_mask] to prevent masking of the interrupts.

6
zynq/zynq7000-hal/src/gpio/mod.rs
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@@ -1,12 +1,12 @@
//! GPIO support module for the Zynq7000 SoC.
//! # GPIO module
//!
//! This module contains a MIO and EMIO pin resource managements singleton as well as abstractions
//! to use these pins as GPIOs.
//!
//! # Examples
//!
//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/main.rs)
//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/logger.rs)
//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/main.rs)
//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
//! which uses MIO pins for the UART.
pub mod emio;
pub mod ll;

8
zynq/zynq7000-hal/src/gtc.rs
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@@ -1,9 +1,9 @@
//! Global timer counter driver module.
//! # Global timer counter driver module
//!
//! # Examples
//! ## Examples
//!
//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq7000-embassy/src/lib.rs)
//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/gtc-ticks.rs)
//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zynq7000-embassy/src/lib.rs)
use zynq7000::gtc::MmioGlobalTimerCounter;
use crate::{clocks::ArmClocks, time::Hertz};

1
zynq/zynq7000-hal/src/i2c.rs
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@@ -1,3 +1,4 @@
//! # I2C module
use arbitrary_int::{u2, u3, u6};
use embedded_hal::i2c::NoAcknowledgeSource;
use zynq7000::{

1
zynq/zynq7000-hal/src/l2_cache.rs
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@@ -1,3 +1,4 @@
//! # L2 cache module
use core::sync::atomic::compiler_fence;
use arbitrary_int::{u2, u3};

5
zynq/zynq7000-hal/src/lib.rs
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@@ -7,6 +7,11 @@
//! raw PAC. This crate also implements traits specified by the
//! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
//! various drivers in the embedded rust ecosystem.
//!
//! ## Examples
//!
//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples)
//! of the project
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]

7
zynq/zynq7000-hal/src/log.rs
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@@ -1,4 +1,9 @@
//! # Simple logging providers.
//! # Simple logging providers
//!
//! ## Examples
//!
//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
//! which uses MIO pins for the UART.
use core::sync::atomic::{AtomicBool, AtomicU8};

5
zynq/zynq7000-hal/src/priv_tim.rs
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@@ -1,3 +1,8 @@
//! # CPU private timer module
//!
//! ## Examples
//!
//! - Private timer as delay provider in [blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/blinky.rs)
use core::{marker::PhantomData, sync::atomic::AtomicBool};
use zynq7000::priv_tim::InterruptStatus;

5
zynq/zynq7000-hal/src/qspi/mod.rs
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@@ -1,3 +1,8 @@
//! # QSPI module
//!
//! ## Examples
//!
//! - [Zedboard QSPI](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/qspi.rs)
use core::ops::{Deref, DerefMut};
use arbitrary_int::{prelude::*, u2, u3, u6};

2
zynq/zynq7000-hal/src/slcr.rs
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@@ -1,4 +1,4 @@
//! # System Level Control Register (SLCR) module.
//! # System Level Control Register (SLCR) module
use zynq7000::slcr::MmioSlcr;
pub const LOCK_KEY: u32 = 0x767B;

6
zynq/zynq7000-hal/src/spi/mod.rs
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@@ -1,4 +1,8 @@
//! PS SPI HAL driver.
//! SPI module
//!
//! ## Examples
//!
//! - [L3GD20H SPI sensor](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs)
use core::convert::Infallible;
use crate::clocks::Clocks;

2
zynq/zynq7000-hal/src/time.rs
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@@ -1,4 +1,4 @@
//! Time units
//! # Time units
// Frequency based

6
zynq/zynq7000-hal/src/ttc.rs
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@@ -1,6 +1,10 @@
//! Triple-timer counter (TTC) high-level driver.
//! # Triple-timer counter (TTC) high-level driver
//!
//! This module also contains support for PWM and output waveform generation.
//!
//! ## Examples
//!
//! - [PWM](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/embassy/src/bin/pwm.rs)
use core::convert::Infallible;

8
zynq/zynq7000-hal/src/uart/mod.rs
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@@ -1,6 +1,12 @@
//! # UART module.
//! # UART module
//!
//! Support for the processing system UARTs.
//!
//! ## Examples
//!
//! - [Logger through UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
//! - [Zedboard Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-blocking.rs)
//! - [Zedboard Non-Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-non-blocking.rs)
use core::convert::Infallible;
use arbitrary_int::u3;