10 Commits

Author SHA1 Message Date
02725c9aa2 v0.2.1: updated homepage and repostory
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2021-12-03 15:04:20 +01:00
b09e82a563 Merge pull request 'v0.2.0: Relicensed as Apache-2.0' (#3) from mueller/bump-to-v0.2.0 into main
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Reviewed-on: rust/va108xx-rs#3
2021-12-03 14:41:59 +01:00
2c86b1420e v0.2.0: Relicensed and republished
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- Now hosted on EGit
2021-12-03 14:28:37 +01:00
74a4c44f71 Merge pull request 'NOTICE Draft' (#2) from mohr-NOTICE into main
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Reviewed-on: rust/va108xx-rs#2
2021-11-29 09:54:16 +01:00
b7ba49258c NOTICE Draft
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2021-11-26 18:00:10 +01:00
acadf7cdc9 Merge pull request 'EGit integration' (#1) from mueller/egit-integration into main
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Reviewed-on: rust/va108xx-rs#1
2021-11-26 14:56:15 +01:00
952ec3738b EGit integration
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- Added automation files for CI/CD
- Relicense as Apache 2.0
2021-11-23 10:34:25 +01:00
e59ba9e860 Merge #12
12: I2C update r=robamu a=robamu

- Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE
- Made STATUS register read-only

Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>
2021-11-23 09:19:29 +00:00
4c91a36568 I2C update
- Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE
- Made STATUS register read-only
2021-11-23 01:42:22 +01:00
1c08574e3e update changelog 2021-11-09 18:49:01 +01:00
10 changed files with 124 additions and 409 deletions

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@ -10,9 +10,20 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [v0.2.0]
## [v0.1.1]
- Authorative repository was transferred to https://egit.irs.uni-stuttgart.de/rust/va108xx-rs but
there still will be a GitHub mirror. Project relicensed as Apache-2.0 only
- Relicensed under dual Apache-2.0 / MIT license
## [v0.1.3]
### Added
- Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE
### Fixed
- Made I2CA STATUS register read-only
## [v0.1.2]
### Fixed
@ -20,6 +31,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
https://github.com/rust-embedded/svd2rust/pull/549 for more details.
Some bitmasks were missing from register reader definitions.
## [v0.1.1]
- Relicensed under dual Apache-2.0 / MIT license
### Changed
- SVD file handling improved and new fields added for the peripheral

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@ -1,12 +1,12 @@
[package]
name = "va108xx"
version = "0.1.2"
authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
version = "0.2.1"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers"
homepage = "https://github.com/robamu-org/va108xx-rs"
repository = "https://github.com/robamu-org/va108xx-rs"
license = "MIT OR Apache-2.0"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
license = "Apache-2.0"
keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
categories = ["embedded", "no-std", "hardware-support"]

View File

@ -1,25 +0,0 @@
Copyright (c) 2021 Robin Mueller
Permission is hereby granted, free of charge, to any
person obtaining a copy of this software and associated
documentation files (the "Software"), to deal in the
Software without restriction, including without
limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of
the Software, and to permit persons to whom the Software
is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice
shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.

3
NOTICE Normal file
View File

@ -0,0 +1,3 @@
Peripheral access crate for the Vorago VA108xx family microcontrollers
This software contains code developed at the University of Stuttgart.

11
automation/Dockerfile Normal file
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@ -0,0 +1,11 @@
# Run the following commands from root directory to build and run locally
# docker build -f automation/Dockerfile -t <NAME> .
# docker run -it <NAME>
FROM rust:latest
RUN apt-get update
RUN apt-get --yes upgrade
# tzdata is a dependency, won't install otherwise
ARG DEBIAN_FRONTEND=noninteractive
RUN rustup target add thumbv6m-none-eabi && \
rustup component add rustfmt clippy

39
automation/Jenkinsfile vendored Normal file
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@ -0,0 +1,39 @@
pipeline {
agent any
stages {
stage('Clippy') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo clippy'
}
}
stage('Rustfmt') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo fmt'
}
}
stage('Build') {
agent {
dockerfile {
dir 'automation'
reuseNode true
}
}
steps {
sh 'cargo build'
}
}
}
}

View File

@ -13,27 +13,6 @@ impl From<crate::R<STATUS_SPEC>> for R {
R(reader)
}
}
#[doc = "Register `STATUS` writer"]
pub struct W(crate::W<STATUS_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<STATUS_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<STATUS_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<STATUS_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `WAITING` reader - Controller is Waiting"]
pub struct WAITING_R(crate::FieldReader<bool, bool>);
impl WAITING_R {
@ -49,28 +28,6 @@ impl core::ops::Deref for WAITING_R {
&self.0
}
}
#[doc = "Field `WAITING` writer - Controller is Waiting"]
pub struct WAITING_W<'a> {
w: &'a mut W,
}
impl<'a> WAITING_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `STALLED` reader - Controller is Stalled"]
pub struct STALLED_R(crate::FieldReader<bool, bool>);
impl STALLED_R {
@ -86,28 +43,6 @@ impl core::ops::Deref for STALLED_R {
&self.0
}
}
#[doc = "Field `STALLED` writer - Controller is Stalled"]
pub struct STALLED_W<'a> {
w: &'a mut W,
}
impl<'a> STALLED_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
self.w
}
}
#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
impl ARBLOST_R {
@ -123,28 +58,6 @@ impl core::ops::Deref for ARBLOST_R {
&self.0
}
}
#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
pub struct ARBLOST_W<'a> {
w: &'a mut W,
}
impl<'a> ARBLOST_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
impl NACKADDR_R {
@ -160,28 +73,6 @@ impl core::ops::Deref for NACKADDR_R {
&self.0
}
}
#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
pub struct NACKADDR_W<'a> {
w: &'a mut W,
}
impl<'a> NACKADDR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
impl NACKDATA_R {
@ -197,28 +88,6 @@ impl core::ops::Deref for NACKDATA_R {
&self.0
}
}
#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
pub struct NACKDATA_W<'a> {
w: &'a mut W,
}
impl<'a> NACKDATA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
pub struct RXNEMPTY_R(crate::FieldReader<bool, bool>);
impl RXNEMPTY_R {
@ -234,28 +103,6 @@ impl core::ops::Deref for RXNEMPTY_R {
&self.0
}
}
#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"]
pub struct RXNEMPTY_W<'a> {
w: &'a mut W,
}
impl<'a> RXNEMPTY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `RXFULL` reader - RX FIFO is Full"]
pub struct RXFULL_R(crate::FieldReader<bool, bool>);
impl RXFULL_R {
@ -271,28 +118,6 @@ impl core::ops::Deref for RXFULL_R {
&self.0
}
}
#[doc = "Field `RXFULL` writer - RX FIFO is Full"]
pub struct RXFULL_W<'a> {
w: &'a mut W,
}
impl<'a> RXFULL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
pub struct RXTRIGGER_R(crate::FieldReader<bool, bool>);
impl RXTRIGGER_R {
@ -308,28 +133,6 @@ impl core::ops::Deref for RXTRIGGER_R {
&self.0
}
}
#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"]
pub struct RXTRIGGER_W<'a> {
w: &'a mut W,
}
impl<'a> RXTRIGGER_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
impl TXEMPTY_R {
@ -345,28 +148,6 @@ impl core::ops::Deref for TXEMPTY_R {
&self.0
}
}
#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"]
pub struct TXEMPTY_W<'a> {
w: &'a mut W,
}
impl<'a> TXEMPTY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
self.w
}
}
#[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
pub struct TXNFULL_R(crate::FieldReader<bool, bool>);
impl TXNFULL_R {
@ -382,28 +163,6 @@ impl core::ops::Deref for TXNFULL_R {
&self.0
}
}
#[doc = "Field `TXNFULL` writer - TX FIFO is Full"]
pub struct TXNFULL_W<'a> {
w: &'a mut W,
}
impl<'a> TXNFULL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
self.w
}
}
#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
pub struct TXTRIGGER_R(crate::FieldReader<bool, bool>);
impl TXTRIGGER_R {
@ -419,28 +178,6 @@ impl core::ops::Deref for TXTRIGGER_R {
&self.0
}
}
#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"]
pub struct TXTRIGGER_W<'a> {
w: &'a mut W,
}
impl<'a> TXTRIGGER_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
self.w
}
}
#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
pub struct RAW_SDA_R(crate::FieldReader<bool, bool>);
impl RAW_SDA_R {
@ -456,28 +193,6 @@ impl core::ops::Deref for RAW_SDA_R {
&self.0
}
}
#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"]
pub struct RAW_SDA_W<'a> {
w: &'a mut W,
}
impl<'a> RAW_SDA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
self.w
}
}
#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
pub struct RAW_SCL_R(crate::FieldReader<bool, bool>);
impl RAW_SCL_R {
@ -493,26 +208,34 @@ impl core::ops::Deref for RAW_SCL_R {
&self.0
}
}
#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"]
pub struct RAW_SCL_W<'a> {
w: &'a mut W,
#[doc = "Field `I2C_IDLE` reader - I2C bus is Idle"]
pub struct I2C_IDLE_R(crate::FieldReader<bool, bool>);
impl I2C_IDLE_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
I2C_IDLE_R(crate::FieldReader::new(bits))
}
}
impl<'a> RAW_SCL_W<'a> {
#[doc = r"Sets the field bit"]
impl core::ops::Deref for I2C_IDLE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
fn deref(&self) -> &Self::Target {
&self.0
}
#[doc = r"Clears the field bit"]
}
#[doc = "Field `IDLE` reader - Controller is Idle"]
pub struct IDLE_R(crate::FieldReader<bool, bool>);
impl IDLE_R {
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
pub(crate) fn new(bits: bool) -> Self {
IDLE_R(crate::FieldReader::new(bits))
}
#[doc = r"Writes raw bits to the field"]
}
impl core::ops::Deref for IDLE_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
self.w
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl R {
@ -581,81 +304,18 @@ impl R {
pub fn raw_scl(&self) -> RAW_SCL_R {
RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 2 - Controller is Waiting"]
#[doc = "Bit 0 - I2C bus is Idle"]
#[inline(always)]
pub fn waiting(&mut self) -> WAITING_W {
WAITING_W { w: self }
pub fn i2c_idle(&self) -> I2C_IDLE_R {
I2C_IDLE_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 3 - Controller is Stalled"]
#[doc = "Bit 1 - Controller is Idle"]
#[inline(always)]
pub fn stalled(&mut self) -> STALLED_W {
STALLED_W { w: self }
}
#[doc = "Bit 4 - I2C Arbitration was lost"]
#[inline(always)]
pub fn arblost(&mut self) -> ARBLOST_W {
ARBLOST_W { w: self }
}
#[doc = "Bit 5 - I2C Address was not Acknowledged"]
#[inline(always)]
pub fn nackaddr(&mut self) -> NACKADDR_W {
NACKADDR_W { w: self }
}
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)]
pub fn nackdata(&mut self) -> NACKDATA_W {
NACKDATA_W { w: self }
}
#[doc = "Bit 8 - RX FIFO is Not Empty"]
#[inline(always)]
pub fn rxnempty(&mut self) -> RXNEMPTY_W {
RXNEMPTY_W { w: self }
}
#[doc = "Bit 9 - RX FIFO is Full"]
#[inline(always)]
pub fn rxfull(&mut self) -> RXFULL_W {
RXFULL_W { w: self }
}
#[doc = "Bit 11 - RX FIFO Above Trigger Level"]
#[inline(always)]
pub fn rxtrigger(&mut self) -> RXTRIGGER_W {
RXTRIGGER_W { w: self }
}
#[doc = "Bit 12 - TX FIFO is Empty"]
#[inline(always)]
pub fn txempty(&mut self) -> TXEMPTY_W {
TXEMPTY_W { w: self }
}
#[doc = "Bit 13 - TX FIFO is Full"]
#[inline(always)]
pub fn txnfull(&mut self) -> TXNFULL_W {
TXNFULL_W { w: self }
}
#[doc = "Bit 15 - TX FIFO Below Trigger Level"]
#[inline(always)]
pub fn txtrigger(&mut self) -> TXTRIGGER_W {
TXTRIGGER_W { w: self }
}
#[doc = "Bit 30 - I2C Raw SDA value"]
#[inline(always)]
pub fn raw_sda(&mut self) -> RAW_SDA_W {
RAW_SDA_W { w: self }
}
#[doc = "Bit 31 - I2C Raw SCL value"]
#[inline(always)]
pub fn raw_scl(&mut self) -> RAW_SCL_W {
RAW_SCL_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
pub fn idle(&self) -> IDLE_R {
IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
}
}
#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
pub struct STATUS_SPEC;
impl crate::RegisterSpec for STATUS_SPEC {
type Ux = u32;
@ -664,10 +324,6 @@ impl crate::RegisterSpec for STATUS_SPEC {
impl crate::Readable for STATUS_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"]
impl crate::Writable for STATUS_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets STATUS to value 0"]
impl crate::Resettable for STATUS_SPEC {
#[inline(always)]

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@ -1,4 +1,4 @@
#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (43be074 2021-11-09))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (877196f 2021-11-14))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![deny(const_err)]
#![deny(dead_code)]

View File

@ -2157,7 +2157,7 @@
<name>STATUS</name>
<description>I2C Controller Status Register</description>
<addressOffset>0x018</addressOffset>
<fields>
<access>read-only</access><fields>
<field>
<name>WAITING</name>
<description>Controller is Waiting</description>
@ -2223,7 +2223,9 @@
<description>I2C Raw SCL value</description>
<bitRange>[31:31]</bitRange>
</field>
</fields>
<field><name>I2C_IDLE</name><description>I2C bus is Idle</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field>
<field><name>IDLE</name><description>Controller is Idle</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field>
</fields>
</register>
<register>
<name>STATE</name>

View File

@ -56,4 +56,18 @@ SYSCONFIG:
bitOffset: 24
bitWidth: 1
# I2CB is derived from I2CA
I2CA:
_modify:
STATUS:
access: read-only
STATUS:
_add:
I2C_IDLE:
description: I2C bus is Idle
bitOffset: 0
bitWidth: 1
IDLE:
description: Controller is Idle
bitOffset: 1
bitWidth: 1