eive-obsw/mission/pollingSeqTables.cpp

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#include "pollingSeqTables.h"
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#include <fsfw/devicehandlers/DeviceHandlerIF.h>
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#include <fsfw/objectmanager/ObjectManagerIF.h>
#include <fsfw/serviceinterface/ServiceInterfaceStream.h>
#include <fsfw/tasks/FixedTimeslotTaskIF.h>
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#include <mission/acs/imtqHelpers.h>
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#include <mission/tcs/Max31865Definitions.h>
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#include "OBSWConfig.h"
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#include "eive/definitions.h"
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#ifndef RPI_TEST_ADIS16507
#define RPI_TEST_ADIS16507 0
#endif
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#ifndef RPI_TEST_GPS_HANDLER
#define RPI_TEST_GPS_HANDLER 0
#endif
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ReturnValue_t pst::pstSyrlinks(FixedTimeslotTaskIF *thisSequence) {
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uint32_t length = thisSequence->getPeriodMs();
thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.4,
DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.4, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.4, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
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static_cast<void>(length);
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return thisSequence->checkSequence();
}
// I don't think this needs to be in a PST because linux takes care of bus serialization, but
// keep it like this for now, it works
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ReturnValue_t pst::pstI2cProcessingSystem(FixedTimeslotTaskIF *thisSequence) {
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// Length of a communication cycle
uint32_t length = thisSequence->getPeriodMs();
static_cast<void>(length);
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// These are actually part of another bus, but this works, so keep it like this for now
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.2,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.2, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.2, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.3, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.3, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.4,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.4, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.4, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.5, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.5, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.6,
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DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.6,
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DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.6,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.7,
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DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.7, DeviceHandlerIF::GET_READ);
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// damaged
/*
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.4,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.4,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.4,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.4,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.4, DeviceHandlerIF::GET_READ);
*/
thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.9,
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DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.9, DeviceHandlerIF::GET_READ);
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static_cast<void>(length);
return thisSequence->checkSequence();
}
ReturnValue_t pst::pstGompaceCan(FixedTimeslotTaskIF *thisSequence) {
uint32_t length = thisSequence->getPeriodMs();
// PCDU handlers receives two messages and both must be handled
thisSequence->addSlot(objects::PCDU_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.5, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.5, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.5, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.5, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.5, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.5, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.5, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.5, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.5, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.5, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.5, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.5, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::ACU_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
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if (thisSequence->checkSequence() != returnvalue::OK) {
sif::error << "GomSpace PST initialization failed" << std::endl;
return returnvalue::FAILED;
}
static_cast<void>(length);
return returnvalue::OK;
}
ReturnValue_t pst::pstTest(FixedTimeslotTaskIF *thisSequence) {
/* Length of a communication cycle */
uint32_t length = thisSequence->getPeriodMs();
bool notEmpty = false;
#if RPI_TEST_ADIS16507 == 1
notEmpty = true;
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.2, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.4, DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.6, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.8, DeviceHandlerIF::GET_READ);
#endif
#if RPI_TEST_GPS_HANDLER == 1
notEmpty = true;
thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::GPS0_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::GPS0_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
#endif
static_cast<void>(length);
if (not notEmpty) {
return returnvalue::FAILED;
}
if (thisSequence->checkSequence() != returnvalue::OK) {
sif::error << "Test PST initialization failed" << std::endl;
return returnvalue::FAILED;
}
return returnvalue::OK;
}
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ReturnValue_t pst::pstTcsAndAcs(FixedTimeslotTaskIF *thisSequence, AcsPstCfg cfg) {
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/* Length of a communication cycle */
uint32_t length = thisSequence->getPeriodMs();
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// SUS: 16 ms
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if (cfg.scheduleSus) {
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/* Write setup */
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
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length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-03-01 16:36:21 +01:00
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
2023-03-01 16:36:21 +01:00
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-03-01 16:36:21 +01:00
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
2023-03-01 16:36:21 +01:00
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-03-01 16:36:21 +01:00
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
DeviceHandlerIF::GET_READ);
2022-02-23 19:26:02 +01:00
}
2022-05-05 16:46:04 +02:00
2023-02-08 16:46:30 +01:00
if (cfg.scheduleStr) {
2023-03-22 02:20:14 +01:00
// 2 COM cycles for full PST for STR. The STR requests 2 packets types in NORMAL mode, this
// ensures we always get an updated STR dataset for a regular normal mode cycle.
2023-02-08 16:46:30 +01:00
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::GET_WRITE);
2023-03-22 02:20:14 +01:00
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::GET_READ);
2022-02-23 19:26:02 +01:00
}
2022-05-05 16:46:04 +02:00
2023-02-26 14:55:33 +01:00
bool enableAside = true;
bool enableBside = true;
if (cfg.scheduleAcsBoard) {
if (enableAside) {
// A side
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_WRITE);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::GET_READ);
2023-02-26 14:55:33 +01:00
}
if (enableBside) {
// B side
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_READ);
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_WRITE);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::GET_READ);
2023-02-26 14:55:33 +01:00
}
if (enableAside) {
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_WRITE);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::GET_READ);
2023-02-26 14:55:33 +01:00
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_READ);
}
if (enableBside) {
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
2023-03-01 23:17:33 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
DeviceHandlerIF::GET_WRITE);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::SEND_READ);
2023-02-26 14:55:33 +01:00
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
2023-03-02 15:05:12 +01:00
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
DeviceHandlerIF::GET_READ);
2023-02-26 14:55:33 +01:00
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-26 14:55:33 +01:00
DeviceHandlerIF::GET_READ);
}
}
2023-02-08 16:46:30 +01:00
if (cfg.scheduleImtq) {
// This is the MTM measurement cycle
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::DHB_OP);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::START_MEASURE_SEND);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::START_MEASURE_GET);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::READ_MEASURE_SEND);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::READ_MEASURE_GET);
2022-02-23 19:26:02 +01:00
}
2022-01-18 11:41:19 +01:00
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::ACS_CONTROLLER, length * config::spiSched::SCHED_BLOCK_4_PERIOD,
0);
2022-05-05 16:46:04 +02:00
2023-02-08 16:46:30 +01:00
if (cfg.scheduleImtq) {
// This is the torquing cycle.
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::START_ACTUATE_SEND);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::START_ACTUATE_GET);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::READ_ACTUATE_SEND);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
2023-02-20 19:35:36 +01:00
imtq::ComStep::READ_ACTUATE_GET);
2022-02-23 19:26:02 +01:00
}
2022-01-18 11:41:19 +01:00
2023-02-13 10:42:05 +01:00
if (cfg.scheduleRws) {
// this is the torquing cycle
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::SEND_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
2023-02-13 10:42:05 +01:00
DeviceHandlerIF::GET_WRITE);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2022-05-05 16:46:04 +02:00
DeviceHandlerIF::SEND_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::SEND_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2022-05-05 16:46:04 +02:00
DeviceHandlerIF::SEND_READ);
2023-02-08 16:45:19 +01:00
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::GET_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::GET_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::GET_READ);
2023-03-01 23:17:33 +01:00
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
2023-02-08 16:46:30 +01:00
DeviceHandlerIF::GET_READ);
2023-02-08 16:45:19 +01:00
}
2023-02-13 16:10:58 +01:00
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::SPI_RTD_COM_IF, length * config::spiSched::SCHED_BLOCK_RTD_PERIOD,
0);
2023-02-13 16:10:58 +01:00
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::GET_READ);
2023-03-17 16:27:00 +01:00
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::PERFORM_OPERATION);
2023-03-17 18:20:41 +01:00
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::GET_READ);
2023-03-01 23:17:33 +01:00
#if OBSW_ADD_RAD_SENSORS == 1
/* Radiation sensor */
2023-03-02 15:05:12 +01:00
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::PERFORM_OPERATION);
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::SEND_WRITE);
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::GET_WRITE);
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::SEND_READ);
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
DeviceHandlerIF::GET_READ);
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#endif
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return returnvalue::OK;
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}