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d3af5e1519
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additional adjustment to xil_eth
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2024-10-17 14:00:32 +02:00 |
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6ff33beecc
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adjusting xil eth to work for us
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2024-10-14 14:15:07 +02:00 |
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fd2c5a544f
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xilinx eth lwip version xilinx_v2024.1
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2024-10-14 14:06:49 +02:00 |
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65299e46c4
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documentation
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2024-10-14 13:36:46 +02:00 |
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fb4b12c8f9
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xilinx ps7_cortexa9 code Version xilinx_v2024.1
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2024-10-14 13:36:25 +02:00 |
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dd9c39af30
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further cleanup
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2024-10-10 16:04:18 +02:00 |
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791428e6c0
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making the linker happy
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2024-10-07 16:55:20 +02:00 |
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944e45cad2
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refactoring, added second binary for sim interface, added second lwip implementation for sim interface
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2024-09-30 17:38:37 +02:00 |
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8fa5cddc23
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cleanup
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2024-09-09 17:37:41 +02:00 |
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44ffb09ee9
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ps7_init for zedboard
uart0 is 1000000 baud
uart1 is 230400 baud
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2024-09-09 16:28:27 +02:00 |
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5ad8853fef
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uart1 IO
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2024-08-29 14:48:16 +02:00 |
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8e7424bb2f
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io interface; relying on patched lwip
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2024-08-26 23:03:38 +02:00 |
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ee06c79bf4
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xilinx eth in own folder. found another bug/challenge with dma
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2024-08-26 12:03:31 +02:00 |
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8497fe754c
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cleanup
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2024-08-23 12:06:35 +02:00 |
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ae47ca8291
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found it. DMA can obviously not handle fragmented pbufs to receive packets. -> debug cleanup needed
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2024-08-22 18:14:51 +02:00 |
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497e380860
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RX working, still a bit messy
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2024-08-20 22:38:02 +02:00 |
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6c556b8fbf
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better, not done
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2024-08-20 15:13:03 +02:00 |
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2d8d8aeb0a
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working on RX, broke FreeRTOS
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2024-08-20 11:26:27 +02:00 |
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910553df45
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added xilinx lwip drivers, outgoing is working incoming TODO
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2024-08-19 16:52:10 +02:00 |
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fe5629fa85
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switched to UDP from UNIX Socket
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2024-08-02 01:05:11 +02:00 |
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926ef26000
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z7 uart0 buffered read
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2024-07-23 17:08:11 +02:00 |
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cbe8184fab
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portable device access api based on unix file descriptors
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2024-07-20 00:27:24 +02:00 |
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02a7d525be
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Using write() for output for better portability
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2024-07-16 14:12:15 +02:00 |
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976e079d02
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added freeRTOS on linux build
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2024-07-12 16:56:31 +02:00 |
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e585ecafcc
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adding mutexes, cleaning up types
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2023-12-11 22:44:06 +01:00 |
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96091b97af
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CMake Update
- Project name is now romeo-obsw
- ZYNQ_UART selects which Zynq PS UART is used for stdio
|
2023-12-01 13:44:42 +01:00 |
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c08d15215b
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too static, does not work
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2023-11-20 16:49:52 +01:00 |
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4782011fb8
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task demo (unsane)
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2023-11-14 01:26:35 +01:00 |
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701d3dca7f
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lwip without any alloc and sending and receiving UDP via slip
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2023-11-03 17:08:59 +01:00 |
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450eeede33
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lwip is back (using printf with malloc, but apart from that static)
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2023-11-03 11:58:56 +01:00 |
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baa7b8a96d
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no allocations anymore; lwip TODO
|
2023-10-28 00:37:06 +02:00 |
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a4bcbf64cc
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starting work on tmtcbridge
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2023-10-27 13:43:34 +02:00 |
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1eb406074c
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thread safety in newlib, newer lwip, optimized ISR for UART, some more stuff
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2023-10-06 17:29:07 +02:00 |
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1ba3d9412d
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tftp demo on uart0 (NSFZed)
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2023-09-28 22:52:18 +02:00 |
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8bca815cd2
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slip working with int driven rx
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2023-09-28 18:03:02 +02:00 |
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5c75cfa63a
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lwip both directions working
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2023-09-26 12:46:24 +02:00 |
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3697705319
|
removed features from ip stack that crash ip stack
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2023-09-25 14:27:23 +02:00 |
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69e14e14cf
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ip over slip outgoing works
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2023-09-22 16:38:05 +02:00 |
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2b6a8a501b
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WIP
|
2023-09-21 18:02:13 +02:00 |
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95c26b34c7
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zed goes blink
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2023-09-20 12:50:48 +02:00 |
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5a61af053b
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zedboard working
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2023-09-15 17:37:58 +02:00 |
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fb8f4a68e7
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starting fsfw
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2023-09-11 18:12:52 +02:00 |
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dcce9574c8
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changed to compile libxil as part of application, to be moved into lib
|
2023-09-11 17:26:42 +02:00 |
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08302ed7d4
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inertial commit, libxil built externally
|
2023-09-08 15:50:30 +02:00 |
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