prep patch v0.5.2

- Docs updated, internal architecture improvements

CHANGELOG.md

@@ -6,7 +6,34 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
-## [unreleased]
+## [v0.5.2] 2024-06-16
+
+## Fixed
+
+- Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
+  compilers.
+
+## [v0.5.1]
+
+### Changes
+
+- Updated dependencies:
+  - `cortex-m-rtic` (dev-depencency) to 1.1.2
+  - `once_cell` to 1.12.0
+  - Other dependencies: Only revision has changed
+
+## [v0.5.0]
+
+### Added
+
+- Reactored IRQ handling, so that `unmask` operations can be moved to HAL
+- Added UART IRQ handler. Right now, can only perform reception, TX still needs to be done in
+  a blocking manner
+- Added RTIC template and RTIC UART IRQ application
+
+### Fixed
+
+- Bugfix in UART code where RX and TX could not be enabled or disabled independently
 
 ## [v0.4.3]
 

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.4.3"
+version = "0.5.2"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -8,29 +8,43 @@ homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-hal"
 repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-hal"
 license = "Apache-2.0"
 keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
-categories = ["embedded", "no-std", "hardware-support"]
+categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
+va108xx = "0.2.4"
 cortex-m = "0.7"
 cortex-m-rt = "0.7"
 nb = "1"
 paste = "1.0"
-embedded-hal = { features = ["unproven"], version = "0.2.6" }
-void = { version = "1.0", default-features = false }
-once_cell = { version = "1.8.0", default-features = false }
-libm = "0.2.1"
+libm = "0.2"
 
-[dependencies.va108xx]
-version = "0.2.4"
+[dependencies.embedded-hal]
+version = "0.2.7"
+features = ["unproven"]
+
+[dependencies.void]
+version = "1.0"
+default-features = false
+
+[dependencies.once_cell]
+version = "1.14"
+default-features = false
 
 [features]
 rt = ["va108xx/rt"]
 
 [dev-dependencies]
-panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
-rtt-target = { version = "0.3", features = ["cortex-m"] }
+cortex-m-rtic = "1.1.2"
 panic-halt = "0.2"
 
+[dev-dependencies.rtt-target]
+version = "0.3"
+features = ["cortex-m"]
+
+[dev-dependencies.panic-rtt-target]
+version = "0.1"
+features = ["cortex-m"]
+
 [profile.dev]
 debug = true
 lto = false
@@ -55,9 +69,9 @@ name = "tests"
 required-features = ["rt"]
 
 [[example]]
-name = "pwm"
+name = "cascade"
 required-features = ["rt"]
 
 [[example]]
-name = "cascade"
+name = "uart-irq-rtic"
 required-features = ["rt"]

README.md

@@ -1,5 +1,5 @@
 [![Crates.io](https://img.shields.io/crates/v/va108xx-hal)](https://crates.io/crates/va108xx-hal)
-[![ci](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-hal-rs/actions/workflows/ci.yml)
+[![ci](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-hal-rs/actions/workflows/ci.yml)
 [![docs.rs](https://img.shields.io/docsrs/va108xx-hal)](https://docs.rs/va108xx-hal)
 
 # HAL for the Vorago VA108xx MCU family
@@ -63,7 +63,7 @@ is contained within the
 
 1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building)
 2. Create a new binary crate with `cargo init`
-3. To ensure that `cargo build` cross-compiles, it is recommended to create a `cargo/config.toml`
+3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml`
    file. A sample `.cargo/config.toml` file is provided in this repository as well
 4. Copy the `memory.x` file into your project. This file contains information required by the linker.
 5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate

automation/Dockerfile

@@ -7,5 +7,7 @@ RUN apt-get --yes upgrade
 # tzdata is a dependency, won't install otherwise
 ARG DEBIAN_FRONTEND=noninteractive
 
-RUN rustup target add thumbv6m-none-eabi && \
+RUN rustup install nightly && \
+	rustup target add thumbv6m-none-eabi && \
+	rustup +nightly target add thumbv6m-none-eabi && \
 	rustup component add rustfmt clippy

automation/Jenkinsfile

@@ -1,47 +1,34 @@
 pipeline {
-    agent any
+    agent {
+        dockerfile {
+            dir 'automation'
+            reuseNode true
+        }
+    }
+
 
     stages {
         stage('Clippy') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo clippy'
             }
         }
         stage('Rustfmt') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo fmt'
             }
         }
-        stage('Check') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
+        stage('Docs') {
+            steps {
+                sh 'cargo +nightly doc'
             }
+        }
+        stage('Check') {
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi'
             }
         }
         stage('Check Examples') {
-            agent {
-                dockerfile {
-                    dir 'automation'
-                    reuseNode true
-                }
-            }
             steps {
                 sh 'cargo check --target thumbv6m-none-eabi --examples'
             }

examples/blinky.rs

@@ -9,7 +9,7 @@
 use cortex_m_rt::entry;
 use embedded_hal::digital::v2::ToggleableOutputPin;
 use panic_halt as _;
-use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::set_up_ms_timer};
+use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountDownTimer};
 
 #[entry]
 fn main() -> ! {
@@ -18,13 +18,7 @@ fn main() -> ! {
     let mut led1 = porta.pa10.into_push_pull_output();
     let mut led2 = porta.pa7.into_push_pull_output();
     let mut led3 = porta.pa6.into_push_pull_output();
-    let mut delay = set_up_ms_timer(
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        50.mhz().into(),
-        dp.TIM0,
-        pac::Interrupt::OC0,
-    );
+    let mut delay = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
     for _ in 0..10 {
         led1.set_low().ok();
         led2.set_low().ok();

examples/cascade.rs

@@ -14,8 +14,8 @@ use va108xx_hal::{
     pac::{self, interrupt, TIM4, TIM5},
     prelude::*,
     timer::{
-        default_ms_irq_handler, set_up_ms_timer, CascadeCtrl, CascadeSource, CountDownTimer, Delay,
-        Event,
+        default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
+        CountDownTimer, Event, IrqCfg,
     },
 };
 
@@ -28,23 +28,16 @@ fn main() -> ! {
     rprintln!("-- VA108xx Cascade example application--");
 
     let mut dp = pac::Peripherals::take().unwrap();
-    let timer = set_up_ms_timer(
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        50.mhz().into(),
-        dp.TIM0,
-        pac::Interrupt::OC0,
-    );
-    let mut delay = Delay::new(timer);
+    let mut delay = set_up_ms_delay_provider(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
 
     // Will be started periodically to trigger a cascade
     let mut cascade_triggerer =
         CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM3).auto_disable(true);
     cascade_triggerer.listen(
         Event::TimeOut,
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        va108xx::Interrupt::OC1,
+        IrqCfg::new(va108xx::Interrupt::OC1, true, false),
+        Some(&mut dp.IRQSEL),
+        Some(&mut dp.SYSCONFIG),
     );
 
     // First target for cascade
@@ -63,9 +56,9 @@ fn main() -> ! {
     // the timer expires
     cascade_target_1.listen(
         Event::TimeOut,
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        va108xx::Interrupt::OC2,
+        IrqCfg::new(va108xx::Interrupt::OC2, true, false),
+        Some(&mut dp.IRQSEL),
+        Some(&mut dp.SYSCONFIG),
     );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
@@ -89,9 +82,9 @@ fn main() -> ! {
     // the timer expires
     cascade_target_2.listen(
         Event::TimeOut,
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        va108xx::Interrupt::OC3,
+        IrqCfg::new(va108xx::Interrupt::OC3, true, false),
+        Some(&mut dp.IRQSEL),
+        Some(&mut dp.SYSCONFIG),
     );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
@@ -112,7 +105,7 @@ fn main() -> ! {
     loop {
         rprintln!("-- Triggering cascade in 0.5 seconds --");
         cascade_triggerer.start(2.hz());
-        delay.delay_ms(5000);
+        delay.delay_ms(5000_u16);
     }
 }
 

examples/pwm.rs

@@ -8,10 +8,10 @@ use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
     gpio::PinsA,
-    pac::{self, interrupt},
+    pac,
     prelude::*,
     pwm::{self, get_duty_from_percent, ReducedPwmPin, PWMA, PWMB},
-    timer::{default_ms_irq_handler, set_up_ms_timer, Delay},
+    timer::set_up_ms_delay_provider,
 };
 
 #[entry]
@@ -26,17 +26,7 @@ fn main() -> ! {
         &mut dp.SYSCONFIG,
         10.hz(),
     );
-    let timer = set_up_ms_timer(
-        &mut dp.SYSCONFIG,
-        &mut dp.IRQSEL,
-        50.mhz().into(),
-        dp.TIM0,
-        pac::Interrupt::OC0,
-    );
-    let mut delay = Delay::new(timer);
-    unsafe {
-        cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
-    }
+    let mut delay = set_up_ms_delay_provider(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
     let mut current_duty_cycle = 0.0;
     PwmPin::set_duty(&mut pwm, get_duty_from_percent(current_duty_cycle));
     PwmPin::enable(&mut pwm);
@@ -46,7 +36,7 @@ fn main() -> ! {
     loop {
         // Increase duty cycle continuously
         while current_duty_cycle < 1.0 {
-            delay.delay_ms(200);
+            delay.delay_ms(200_u16);
             current_duty_cycle += 0.02;
             PwmPin::set_duty(&mut reduced_pin, get_duty_from_percent(current_duty_cycle));
         }
@@ -60,7 +50,7 @@ fn main() -> ! {
         pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
         pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
         while lower_limit < 0.5 {
-            delay.delay_ms(200);
+            delay.delay_ms(200_u16);
             lower_limit += 0.01;
             upper_limit -= 0.01;
             pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
@@ -71,8 +61,3 @@ fn main() -> ! {
         reduced_pin = ReducedPwmPin::<PWMA>::from(pwmb);
     }
 }
-
-#[interrupt]
-fn OC0() {
-    default_ms_irq_handler()
-}

examples/rtic-empty.rs

@@ -0,0 +1,29 @@
+//! Empty RTIC project template
+#![no_main]
+#![no_std]
+
+#[rtic::app(device = pac)]
+mod app {
+    use panic_rtt_target as _;
+    use rtt_target::{rprintln, rtt_init_default};
+    use va108xx_hal::pac;
+
+    #[local]
+    struct Local {}
+
+    #[shared]
+    struct Shared {}
+
+    #[init]
+    fn init(_ctx: init::Context) -> (Shared, Local, init::Monotonics) {
+        rtt_init_default!();
+        rprintln!("-- Vorago RTIC template --");
+        (Shared {}, Local {}, init::Monotonics())
+    }
+
+    // `shared` cannot be accessed from this context
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        loop {}
+    }
+}

examples/tests.rs

@@ -14,7 +14,7 @@ use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Delay},
+    timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Delay, IrqCfg},
 };
 
 #[allow(dead_code)]
@@ -146,15 +146,12 @@ fn main() -> ! {
         }
         TestCase::DelayMs => {
             let ms_timer = set_up_ms_timer(
+                IrqCfg::new(pac::Interrupt::OC0, true, true),
                 &mut dp.SYSCONFIG,
-                &mut dp.IRQSEL,
-                50.mhz().into(),
+                Some(&mut dp.IRQSEL),
+                50.mhz(),
                 dp.TIM0,
-                pac::Interrupt::OC0,
             );
-            unsafe {
-                cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
-            }
             let mut delay = Delay::new(ms_timer);
             for _ in 0..5 {
                 led1.toggle().ok();
@@ -163,7 +160,7 @@ fn main() -> ! {
                 delay.delay_ms(500);
             }
 
-            let mut delay_timer = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
+            let mut delay_timer = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM1);
             let mut pa0 = pinsa.pa0.into_push_pull_output();
             for _ in 0..5 {
                 led1.toggle().ok();

examples/timer-ticks.rs

@@ -12,7 +12,7 @@ use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, MS_COUNTER},
+    timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, IrqCfg, MS_COUNTER},
 };
 
 #[allow(dead_code)]
@@ -65,22 +65,21 @@ fn main() -> ! {
         }
         LibType::Hal => {
             set_up_ms_timer(
+                IrqCfg::new(interrupt::OC0, true, true),
                 &mut dp.SYSCONFIG,
-                &mut dp.IRQSEL,
-                50.mhz().into(),
+                Some(&mut dp.IRQSEL),
+                50.mhz(),
                 dp.TIM0,
-                interrupt::OC0,
             );
             let mut second_timer =
                 CountDownTimer::new(&mut dp.SYSCONFIG, get_sys_clock().unwrap(), dp.TIM1);
             second_timer.listen(
                 Event::TimeOut,
-                &mut dp.SYSCONFIG,
-                &mut dp.IRQSEL,
-                interrupt::OC1,
+                IrqCfg::new(interrupt::OC1, true, true),
+                Some(&mut dp.IRQSEL),
+                Some(&mut dp.SYSCONFIG),
             );
             second_timer.start(1.hz());
-            unmask_irqs();
         }
     }
     loop {

examples/uart-irq-rtic.rs

@@ -0,0 +1,126 @@
+//! More complex UART application
+//!
+//! Uses the IRQ capabilities of the VA10820 peripheral and the RTIC framework to poll the UART in
+//! a non-blocking way. You can send variably sized strings to the VA10820 which will be echoed
+//! back to the sender.
+//!
+//! This script was tested with an Arduino Due. You can find the test script in the
+//! [`/test/DueSerialTest`](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/test/DueSerialTest)
+//! folder.
+#![no_main]
+#![no_std]
+
+#[rtic::app(device = pac, dispatchers = [OC4])]
+mod app {
+    use core::fmt::Write;
+    use panic_rtt_target as _;
+    use rtt_target::{rprintln, rtt_init_default, set_print_channel};
+    use va108xx_hal::{
+        gpio::PinsB,
+        pac,
+        prelude::*,
+        uart::{self, IrqCfg, IrqResult, UartWithIrqBase},
+    };
+
+    #[local]
+    struct Local {}
+
+    #[shared]
+    struct Shared {
+        irq_uart: UartWithIrqBase<pac::UARTB>,
+        rx_buf: [u8; 64],
+    }
+
+    #[init]
+    fn init(ctx: init::Context) -> (Shared, Local, init::Monotonics) {
+        let channels = rtt_init_default!();
+        set_print_channel(channels.up.0);
+        rprintln!("-- VA108xx UART IRQ example application--");
+        let mut dp = ctx.device;
+        let gpiob = PinsB::new(&mut dp.SYSCONFIG, Some(dp.IOCONFIG), dp.PORTB);
+        let tx = gpiob.pb21.into_funsel_1();
+        let rx = gpiob.pb20.into_funsel_1();
+
+        let irq_cfg = IrqCfg::new(pac::interrupt::OC3, true, true);
+        let (mut irq_uart, _) = uart::Uart::uartb(
+            dp.UARTB,
+            (tx, rx),
+            115200.bps(),
+            &mut dp.SYSCONFIG,
+            50.mhz(),
+        )
+        .into_uart_with_irq(irq_cfg, Some(&mut dp.SYSCONFIG), Some(&mut dp.IRQSEL))
+        .downgrade();
+        irq_uart
+            .read_fixed_len_using_irq(64, true)
+            .expect("Read initialization failed");
+        let rx_buf: [u8; 64] = [0; 64];
+        (Shared { irq_uart, rx_buf }, Local {}, init::Monotonics())
+    }
+
+    // `shared` cannot be accessed from this context
+    #[idle]
+    fn idle(_cx: idle::Context) -> ! {
+        loop {}
+    }
+
+    #[task(
+        binds = OC3,
+        shared = [irq_uart, rx_buf],
+        local = [cnt: u32 = 0, result: IrqResult = IrqResult::new()],
+        priority = 4
+    )]
+    fn reception_task(cx: reception_task::Context) {
+        let result = cx.local.result;
+        let cnt: &mut u32 = cx.local.cnt;
+        let irq_uart = cx.shared.irq_uart;
+        let rx_buf = cx.shared.rx_buf;
+        let (completed, end_idx) = (irq_uart, rx_buf).lock(|irq_uart, rx_buf| {
+            match irq_uart.irq_handler(result, rx_buf) {
+                Ok(_) => {
+                    if result.complete() {
+                        // Initiate next transfer immediately
+                        irq_uart
+                            .read_fixed_len_using_irq(64, true)
+                            .expect("Read operation init failed");
+
+                        let mut end_idx = 0;
+                        for idx in 0..rx_buf.len() {
+                            if (rx_buf[idx] as char) == '\n' {
+                                end_idx = idx;
+                                break;
+                            }
+                        }
+                        (true, end_idx)
+                    } else {
+                        (false, 0)
+                    }
+                }
+                Err(e) => {
+                    rprintln!("Reception Error {:?}", e);
+                    (false, 0)
+                }
+            }
+        });
+        if completed {
+            rprintln!("Counter: {}", cnt);
+            reply_handler::spawn(result.bytes_read, end_idx, result.timeout()).unwrap();
+        }
+        *cnt += 1;
+    }
+
+    #[task(shared = [irq_uart, rx_buf], priority = 3)]
+    fn reply_handler(cx: reply_handler::Context, bytes_read: usize, end_idx: usize, timeout: bool) {
+        let irq_uart = cx.shared.irq_uart;
+        let rx_buf = cx.shared.rx_buf;
+        (irq_uart, rx_buf).lock(|irq_uart, rx_buf| {
+            rprintln!("Reception success, {} bytes read", bytes_read);
+            if timeout {
+                rprintln!("Timeout occured");
+            }
+            let string = core::str::from_utf8(&rx_buf[0..end_idx]).expect("Invalid string format");
+            rprintln!("Read string: {}", string);
+            writeln!(irq_uart.uart, "{}", string).expect("Sending reply failed");
+        });
+    }
+}

src/clock.rs

@@ -11,7 +11,7 @@ static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
 
 pub type PeripheralClocks = PeripheralSelect;
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterClkSel {
     SysClk = 0,
     Clk1 = 1,
@@ -50,12 +50,14 @@ pub fn set_clk_div_register(syscfg: &mut SYSCONFIG, clk_sel: FilterClkSel, div:
     }
 }
 
+#[inline]
 pub fn enable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralClocks) {
     syscfg
         .peripheral_clk_enable
         .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
 }
 
+#[inline]
 pub fn disable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralClocks) {
     syscfg
         .peripheral_clk_enable

src/gpio/dynpins.rs

@@ -66,8 +66,8 @@ use super::{
 };
 use crate::{
     clock::FilterClkSel,
-    pac::{self, IRQSEL, SYSCONFIG},
-    utility::Funsel,
+    pac::{IRQSEL, SYSCONFIG},
+    utility::{Funsel, IrqCfg},
 };
 use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
 use paste::paste;
@@ -143,14 +143,14 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Funse
 //==================================================================================================
 
 /// Value-level `enum` for pin groups
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub enum DynGroup {
     A,
     B,
 }
 
 /// Value-level `struct` representing pin IDs
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub struct DynPinId {
     pub group: DynGroup,
     pub num: u8,
@@ -344,14 +344,14 @@ impl DynPin {
     pub fn interrupt_edge(
         mut self,
         edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Result<Self, PinError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
-                self._irq_enb(syscfg, irqsel, interrupt);
                 self.regs.interrupt_edge(edge_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
                 Ok(self)
             }
             _ => Err(PinError::InvalidPinType),
@@ -361,14 +361,14 @@ impl DynPin {
     pub fn interrupt_level(
         mut self,
         level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: crate::pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Result<Self, PinError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
-                self._irq_enb(syscfg, irqsel, interrupt);
                 self.regs.interrupt_level(level_type);
+                self.irq_enb(irq_cfg, syscfg, irqsel);
                 Ok(self)
             }
             _ => Err(PinError::InvalidPinType),

src/gpio/pins.rs

@@ -92,8 +92,9 @@
 use super::dynpins::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
 use super::reg::RegisterInterface;
 use crate::{
-    pac::{self, IOCONFIG, IRQSEL, PORTA, PORTB, SYSCONFIG},
+    pac::{IOCONFIG, IRQSEL, PORTA, PORTB, SYSCONFIG},
     typelevel::Is,
+    utility::IrqCfg,
     Sealed,
 };
 use core::convert::Infallible;
@@ -105,27 +106,27 @@ use paste::paste;
 //  Errors and Definitions
 //==================================================================================================
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptEdge {
     HighToLow,
     LowToHigh,
     BothEdges,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptLevel {
     Low = 0,
     High = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinState {
     Low = 0,
     High = 1,
 }
 
 /// GPIO error type
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinError {
     /// The pin did not have the correct ID or mode for the requested operation.
     /// [`DynPin`](crate::gpio::DynPin)s are not tracked and verified at compile-time, so run-time
@@ -181,7 +182,7 @@ pub struct Input<C: InputConfig> {
 
 impl<C: InputConfig> Sealed for Input<C> {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterType {
     SystemClock = 0,
     DirectInputWithSynchronization = 1,
@@ -397,11 +398,11 @@ macro_rules! common_reg_if_functions {
                 self.regs.write_pin_masked(false)
             }
 
-            fn _irq_enb(
+            fn irq_enb(
                 &mut self,
+                irq_cfg: crate::utility::IrqCfg,
                 syscfg: Option<&mut va108xx::SYSCONFIG>,
-                irqsel: &mut va108xx::IRQSEL,
-                interrupt: va108xx::Interrupt,
+                irqsel: Option<&mut va108xx::IRQSEL>,
             ) {
                 if syscfg.is_some() {
                     crate::clock::enable_peripheral_clock(
@@ -410,15 +411,19 @@ macro_rules! common_reg_if_functions {
                     );
                 }
                 self.regs.enable_irq();
-                match self.regs.id().group {
-                    // Set the correct interrupt number in the IRQSEL register
-                    DynGroup::A => {
-                        irqsel.porta[self.regs.id().num as usize]
-                            .write(|w| unsafe { w.bits(interrupt as u32) });
-                    }
-                    DynGroup::B => {
-                        irqsel.portb[self.regs.id().num as usize]
-                            .write(|w| unsafe { w.bits(interrupt as u32) });
+                if let Some(irqsel) = irqsel {
+                    if irq_cfg.route {
+                        match self.regs.id().group {
+                            // Set the correct interrupt number in the IRQSEL register
+                            DynGroup::A => {
+                                irqsel.porta[self.regs.id().num as usize]
+                                    .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                            }
+                            DynGroup::B => {
+                                irqsel.portb[self.regs.id().num as usize]
+                                    .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                            }
+                        }
                     }
                 }
             }
@@ -577,24 +582,24 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
     pub fn interrupt_edge(
         mut self,
         edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
-        self._irq_enb(syscfg, irqsel, interrupt);
         self.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
         self
     }
 
     pub fn interrupt_level(
         mut self,
         level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
-        self._irq_enb(syscfg, irqsel, interrupt);
         self.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
         self
     }
 }
@@ -622,24 +627,24 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
     pub fn interrupt_edge(
         mut self,
         edge_type: InterruptEdge,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
-        self._irq_enb(syscfg, irqsel, interrupt);
         self.regs.interrupt_edge(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
         self
     }
 
     pub fn interrupt_level(
         mut self,
         level_type: InterruptLevel,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut SYSCONFIG>,
-        irqsel: &mut IRQSEL,
-        interrupt: pac::Interrupt,
+        irqsel: Option<&mut IRQSEL>,
     ) -> Self {
-        self._irq_enb(syscfg, irqsel, interrupt);
         self.regs.interrupt_level(level_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
         self
     }
 }

src/i2c.rs

@@ -18,13 +18,13 @@ pub use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress};
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum FifoEmptyMode {
     Stall = 0,
     EndTransaction = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum Error {
     InvalidTimingParams,
     ArbitrationLost,
@@ -46,19 +46,19 @@ enum I2cCmd {
     Cancel = 0b100,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cSpeed {
     Regular100khz = 0,
     Fast400khz = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum I2cDirection {
     Send = 0,
     Read = 1,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cAddress {
     Regular(u8),
     TenBit(u16),
@@ -119,14 +119,14 @@ impl TimingCfg {
     }
 
     pub fn reg(&self) -> u32 {
-        ((self.tbuf as u32) << 28
+        (self.tbuf as u32) << 28
             | (self.thd_sta as u32) << 24
             | (self.tsu_sta as u32) << 20
             | (self.tsu_sto as u32) << 16
             | (self.tlow as u32) << 12
             | (self.thigh as u32) << 8
             | (self.tf as u32) << 4
-            | (self.tr as u32)) as u32
+            | (self.tr as u32)
     }
 }
 

src/spi.rs

@@ -25,7 +25,7 @@ use embedded_hal::{
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum HwChipSelectId {
     Id0 = 0,
     Id1 = 1,
@@ -38,7 +38,7 @@ pub enum HwChipSelectId {
     Invalid = 0xff,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum WordSize {
     OneBit = 0x00,
     FourBits = 0x03,

src/time.rs

@@ -6,7 +6,7 @@
 //! allowing it to be converted into frequencies.
 
 /// Bits per second
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Bps(pub u32);
 
 /// Hertz
@@ -25,7 +25,7 @@ pub struct Bps(pub u32);
 ///
 /// let freq = 60.hz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Hertz(pub u32);
 
 /// Kilohertz
@@ -47,7 +47,7 @@ pub struct Hertz(pub u32);
 ///
 /// let freq = 100.khz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct KiloHertz(pub u32);
 
 /// Megahertz
@@ -68,14 +68,14 @@ pub struct KiloHertz(pub u32);
 ///
 /// let freq = 8.mhz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct MegaHertz(pub u32);
 
 /// Time unit
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MilliSeconds(pub u32);
 
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MicroSeconds(pub u32);
 
 /// Extension trait that adds convenience methods to the `u32` type

src/timer.rs

@@ -4,6 +4,7 @@
 //!
 //! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/timer-ticks.rs)
 //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/cascade.rs)
+pub use crate::utility::IrqCfg;
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
     gpio::{
@@ -20,6 +21,7 @@ use crate::{
     private::Sealed,
     time::Hertz,
     timer,
+    utility::unmask_irq,
 };
 use core::cell::Cell;
 use cortex_m::interrupt::Mutex;
@@ -27,7 +29,7 @@ use embedded_hal::{
     blocking::delay,
     timer::{Cancel, CountDown, Periodic},
 };
-use va108xx::{Interrupt, IRQSEL, SYSCONFIG};
+use va108xx::{IRQSEL, SYSCONFIG};
 use void::Void;
 
 const IRQ_DST_NONE: u32 = 0xffffffff;
@@ -43,7 +45,7 @@ pub enum Event {
     TimeOut,
 }
 
-#[derive(Default, Debug, PartialEq, Copy, Clone)]
+#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
 pub struct CascadeCtrl {
     /// Enable Cascade 0 signal active as a requirement for counting
     pub enb_start_src_csd0: bool,
@@ -72,7 +74,7 @@ pub struct CascadeCtrl {
     pub trg_csd2: bool,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSel {
     Csd0 = 0,
     Csd1 = 1,
@@ -80,7 +82,7 @@ pub enum CascadeSel {
 }
 
 /// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSource {
     PortABase = 0,
     PortBBase = 32,
@@ -93,7 +95,7 @@ pub enum CascadeSource {
     ClockDividerBase = 120,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum TimerErrors {
     Canceled,
     /// Invalid input for Cascade source
@@ -386,6 +388,7 @@ unsafe impl TimPinInterface for TimDynRegister {
 pub struct CountDownTimer<TIM: ValidTim> {
     tim: TimRegister<TIM>,
     curr_freq: Hertz,
+    irq_cfg: Option<IrqCfg>,
     sys_clk: Hertz,
     rst_val: u32,
     last_cnt: u32,
@@ -482,6 +485,7 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
         let cd_timer = CountDownTimer {
             tim: unsafe { TimRegister::new(tim) },
             sys_clk: sys_clk.into(),
+            irq_cfg: None,
             rst_val: 0,
             curr_freq: 0.hz(),
             listening: false,
@@ -491,21 +495,28 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
         cd_timer
     }
 
-    /// Listen for events. This also actives the IRQ in the IRQSEL register
-    /// for the provided interrupt. It also actives the peripheral clock for
-    /// IRQSEL
+    /// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the
+    /// IRQSEL peripheral for the provided interrupt and unmasks the interrupt
     pub fn listen(
         &mut self,
         event: Event,
-        syscfg: &mut SYSCONFIG,
-        irqsel: &mut IRQSEL,
-        interrupt: Interrupt,
+        irq_cfg: IrqCfg,
+        irq_sel: Option<&mut IRQSEL>,
+        sys_cfg: Option<&mut SYSCONFIG>,
     ) {
         match event {
             Event::TimeOut => {
-                enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
-                irqsel.tim[TIM::TIM_ID as usize].write(|w| unsafe { w.bits(interrupt as u32) });
-                self.enable_interrupt();
+                cortex_m::peripheral::NVIC::mask(irq_cfg.irq);
+                self.irq_cfg = Some(irq_cfg);
+                if irq_cfg.route {
+                    if let Some(sys_cfg) = sys_cfg {
+                        enable_peripheral_clock(sys_cfg, PeripheralClocks::Irqsel);
+                    }
+                    if let Some(irq_sel) = irq_sel {
+                        irq_sel.tim[TIM::TIM_ID as usize]
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
+                    }
+                }
                 self.listening = true;
             }
         }
@@ -554,6 +565,12 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
     #[inline(always)]
     pub fn enable(&mut self) {
         self.tim.reg().ctrl.modify(|_, w| w.enable().set_bit());
+        if let Some(irq_cfg) = self.irq_cfg {
+            self.enable_interrupt();
+            if irq_cfg.enable {
+                unmask_irq(irq_cfg.irq);
+            }
+        }
     }
 
     #[inline(always)]