2023-02-23 11:57:12 +01:00
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#include "pollingSeqTables.h"
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2021-05-17 16:53:06 +02:00
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2022-01-18 11:41:19 +01:00
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#include <fsfw/devicehandlers/DeviceHandlerIF.h>
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2021-03-22 13:09:06 +01:00
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#include <fsfw/objectmanager/ObjectManagerIF.h>
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#include <fsfw/serviceinterface/ServiceInterfaceStream.h>
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#include <fsfw/tasks/FixedTimeslotTaskIF.h>
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2023-03-24 20:50:33 +01:00
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#include <mission/acs/imtqHelpers.h>
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2023-03-26 16:42:00 +02:00
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#include <mission/tcs/Max31865Definitions.h>
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2021-03-22 13:09:06 +01:00
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2023-02-14 14:29:47 +01:00
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#include "OBSWConfig.h"
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2023-02-08 16:46:30 +01:00
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#include "eive/definitions.h"
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2023-11-14 13:25:53 +01:00
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#include "eive/objects.h"
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#include "linux/payload/FreshSupvHandler.h"
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2022-05-14 09:41:28 +02:00
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2022-03-08 09:37:23 +01:00
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#ifndef RPI_TEST_ADIS16507
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#define RPI_TEST_ADIS16507 0
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#endif
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2021-03-22 13:09:06 +01:00
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2022-03-08 09:37:23 +01:00
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#ifndef RPI_TEST_GPS_HANDLER
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#define RPI_TEST_GPS_HANDLER 0
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#endif
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2021-06-23 15:18:31 +02:00
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2023-03-13 11:34:51 +01:00
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ReturnValue_t pst::pstSyrlinks(FixedTimeslotTaskIF *thisSequence) {
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2022-01-18 11:41:19 +01:00
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uint32_t length = thisSequence->getPeriodMs();
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2023-02-03 15:02:08 +01:00
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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2023-03-24 01:19:08 +01:00
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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2023-03-24 02:34:38 +01:00
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.25, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.25, DeviceHandlerIF::GET_READ);
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2023-04-04 16:46:07 +02:00
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2023-03-24 02:34:38 +01:00
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.4, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.4, DeviceHandlerIF::GET_WRITE);
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2023-03-31 12:11:31 +02:00
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.75, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::SYRLINKS_HANDLER, length * 0.75, DeviceHandlerIF::GET_READ);
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2023-02-03 15:02:08 +01:00
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2022-01-18 11:41:19 +01:00
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static_cast<void>(length);
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2023-02-02 17:06:26 +01:00
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return thisSequence->checkSequence();
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}
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// I don't think this needs to be in a PST because linux takes care of bus serialization, but
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// keep it like this for now, it works
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2023-07-06 14:34:12 +02:00
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ReturnValue_t pst::pstI2c(TmpSchedConfig schedConf, FixedTimeslotTaskIF *thisSequence) {
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2023-02-02 17:06:26 +01:00
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// Length of a communication cycle
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uint32_t length = thisSequence->getPeriodMs();
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static_cast<void>(length);
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2023-03-14 10:54:44 +01:00
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2023-06-17 15:28:05 +02:00
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if (schedConf.scheduleTmpDev0) {
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::PERFORM_OPERATION);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.1, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.1, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_0, length * 0.1, DeviceHandlerIF::GET_READ);
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2023-06-17 15:28:05 +02:00
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}
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2023-03-14 10:54:44 +01:00
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2023-06-17 15:28:05 +02:00
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if (schedConf.scheduleTmpDev1) {
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.2,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::PERFORM_OPERATION);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.2,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::SEND_WRITE);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.2, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.3, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_TCS_1, length * 0.3, DeviceHandlerIF::GET_READ);
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2023-06-17 15:28:05 +02:00
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}
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2023-03-14 10:54:44 +01:00
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2023-06-17 15:28:05 +02:00
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if (schedConf.schedulePlPcduDev0) {
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.4,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::PERFORM_OPERATION);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.4,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::SEND_WRITE);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.4,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::GET_WRITE);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.5,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::SEND_READ);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_0, length * 0.5,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::GET_READ);
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}
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if (schedConf.schedulePlPcduDev1) {
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.6,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::PERFORM_OPERATION);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.6,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::SEND_WRITE);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.6,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::GET_WRITE);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.7,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::SEND_READ);
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2023-06-17 17:01:01 +02:00
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thisSequence->addSlot(objects::TMP1075_HANDLER_PLPCDU_1, length * 0.7,
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2023-06-17 15:28:05 +02:00
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DeviceHandlerIF::GET_READ);
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}
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if (schedConf.scheduleIfBoardDev) {
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.8,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.9,
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DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::TMP1075_HANDLER_IF_BOARD, length * 0.9,
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DeviceHandlerIF::GET_READ);
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}
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2023-02-02 17:06:26 +01:00
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static_cast<void>(length);
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return thisSequence->checkSequence();
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}
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ReturnValue_t pst::pstGompaceCan(FixedTimeslotTaskIF *thisSequence) {
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uint32_t length = thisSequence->getPeriodMs();
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// PCDU handlers receives two messages and both must be handled
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thisSequence->addSlot(objects::PCDU_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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2023-04-01 15:06:21 +02:00
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::PDU1_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::PDU2_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::ACU_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
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2023-04-04 20:36:52 +02:00
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::ACU_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
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2023-04-01 15:06:21 +02:00
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2023-04-04 16:46:07 +02:00
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thisSequence->addSlot(objects::P60DOCK_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::PDU1_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::PDU2_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::ACU_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
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2023-07-26 17:01:48 +02:00
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2023-02-02 17:06:26 +01:00
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if (thisSequence->checkSequence() != returnvalue::OK) {
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sif::error << "GomSpace PST initialization failed" << std::endl;
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return returnvalue::FAILED;
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}
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static_cast<void>(length);
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return returnvalue::OK;
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}
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ReturnValue_t pst::pstTest(FixedTimeslotTaskIF *thisSequence) {
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/* Length of a communication cycle */
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uint32_t length = thisSequence->getPeriodMs();
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bool notEmpty = false;
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#if RPI_TEST_ADIS16507 == 1
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notEmpty = true;
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thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.2, DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.4, DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.6, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER, length * 0.8, DeviceHandlerIF::GET_READ);
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#endif
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#if RPI_TEST_GPS_HANDLER == 1
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notEmpty = true;
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thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::GPS0_HANDLER, length * 0, DeviceHandlerIF::GET_READ);
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thisSequence->addSlot(objects::GPS0_HANDLER, length * 0.5, DeviceHandlerIF::SEND_READ);
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thisSequence->addSlot(objects::GPS0_HANDLER, length * 0.5, DeviceHandlerIF::GET_READ);
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#endif
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static_cast<void>(length);
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if (not notEmpty) {
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return returnvalue::FAILED;
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}
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if (thisSequence->checkSequence() != returnvalue::OK) {
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sif::error << "Test PST initialization failed" << std::endl;
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return returnvalue::FAILED;
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}
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return returnvalue::OK;
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}
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2023-02-13 15:37:42 +01:00
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ReturnValue_t pst::pstTcsAndAcs(FixedTimeslotTaskIF *thisSequence, AcsPstCfg cfg) {
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2023-02-02 17:06:26 +01:00
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/* Length of a communication cycle */
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uint32_t length = thisSequence->getPeriodMs();
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2023-02-08 16:46:30 +01:00
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2023-02-02 17:06:26 +01:00
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// SUS: 16 ms
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2023-02-08 16:46:30 +01:00
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if (cfg.scheduleSus) {
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2023-03-01 16:36:21 +01:00
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/* Write setup */
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thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
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DeviceHandlerIF::SEND_WRITE);
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thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB, length * 0,
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DeviceHandlerIF::GET_WRITE);
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thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
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DeviceHandlerIF::PERFORM_OPERATION);
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thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
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DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB, length * 0,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
|
|
|
|
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 16:36:21 +01:00
|
|
|
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2022-02-23 19:26:02 +01:00
|
|
|
}
|
2022-05-05 16:46:04 +02:00
|
|
|
|
2023-02-08 16:46:30 +01:00
|
|
|
if (cfg.scheduleStr) {
|
2023-03-22 02:20:14 +01:00
|
|
|
// 2 COM cycles for full PST for STR. The STR requests 2 packets types in NORMAL mode, this
|
|
|
|
// ensures we always get an updated STR dataset for a regular normal mode cycle.
|
2023-02-08 16:46:30 +01:00
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * 0, DeviceHandlerIF::GET_WRITE);
|
2023-03-22 02:20:14 +01:00
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::STAR_TRACKER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2022-02-23 19:26:02 +01:00
|
|
|
}
|
2022-05-05 16:46:04 +02:00
|
|
|
|
2023-02-26 14:55:33 +01:00
|
|
|
bool enableAside = true;
|
|
|
|
bool enableBside = true;
|
|
|
|
if (cfg.scheduleAcsBoard) {
|
|
|
|
if (enableAside) {
|
|
|
|
// A side
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
|
|
|
|
|
|
|
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
}
|
|
|
|
if (enableBside) {
|
|
|
|
// B side
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
|
|
|
|
|
|
|
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
}
|
|
|
|
if (enableAside) {
|
|
|
|
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
|
|
|
}
|
|
|
|
if (enableBside) {
|
|
|
|
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
2023-03-01 23:17:33 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
2023-03-02 15:05:12 +01:00
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-02-26 14:55:33 +01:00
|
|
|
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER,
|
|
|
|
length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-26 14:55:33 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-02-08 16:46:30 +01:00
|
|
|
if (cfg.scheduleImtq) {
|
|
|
|
// This is the MTM measurement cycle
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::DHB_OP);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::START_MEASURE_SEND);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::START_MEASURE_GET);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::READ_MEASURE_SEND);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::READ_MEASURE_GET);
|
2022-02-23 19:26:02 +01:00
|
|
|
}
|
2022-01-18 11:41:19 +01:00
|
|
|
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::ACS_CONTROLLER, length * config::spiSched::SCHED_BLOCK_4_PERIOD,
|
|
|
|
0);
|
2022-05-05 16:46:04 +02:00
|
|
|
|
2023-02-08 16:46:30 +01:00
|
|
|
if (cfg.scheduleImtq) {
|
|
|
|
// This is the torquing cycle.
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::START_ACTUATE_SEND);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::START_ACTUATE_GET);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::READ_ACTUATE_SEND);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
|
2023-02-20 19:35:36 +01:00
|
|
|
imtq::ComStep::READ_ACTUATE_GET);
|
2022-02-23 19:26:02 +01:00
|
|
|
}
|
2022-01-18 11:41:19 +01:00
|
|
|
|
2023-02-13 10:42:05 +01:00
|
|
|
if (cfg.scheduleRws) {
|
|
|
|
// this is the torquing cycle
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
2023-02-13 10:42:05 +01:00
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2022-05-05 16:46:04 +02:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2022-05-05 16:46:04 +02:00
|
|
|
DeviceHandlerIF::SEND_READ);
|
2023-02-08 16:45:19 +01:00
|
|
|
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
2023-02-08 16:46:30 +01:00
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-02-08 16:45:19 +01:00
|
|
|
}
|
2023-02-13 16:10:58 +01:00
|
|
|
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::SPI_RTD_COM_IF, length * config::spiSched::SCHED_BLOCK_RTD_PERIOD,
|
|
|
|
0);
|
2023-02-13 16:10:58 +01:00
|
|
|
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-17 16:27:00 +01:00
|
|
|
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
2023-03-17 18:20:41 +01:00
|
|
|
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::BPX_BATT_HANDLER, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-03-01 23:17:33 +01:00
|
|
|
|
|
|
|
/* Radiation sensor */
|
2023-03-02 15:05:12 +01:00
|
|
|
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD,
|
|
|
|
DeviceHandlerIF::GET_READ);
|
2023-09-28 13:09:53 +02:00
|
|
|
|
|
|
|
thisSequence->addSlot(objects::POWER_CONTROLLER, length * config::spiSched::SCHED_BLOCK_10_PERIOD,
|
|
|
|
0);
|
2022-08-24 17:27:47 +02:00
|
|
|
return returnvalue::OK;
|
2021-03-22 13:09:06 +01:00
|
|
|
}
|
2023-11-14 13:25:53 +01:00
|
|
|
ReturnValue_t pst::pstPayload(FixedTimeslotTaskIF *thisSequence) {
|
|
|
|
uint32_t length = thisSequence->getPeriodMs();
|
|
|
|
|
|
|
|
thisSequence->addSlot(objects::CAM_SWITCHER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::PLOC_MPSOC_HANDLER, length * 0,
|
|
|
|
DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::PLOC_MPSOC_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::PLOC_MPSOC_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::PLOC_MPSOC_HANDLER, length * 0, DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::PLOC_MPSOC_HANDLER, length * 0, DeviceHandlerIF::GET_READ);
|
|
|
|
|
|
|
|
thisSequence->addSlot(objects::PLOC_SUPERVISOR_HANDLER, length * 0,
|
|
|
|
FreshSupvHandler::OpCode::DEFAULT_OPERATION);
|
2023-11-15 11:33:53 +01:00
|
|
|
// Two COM TM steps, which might cover telemetry which takes a bit longer to be sent.
|
2023-11-14 13:25:53 +01:00
|
|
|
thisSequence->addSlot(objects::PLOC_SUPERVISOR_HANDLER, length * 0.1,
|
|
|
|
FreshSupvHandler::OpCode::PARSE_TM);
|
|
|
|
thisSequence->addSlot(objects::PLOC_SUPERVISOR_HANDLER, length * 0.2,
|
|
|
|
FreshSupvHandler::OpCode::PARSE_TM);
|
|
|
|
|
2023-12-06 11:31:39 +01:00
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.6, DeviceHandlerIF::PERFORM_OPERATION);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.6, DeviceHandlerIF::SEND_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.6, DeviceHandlerIF::GET_WRITE);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.6, DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.6, DeviceHandlerIF::GET_READ);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.8, DeviceHandlerIF::SEND_READ);
|
|
|
|
thisSequence->addSlot(objects::SCEX, length * 0.8, DeviceHandlerIF::GET_READ);
|
2023-11-14 13:25:53 +01:00
|
|
|
return thisSequence->checkSequence();
|
|
|
|
}
|