Commit Graph

40 Commits

Author SHA1 Message Date
dc4639b2f0
some timer extensions
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
2022-05-02 16:23:19 +02:00
5cbbb53094 some minor improvements
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
- Docs updated, internal architecture improvements
2021-12-21 00:30:28 +01:00
e3cdd21b41
added link to new example
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
2021-12-20 23:51:37 +01:00
9a5c9ac53c update changelog and manifest
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
Rust/va108xx-hal/pipeline/pr-main This commit looks good
- Clippy fixes
2021-12-20 11:39:30 +01:00
a8b484d66f UART reception and echo reply now working
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
- Important bugfix in UART: use `modify` instead of `write` when enabling
  or disabling TX or RX
- Extend RTIC example application. Reply handling is dispatched to lower
  priority interrupt
2021-12-20 11:25:00 +01:00
d5b12c8343
some fixes for manifest file
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
2021-12-19 14:25:15 +01:00
f376a43f41
Major refactoring
Some checks failed
Rust/va108xx-hal/pipeline/head There was a failure building this commit
- Improved IRQ handling, which makes most unsafe unmask operations
  in user code absolete
- Add first UART RX handlers which use an IRQ
2021-12-19 14:18:10 +01:00
dc2426a905
make clock enable function inline
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
2021-12-18 15:48:14 +01:00
a1c0fb90e0
update example link
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
2021-12-12 23:04:21 +01:00
fb158caf6e
HAL update
All checks were successful
Rust/va108xx-hal/pipeline/head This commit looks good
Rust/va108xx-hal/pipeline/pr-main This commit looks good
- SPI: Clear TX and RX FIFO for transfers
- Added `port_mux` function to manually select function for pins
2021-12-12 14:21:49 +01:00
063a7a56e5
init blockmode was not set 2021-12-11 17:45:06 +01:00
659b7e8f27
Replaced Hertz by impl Into<Hertz> completely
Some checks are pending
Rust/va108xx-hal/pipeline/head This commit looks good
Rust/va108xx-hal/pipeline/pr-main Build started...
2021-12-09 23:19:21 +01:00
2de11478fb
updated all example links 2021-12-06 16:02:51 +01:00
5f712b6ab7 added cascade example
- Slight change to CountDownTimer input parameter format
2021-12-06 12:39:13 +01:00
779d5a94ec Timer API now macroless
- Separation of TIM reg and TIM pin IF
- Improvements of API
2021-12-05 23:00:28 +01:00
9af01f3067 Added PWM implementation and example 2021-12-05 17:44:18 +01:00
554b9c8550 Added EDAC API 2021-12-04 22:00:45 +01:00
d4d5bf66e4
applied cargo fmt and fixed link 2021-12-04 21:35:11 +01:00
380872107b
re-exporting i2c address definitions 2021-12-04 21:25:35 +01:00
3886e2f11f First I2C implementation
Initial I2C HAL implementation.
Only the I2cMaster was tested so far, I2cSlave will be tested next.

Master side was tested with a temerature sensor example application
in the vorago-reb1 crate
2021-12-02 12:05:24 +01:00
7dae33e7ca Merge remote-tracking branch 'origin/main' into develop 2021-12-02 11:55:40 +01:00
71afe3172e
fixes for SPI documentation 2021-11-21 20:24:44 +01:00
4feb74e4a6 SPI improvements / Clock passing update
1. Using `impl Into<Hertz>` instead of Hertz now to increase
   usability for users
2. Update for SPI API to increase usability
2021-11-21 20:18:42 +01:00
283d9d5991 Doc fixes and SPI block mode support
- Various smaller fixes for documentation
- Added support for SPI blockmode
2021-11-21 14:04:17 +01:00
cbc7c88112
Added SPI implementation
- First SPI HAL implementation for blocking mode
- Added example for SPI as well which uses loopback mode
  and regular mode
2021-11-20 23:57:08 +01:00
2a9225fda5 added blocking delay functions
- DelayUs and DelayMs trait implementations for CountDown timer
  peripherals
- Bugfix for wait function
2021-11-20 15:09:12 +01:00
c07d937c12
added a few inline always directives 2021-11-13 18:58:24 +01:00
de0e000af3
tiny doc tweak 2021-11-13 15:03:50 +01:00
af5a831579 Added GPIO IRQ interface, refactoring
- Adds the IRQ interface to configure interrupts on output and input pins
- Moved the `FilterClkSel` struct to the `clock` module, reexporting in `gpio`
- Added function to set clock divisor registers
- Clearing output state at initialization of Output pins
- Added utility function to set up millisecond timer
2021-11-13 14:51:24 +01:00
04830087da GPIO optimization and tweaks
- Some functions marked inline
- Doc updated
2021-11-11 20:01:40 +01:00
6c9d9f7dfa
smaller tweaks and updates 2021-11-11 18:18:40 +01:00
63be6ed5fe Refactored GPIO module
- The GPIO module uses type-level programming now
- Implementation heavily based on the ATSAMD GPIO HAL:
  https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/gpio/v2/index.html
- Changes to API, but no passing of peripheral references necessary
  anymore. All examples and tests updated accordingly
2021-11-11 17:39:26 +01:00
b18e32e0cc Rust edition bumped & UART implementation
- Also adds UART example
2021-11-09 18:37:52 +01:00
f3d71cf0f9
Timer and Clock modules added
- Clock module to set and retrieve system clock which can have
  varying frequencies. Also allows enabling peripheral clocks
- Prelude updated
- Common time types added, based on stm32f1xx HAL implementation
- Basic timer implementation added
2021-11-08 01:40:01 +01:00
f153732fcc
applied cargo fmt 2021-11-08 01:04:00 +01:00
021efc5a5a
Update GPIO code 2021-11-08 01:01:44 +01:00
1e1b7f3c9f
fix prelude naming 2021-11-06 16:19:38 +01:00
9020fc92d0
Refactored parts of the GPIO implementation 2021-11-06 16:16:53 +01:00
9181e61e70
Added first GPIO implementation
- First GPIO implementation based on the stm32f0xx amd stm32f1xx
HAL implementations for the HAL module
2021-11-06 01:27:04 +01:00
3ae5b0e27d
init commit 2021-11-03 23:11:59 +01:00