v1.9.0 #175
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For all related PRs see: https://egit.irs.uni-stuttgart.de/eive/eive-obsw/milestone/17 .
There are a lot of changes because there has not been an intermediate release for a longer period of time.
This is the release with most/all GPIO pins, SPI, I2C and UART peripherals designated and named, the FPGA configuration becoming more stable, and most basic device handlers implemented.
It will be the last release before system components are added.
v1.9to v1.9.0